Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6667560 B2
Publication typeGrant
Application numberUS 08/863,848
Publication dateDec 23, 2003
Filing dateMay 27, 1997
Priority dateMay 29, 1996
Fee statusPaid
Also published asEP0810655A2, EP0810655A3, US20020000652
Publication number08863848, 863848, US 6667560 B2, US 6667560B2, US-B2-6667560, US6667560 B2, US6667560B2
InventorsJing S. Goh
Original AssigneeTexas Instruments Incorporated
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Board on chip ball grid array
US 6667560 B2
Abstract
A package for an integrated circuit includes a circuit board 122 for mounting the integrated circuit 114 having a first surface and a second surface, a connection device positioned on the first surface of the circuit board 122 for electrically connecting the integrated circuit 114 and the integrated circuit 114 being positioned on the second surface of the integrated circuit 114.
Images(5)
Previous page
Next page
Claims(8)
What is claimed:
1. A package for an integrated circuit having wires for electrial connection, comprising:
a circuit board for mounting the integrated circuit having a first surface and a second surface;
a connector device positioned on the first surface of the circuit board for electrically connecting the integrated circuit by said wires;
said integrated circuit being positioned on the second surface of said circuit board; and
said wires being centrally positioned on said integrated circuit to abut said first surface of the circuit board.
2. A package for an integrated circuit, as in claim 1, wherein said integrated circuit is attached to said circuit board by epoxy.
3. A package for an integrated circuit, as in claim 1, wherein said integrated circuit is attached to said circuit board by adhesive tape.
4. A package for an integrated circuit, as in claim 3, wherein said adhesive tape is polymide tape.
5. A package for an integrated circuit, as in claim 1, wherein said circuit board has a hole to place wires to connect the integrated circuit and said connection device.
6. A package for an integrated circuit, as in claim 1, wherein said connection device includes a solder ball.
7. A package for an integrated circuit, as in claim 1, wherein the package further comprises:
a sealing material to seal the integrated circuit, and wherein the sealing material form a flush surface with a surface of the integrated circuit.
8. A package for an integrated circuit, as in claim 1, wherein the package further comprises a sealing material to completely encapsulate the integrated circuit.
Description

This application claims priority under 35 USC §119(e)(1) provisional application No. 60/018,579 filed May 29, 1996.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to packaging semiconductor devices, and more particularly to packaging board on chip (BOC) devices.

BACKGROUND OF THE INVENTION

The semiconductor technology has shown a general trend towards the dramatic increase in integrated circuit speed and density. Both of these trends are fueled by a general reduction in device (active element) geometries. As semiconductor devices becomes smaller, the distances between them on a semiconductor die become, and parasitics (such as parasitic capacitances) and switching currents become smaller. In technologies, such as CMOS, where overall current draw and switching speed characteristics are dominated by the effects of parasitics, the result is a reduction in total power consumption at the same time as switching speed is improved. Overall speed is further improved by the reduction in signal propagation time between active devices (e.g., transistors), resulting from the shorter distances involved. In today's high speed integrated circuitry based on sub-micron geometries, delays in the tens or hundreds of picoseconds can be appreciable.

Typically, integrated circuit dies (chips, or semiconductor dies) are diced (cut apart, or singulated) from a semiconductor wafer and are separated into integrated circuit packages which have pins, leads, solder (ball) bumps, or conductive pads by which electrical connections may be made from external systems to the integrated circuit chip. These packages are then typically applied to circuit board assemblies including systems of interconnected integrated circuit chips.

The aforementioned dramatic improvements in integrated circuit speed and density have placed new demands on integrated circuit assemblies, both at the chip and circuit board levels. Without attendant improvements in these areas, much of the benefit of high device speed is lost. Wiring propagation delays and transmission line effects, in integrated circuit packages and on circuit board assemblies, which were once negligible are now significant factors in the overall performance of systems based on high-speed integrated circuitry. In order to achieve the potential higher system level performance opportunities afforded by the new high density technologies, it is necessary to reduce the amount of signal propagation time between integrated circuits.

Another significant factor in achieving high system level performance is signal drive capability. Longer signal paths are susceptible to noise, cross-talk, etc., and require low impedance, high current drive circuits on the integrated circuit chips (dies). Such circuits tend to occupy large portions of the die area, either reducing the area available for other circuitry or increasing the overall die size, and can introduce significant delays of their own. Clearly, shorter signal paths and their attendant low signal drive current requirements are desirable to achieve high performance.

In the prior art, a number of high density chip assemblies and packages have been proposed and implemented. One such technique is commonly known as “chip-on-board” technology, whereby integrated circuit dies are bonded directly to die mounting areas on a circuit board substrate, for example, ceramic, fiberglass, etc., and are wire bonded (with thin “bond wires”) to traces on the circuit board in areas adjacent to the edges of the dies. The elimination of the traditional integrated circuit package permits chips to be placed much closer together than would otherwise be possible, thereby shortening signal paths and reducing delays.

SUMMARY OF THE INVENTION

The present invention reduces inductance that is induced between wires and internal leads. Additionally, the present packaging arrangement provides one package for all applications. The package for the present invention provides short traces leading to favorable impedance coupling. These short wires are designed to reduce electrical impedance important for the operation of high speed devices, such as the synchronous DRAM. Additionally, the present invention eliminates wire shorts to the bus bar and eliminates T/F. Additionally, the present invention eliminates the use of ultra-advance molding equipment development. Additionally, the present invention provides a true chip size package, which leads to improved mapping density. Additionally, the present invention eliminates the bent leads. Lastly, the present invention eliminate noise due to cross-talk and improves the delays associated with longer wires.

The present invention includes a package for an integrated circuit, including a circuit board for mounting the integrated circuit having a first surface and a second surface, a connector device positioned on the first surface of the circuit board for electrically connecting the integrated circuit, and the integrated circuit being positioned on the second surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a sideview of package die with potting topside;

FIG. 2 illustrates a topview of the package with a stitch design;

FIG. 3 illustrates a sideview of another package die with molding topside;

FIG. 4 illustrates the topview of the same package die;

FIG. 5 illustrates another package die with molded topside;

FIG. 6 illustrates a variation of the package of FIG. 5 with potter topside;

FIG. 7 illustrates another sideview of another package with potter topside;

FIG. 8 illustrates another sideview of another package die with molding topside;

FIG. 9 illustrates the board and solder bumps; and

FIGS. 10-14 illustrates a process of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates that solder balls 100 are positioned along the longitudinal edges of printed circuit board 122. To provide the maximum spacing between the individual solder balls, the solder balls may be positioned along the outer edges of the printed circuit board 122. The number of the solder balls 100 correspond to the number of connections to the semiconductor die 114. The semiconductor die 114, which has been previously cut or diced is mounted to the printed circuit board 122 by an attachment apparatus, for example, polymide tape or any adhesive material suitable to attach the semiconductor die 114 to the printed circuit board 122. Advantageously, the semiconductor die 114 is the type with connections along the longitudinal axis of the semiconductor die. The electrical connection may be positioned along the central axis of the semiconductor die 114. The solder balls 100 are connected to the semiconductor die 114 by wires 118 which may be made of material gold and traces (not. shown). These wires 118 are attached to the semiconductor die on the side of the semiconductor die 114 that faces or abuts the printed circuit board 122. The wires 118 extend from the semiconductor die 114 through a hole 120 of the printed circuit board and are attached to traces which run along or through the printed circuit board to the solder balls. The hole through the printed circuit board 122 may be positioned at the central longitudinal axis of the printed circuit. The semiconductor die 114 and wires 118 are protected from external objects by the elements by sealing material, such as the epoxy resin to form the chip-on-board (COB) semiconductor device. Although, top and bottom have no absolute meaning, for purposes of this application, the side of the printed circuit board 122 with the solder balls 100 and away from the semiconductor die 114 is referred as the top portion while the bottom portion of the printed circuit board 122 is the side opposite to the solder balls 100 and the same side as the semiconductor die 114.

The sealing material 110, which is formed on the top surface of the printed circuit board 114 to cover the wires 118 and the hole 120 protects the wires and has a general curved shape. The bottom sealing material 112 forms between the printed circuit board 122 and the semiconductor die 114 to encapsulate the adhesive means 116 and the wires 118 and further encapsulate the sides of the semiconductor die 114. The bottom of the bottom sealing material 112 is approximately flush with the bottom of the semiconductor die 114.

FIG. 2 illustrates that the top sealing material 110 is formed around the wires 118 and are generally perpendicular to the longitudinal axis of the printed circuit board 122. The height of the packaged device is very compact and approximately only 42 mills. The wires 118 are very short and eliminate inductance. The height between the bottom of the printed circuit board 122 and the bottom of the semiconductor die 114 is approximately 14 mills while the height from the top of the printed circuit board 122 to the top of the solder balls 100 is approximately 20 mills. The semiconductor die 114 is spaced approximately 1 to 3 mils from the bottom of the printed circuit board 122 depending on the type/method of die attached used.

FIG. 3 illustrates a variation of the package of FIGS. 1 and 2, in that the top sealing material 124 has more angular shape with sloping sidewalls. The topview illustrates that the sealing material 124 has an approximately rectangle shape.

Turning now to FIG. 5, FIG. 5 illustrates that the bottom sealing material 126 is not flush with the bottom of the semiconductor die 114 and entirely encapsulates the semiconductor die 114 including the bottom surface of the semiconductor die 114. This improves the protection of the semiconductor die 114, but increases the overall height to approximately 50 mills.

FIG. 6 illustrates that the top sealing material is a curved top sealing material 110. The overall height of this package is approximately 50 mils.

FIG. 7 illustrates that the semiconductor die 114 is not enclosed on either the bottom or sides by a sealing material. The adhesive material 116 extends from the hole 120 to the outermost side of the printed circuit board 122. This extension of the adhesive material 116 provides a stable mounting platform for the semiconductor die 114.

In FIG. 8, the angular top sealing material 124 is used with the extended adhesive material 116. The dimensions of the semiconductor die 114 are approximately the same as the printed circuit board 122 along the longitudinal axis of the printed circuit board 122.

FIG. 9 illustrates a construction in the form of a structure of the printed circuit board 122 with the solder balls. The structure includes a hole 200 formed by etchings other suitable process and extends from the top surface of the printed circuit board 122 into the printed circuit board 122 down to and exposing conductor 202. Conductive material 204, for example, gold or copper is plated on the walls of the hole 200. A conductive plug 206 is deposited in to hole 200 forming a conductive via from the surface of the printed circuit board 122 to the conductor 202. Contact 208 is electrically conductive to plug 206 and is formed on the top surface of the printed circuit board.

FIGS. 10-14 illustrates a process for the construction of device in accordance with the principals of the present invention.

A hole 120 is formed along the central longitudinal axis of the printed circuit board 122. Adjacent to the hole 120 and on the bottomside of the printed circuit board 122, adhesive material 116 is placed. Semiconductor die 114 is positioned next on the adhesive means 116 as illustrated in FIG. 12.

In FIG. 13, wires 118 are formed from the semiconductor die 114 to the conductors located in the printed circuit board 122 by wire bonding machines (not shown). As illustrated in FIG. 14, a top sealing material 124 protects the wires while a bottom sealing material 126 protects the semiconductor die. These top and bottom sealing materials are formed by molding machine (not shown). Thus, the wires are very short and eliminate inductance resulting from longer wires and provides favorable impedants and coupling to the semiconductor die. Furthermore, no bus bar is needed.

The present invention further eliminates or minimizes bent leads resulting from the wire placement process.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3179913Jan 25, 1962Apr 20, 1965Ind Electronic Hardware CorpRack with multilayer matrix boards
US3370203Jul 19, 1965Feb 20, 1968United Aircraft CorpIntegrated circuit modules
US3459998Aug 15, 1967Aug 5, 1969Bell Telephone Labor IncModular circuit assembly
US3904934Mar 26, 1973Sep 9, 1975Massachusetts Inst TechnologyInterconnection of planar electronic structures
US4288841Sep 20, 1979Sep 8, 1981Bell Telephone Laboratories, IncorporatedDouble cavity semiconductor chip carrier
US4502098Feb 8, 1982Feb 26, 1985Brown David FCircuit assembly
US4574331May 31, 1983Mar 4, 1986Trw Inc.Multi-element circuit construction
US4646128Apr 8, 1985Feb 24, 1987Irvine Sensors CorporationHigh-density electronic processing package--structure and fabrication
US4721995Oct 4, 1985Jan 26, 1988Fujitsu LimitedIntegrated circuit semiconductor device formed on a wafer
US4727410Nov 23, 1983Feb 23, 1988Cabot Technical Ceramics, Inc.High density integrated circuit package
US4823233Dec 24, 1984Apr 18, 1989Dowty Electronic Components LimitedCircuit assembly
US4833568Jan 29, 1988May 23, 1989Berhold G MarkThree-dimensional circuit component assembly and method corresponding thereto
US4862249Apr 17, 1987Aug 29, 1989Xoc Devices, Inc.Packaging system for stacking integrated circuits
US4868712Oct 27, 1987Sep 19, 1989Woodman John KThree dimensional integrated circuit package
US4953005Apr 15, 1988Aug 28, 1990Xoc Devices, Inc.Packaging system for stacking integrated circuits
US5016138Sep 18, 1989May 14, 1991Woodman John KThree dimensional integrated circuit package
US5019945Jul 25, 1989May 28, 1991Trw Inc.Backplane interconnection system
US5091251May 24, 1990Feb 25, 1992Tomoegawa Paper Co., Ltd.Adhesive tapes and semiconductor devices
US5148265Mar 21, 1991Sep 15, 1992Ist Associates, Inc.Semiconductor chip assemblies with fan-in leads
US5227232Jan 23, 1991Jul 13, 1993Lim Thiam BConductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5235496Apr 15, 1992Aug 10, 1993Texas Instruments IncorporatedDevice for packaging integrated circuits
US5239448Oct 28, 1991Aug 24, 1993International Business Machines CorporationFor providing function in a computer system
US5336928Sep 18, 1992Aug 9, 1994General Electric CompanyHermetically sealed packaged electronic system
US5384689Dec 20, 1993Jan 24, 1995Shen; Ming-TungIntegrated circuit chip including superimposed upper and lower printed circuit boards
US5444296Nov 22, 1993Aug 22, 1995Sun Microsystems, Inc.Ball grid array packages for high speed applications
US5491362Aug 13, 1993Feb 13, 1996Vlsi Technology, Inc.Package structure having accessible chip
US5523622Sep 25, 1995Jun 4, 1996Hitachi, Ltd.Semiconductor integrated device having parallel signal lines
US5562971Apr 7, 1995Oct 8, 1996Hitachi Chemical Company, Ltd.Multilayer printed wiring board
US5625944Jun 7, 1995May 6, 1997Interconnect Systems, Inc.Methods for interconnecting integrated circuits
US5677566 *May 8, 1995Oct 14, 1997Micron Technology, Inc.Semiconductor chip package
US5683942 *May 25, 1995Nov 4, 1997Nec CorporationMethod for manufacturing bump leaded film carrier type semiconductor device
US5777391 *Dec 11, 1995Jul 7, 1998Hitachi, Ltd.Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof
US5798567Aug 21, 1997Aug 25, 1998Hewlett-Packard CompanyBall grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
US5821605Aug 2, 1995Oct 13, 1998Lg Semicon Co, Ltd.LOC semiconductor package
US5834336Mar 12, 1996Nov 10, 1998Texas Instruments IncorporatedBackside encapsulation of tape automated bonding device
US5846852Sep 15, 1997Dec 8, 1998Motorola, Inc.Process for mounting an electronic component to a substrate and process for spray-cooling the electronic component mounted to a substrate
US5866949Oct 8, 1997Feb 2, 1999Minnesota Mining And Manufacturing CompanyChip scale ball grid array for integrated circuit packaging
US5869356Mar 17, 1998Feb 9, 1999International Business Machines CorporationMethod and structure for constraining the flow of incapsulant applied to an I/C chip on a substrate
US5886399Sep 18, 1996Mar 23, 1999Sony CorporationLead frame and integrated circuit package
US5889333Sep 8, 1997Mar 30, 1999Fujitsu LimitedSemiconductor device and method for manufacturing such
US6013946Mar 31, 1997Jan 11, 2000Samsung Electronics Co., Ltd.Wire bond packages for semiconductor chips and related methods and assemblies
US6049129Dec 19, 1997Apr 11, 2000Texas Instruments IncorporatedChip size integrated circuit package
DE9417734U1Nov 8, 1994Mar 16, 1995Zentr Mikroelekt Dresden GmbhHalbleiteranordnung für Chip-Module
EP0392242A2Mar 26, 1990Oct 17, 1990International Business Machines CorporationModule assembly with intergrated semiconductor chip and chip carrier
EP0698920A2Aug 24, 1995Feb 28, 1996Texas Instruments IncorporatedA method for assembling integrated circuits upon printed circuit boards
JPH07321244A Title not available
JPS58178529A Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6791194 *Jan 28, 2000Sep 14, 2004Hitachi, Ltd.Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US6815835 *May 16, 2003Nov 9, 2004Micron Technology Inc.Single sided adhesive tape for compound diversion on BOC substrates
US6949820Jun 2, 2004Sep 27, 2005Infineon Technologies AgSubstrate-based chip package
US7030473Jun 15, 2004Apr 18, 2006Infineon Technologies AgSubstrate-based IC package
US7221571 *Jan 17, 2006May 22, 2007Fujitsu LimitedPackage unit, printed board having the same, and electronic apparatus having the printed board
US7550842Dec 12, 2002Jun 23, 2009Formfactor, Inc.Integrated circuit assembly
Classifications
U.S. Classification257/784, 257/E23.039, 257/E23.069
International ClassificationH05K1/18, H01L23/12, H01L23/498, H01L23/495, H01L23/31
Cooperative ClassificationH01L24/48, H01L23/4951, H01L2224/48247, H01L2224/4824, H01L2924/30107, H01L2924/01079, H01L2224/32014, H01L2924/14, H01L23/3114, H01L23/49816, H01L2924/3011, H01L2224/48091, H01L2924/15311, H01L2224/73215, H01L2224/32225
European ClassificationH01L23/498C4, H01L23/495A4, H01L23/31H1
Legal Events
DateCodeEventDescription
May 23, 2011FPAYFee payment
Year of fee payment: 8
May 17, 2007FPAYFee payment
Year of fee payment: 4