|Publication number||US6684317 B2|
|Application number||US 10/026,166|
|Publication date||Jan 27, 2004|
|Filing date||Dec 21, 2001|
|Priority date||Dec 21, 2001|
|Also published as||CA2469425A1, CN1606851A, EP1506641A1, US20030120894, WO2003055156A1|
|Publication number||026166, 10026166, US 6684317 B2, US 6684317B2, US-B2-6684317, US6684317 B2, US6684317B2|
|Inventors||Xiaolin Wang, Satish Soman, Benjamin Marshall, Subhasis Pal|
|Original Assignee||Axiowave Networks, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (5), Classifications (6), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to systems and techniques for assigning memory storage addresses to sequential data packets from pluralities of input data line cards, or other sources, being more particularly directed to such addressing for writing the data packets into shared memory selections preferably of an output-buffered switch fabric as of the type described in copending U.S. patent application Ser. No. 09/941,144, entitled: METHOD OF SCALABLE NON-BLOCKING SHARED MEMORY OUTPUT-BUFFERED SWITCHING OF VARIABLE LENGTH DATA PACKETS FOR PLURALITIES OF PORTS AT FULL LINE RATE, AND APPARATUS THEREFOR, filed Aug. 28, 2001 and of common assignee herewith, and such that there is no overlap among the packets and no holes or gaps between adjacent data packets.
While the addressing methodology of the invention may be of more general application as well, it will be illustratively described herein with reference to its preferred and best mode use with output-buffered switch fabrics of the above-mentioned type, wherein a central shared memory architecture is employed, comprised of a plurality of similar successive data memory channels defining a memory space, with fixed limited times of data distribution from the input ports successively into the successive memory cells of the successive memory channels, and in striped fashion across the memory space. This enables non-blocking shared memory output-buffered data switching, with the data stored across the memory channels uniformly. By so limiting the times of storing data from an input port in each successive memory channel, the problem is admirably solved of guaranteeing that data is written into memory in a non-blocking fashion across the memory space and with bounded delay.
This technique, as explained in said copending application, embraces a method of receiving and outputting a plurality m of queues of data traffic streams to be switched from data traffic line card input ports to output ports. A plurality n of similar successive data memory channels, is provided, each having a number of memory cells defining the shared memory space assigned to the m queues. Buffering is effected for m memory cells, disposed in front of each memory channel to receive and buffer data switched thereto from line card traffic streams, and providing sufficient buffering to absorb a burst from up to n line cards. Successive data is distributed in each of the queues during fixed limited times only to corresponding successive cells of each of the successive memory channels and, as before stated, in striped fashion across the memory space, thereby providing the non-blocking shared memory output-buffered data switching I/O (input/output) ports. Each packet from an input port gets an address in the destination queue from an address generator, defining the location in the shared memory in which the packet will be stored. Such use of an output-buffered switch fabric enables packets destined for a queue to come from all input ports; and all these packets are written into the shared memory such that, as before mentioned, there is no overlap among packets and no holes or gaps between adjacent packets. The address of every packet, accordingly, depends upon all the packets that have been previously assigned an address, and the packets must be assigned sequentially.
As an example, the system embodying the shared memory operating with the address generating methodology of the present invention can support minimum 40 byte packets with no impact on the switch fabric performance, receiving from each 10 Gbps port, a 40 byte packet every 40 ns fixed time slot, and with capability to assign addresses for 64 packets every 40 ns, as where all these packets belong to the same queue.
The invention accomplishes this without attempting to push technology as has been proposed in other prior approaches. To the contrary, the present invention develops a parallel processing algorithm, as later detailed, with its address generator being scalable for both port count and bandwidth.
A principal object of the present invention, therefore, is to provide a new and improved address generating methodology particularly, though not exclusively, suited to enable packet addressing in an output-buffered shared memory switch fabric, and by a novel parallel processing scalable approach, and without overlap among the sequentially addressed packets, and with no holes or gaps between adjacent packets.
A further object is to provide a novel address generator for carrying out the method of the addressing technique of the invention, and embodying a ring structure of successively connected subaddress generators, with memory allocation effected sequentially from subaddress generator to subaddress generator along the ring.
Still another object is to provide such novel address generation with successive addressing effected at successive subaddress generators of the ring by adding the current size of packets thereat to the address assignment of the preceding subaddress generator, and with the address of a packet thus depending upon all packets that have previously been assigned an address, and with such assignment occurring sequentially.
Other and further objects will be explained hereinafter and are more particularly detailed in the accompanying claims.
The invention will now be described with reference to the accompanying drawings.
FIG. 1 is a diagram upon an enlarged scale of the address generator ring structure portion of the invention;
FIG. 2 is an explanatory diagram of the execution by all address generators of the ring structure of FIG. 1 of a packet composition functioning for a single queue, wherein super packets are composed or constructed of received data packets, ordered based on time of arrival;
FIG. 3 shows the memory allocation assignment of memory space for each super packet, illustrating the adding of the super packet size to the previous super packet address for use as the starting address when the memory allocation moves to the next subaddress generator, the upper part of the diagram showing address requests, and the lower part, summation expressions illustrating the address offset passed to the next stage at successive time slots;
FIG. 4 is a similar diagram of a packet decomposition function of each subaddress generator, assigning addresses for individual packets in the super packet simultaneously, once the starting address for a super packet has been assigned by a subaddress generator;
FIGS. 5, 6 and 7 correspond, respectively to FIGS. 3, 2 and 4, showing memory allocation for a multiple (two) queue system with address offset passed to the next stage (FIG. 5), packet composition of a two queue system (FIG. 6), and packet decomposition (FIG. 7) of such a two queue system, respectively; and
FIG. 8 of which is an overall block operational diagram of the preferred overall system using the present invention as the addressing generator for the before-described output-buffered shared memory switch fabric;
In summary, however, from one of its important aspects, the invention embraces a method of addressing sequential data packets from a plurality of input data line cards to enable their memory storage in successive shared memory block sections of an output buffered switch fabric, each assigned to a queue dedicated for an output port, that comprises, connecting a plurality of similar subaddress generators successively in a closed ring structure, with each subaddress generator being capable of assigning addresses for predetermined size data byte packets of input data traffic received in a plurality of successive time slots to produce packet composition into super packets that are ordered based on time of arrival; allocating a continuous memory block for a super packet by assigning an initial super packet address in the destination queue from a subaddress generator; thereupon generating the starting address of the next super packet by adding the super packet size to said initial starting address and moving to the next subaddress generator sequentially along the successive subaddress generators of the ring, thereby sequentially allocating memory in the shared memory sections from subaddress generator to subaddress generator along said ring; and, upon the assigning of an address to each super packet, producing packet decomposition at the corresponding subaddress generator by simultaneously assigning addresses for the individual packets in the super packet, based on their arrival order.
Preferred embodiments and best mode configurations are later detailed.
Referring to FIG. 8, an overall system (termed by applicants' assignee as “the Agora ESF” —electronic switch fabric—) is shown comprising the before-described output-buffered shared memory at M, connected to be addressed by the address generator system AGS of the present invention. Before proceeding to describe the complete system, however, it is believed useful to consider first the address-generating system of the present invention.
The before-described address generator ring structure of the address-generating system is illustrated in FIG. 1, having a plurality of subaddress generators AGO through AGn successively connected in a closed ring structure. For the previously described example, each subaddress generator will be capable of assigning addresses for 40 Gbps of input traffic data from the line cards or other data packet sources.
In accordance with the technique of the invention, the entire address assignment is divided into three parts: Packet Composition, Memory Allocation and Packet Decomposition. Packet Composition (FIG. 2) constructs the incoming data packets into “super packets” in which the packets are ordered based on time of arrival. The Memory Allocation (FIG. 3) is a sequential procedure from subaddress generator to subaddress generator along the addressing ring. (AGO to AG1 to AG2, etc. in FIG. 1). This allocates the continuous memory block for a super packet by assigning a starting address, and generates the starting address of the next super packet by adding the current super packet size to that starting address—then moving to the next subaddress generator of the ring. Finally, Packet Decomposition (FIG. 4) assigns the address of each packet in the super packet based on the arriving order. All the subaddress generators of the ring execute the Packet Composition and Packet Decomposition functions concurrently.
As an example, consider the four subaddress generator ring AGO, AG1, AG2, and AG3 of FIGS. 2-4, in which each subaddress generator receives a new packet within address requests in four consecutive fixed time slots represented by respective composed or constructed super packet blocks a0, a1, a2, and a3; b0, b1, b2, and b3; c0, c1, c2, and c3; and d0, d1, d2, and d3; in the queues Qo. Referring to the time graph (“t”) at the right in the figures, the Packet Composition and Memory Allocation function of FIGS. 2 and 3 starts from subaddress generator AGO. At time slot O, only one packet has shown up on subaddress generator AGO, so the super packet contains only one packet. At time slot 1, each subaddress generator has received two packets, shown differentially shaded, composing or constructing the super packet. With the Memory Allocation starting from subaddress generator AGO, when each subaddress generator receives said two-packet super packet, the Memory Allocation moves to subaddress generator AG1, FIG. 3. As Memory Allocation moves along the address generator ring of FIG. 1, the packets that thus far are not yet in any super packets, form a new super packet—each super packet being shown with different shading. Thus Memory Allocation assigns memory space for each super packet. In this example, it assigns address 0 to super packet 0 and then adds the super packet size ao to the starting address, which is going to be used as starting address when Memory Allocation moves to the next subaddress generator. Specifically, at the before mentioned time slot 1, Memory Allocation moves to subaddress generator 1 and assigns a starting address,
to the super packet shaded in FIG. 2. It then adds the super packet size,
to the starting address,
forming the starting address for the next subaddress generator. Every time slot, it moves to the next subaddress generator along the address generator ring, adding the super packet size to the starting address as the starting address of the next subaddress generator. The figure therefore shows Memory Allocation for each subaddress generator for each time slot, and the starting address for the next subaddress generator.
Every time slot along the vertical time axis t, it moves to the next subaddress generator along the address generator ring. The summation blocks illustrate which subaddress generator is performing the memory allocation in each time slot, and the corresponding starting address for the next address generator.
As before stated, the Packet Composition of FIG. 2 and the earlier described Packet Decomposition of FIG. 4 occur concurrently. Turning, therefore, to the Packet Decomposition, as shown in FIG. 4, once the starting address for a super packet is assigned, Packet Decomposition at each subaddress generator assigns addresses for the individual packets in the super packet simultaneously. In this example, a lower-case letter (ao, bo, etc.) represents the packet and its size as before described, and the corresponding capital letter (Ao, Bo, etc.) is used to represent in FIG. 4 the address assigned to the individual packet of the super packet. The starting address of the first super packet in such address generator AGo is Ao=o, assigned to it as the only packet ao, in this super packet and Packet Decomposition. The starting address A1 of the second super packet in AG0 is shown as A1=D3+d3 which is assigned to packet a1. The starting address plus the packet size of a1 will be the address A2 of the next packet a2 in the same super packet, namely, A2=A1+a1, and so on. Each packet of each super packet will get a unique address such that no two packets overlap and no holes or gaps will exist in the shared memory assigned between adjacent packets.
In the algorithmic philosophy thus far described, the Memory Allocation has moved to the next subaddress generator in the ring, every time slot. This, however, is not a requirement since the Memory Allocation period—i.e. the time between two continuous memory allocations at a subaddress generator—is proportional to the maximum size of a super packet. This property makes the parallel processing of address generating of the invention possible and the system scalable in terms of port or subaddress generator count. The latency from packet arrival to address return, however, will increase with the subaddress generator count.
The previously described operation, furthermore, has been illustrated for the case of single queue Q0 for Packet Composition and Packet Decomposition. As before indicated, however, multiple queue systems may also be similarly used, FIGS. 6, 5 and 7 showing Packet Composition, Memory Allocation and Packet Decomposition respectively for multiple queues—in this illustration, a two-queue system illustrating the same algorithmic approach as for the single queue systems of respective FIGS. 2, 3 and 4, detailed above. Many identical address generators may, indeed, be used, each corresponding to a data queue and each starting at different time slots.
In the illustrative two-queue system (Q0, Q1) of FIGS. 6, 5 and 7, the input pattern to each queue will be identical to the previously described operation. The Memory Allocation of FIG. 5 starts with Q0, at time slot 0, and Q1, (differently shaded) at time slot 1. While, moreover, the input pattern of both queues is identical, the super packets of each queue will be different as more particularly shown in FIG. 6. As for the Packet Decomposition of such a multiple queue system (FIG. 7), the method of assigning addresses to the individual packets of a super packet will be the same as described in connection with FIG. 4 for the single queue system. The use of more queues, of course, will result in a larger Memory Allocation period. This, of course, implies that the maximum size and packet and address-assignment latency will increase. In the approach of the method of the invention, as earlier noted, the rate of Packet Decomposition, however, has to match the rate of Packet Composition.
It is now in order to treat with the overall architecture of the address generating system AGS of the invention addressing the before-described preferred non-blocking shared memory output-buffered data switching system M, as of the type of said copending application and represented in FIG. 8. For illustration purposes, two input or ingress ports A and C are shown at the left, with received data packets to be sent to the output or egress port B at the far right. Qn and Qn+1 queues in the shared memory M are illustratively shown dedicated to the output port B.
In operation, received packets AP1 and AP2 arrive from line cards sequentially at input port A. These packets are destined for queue Qn in the shared memory dedicated to output port B. The independently received packet CP1 and CP2 arrive sequentially at input port C, destined for queue Qn in the shared memory. The input port A makes a request for an address to the address-generating system AGS of the invention, earlier described, for illustrative packets AP1 and packet AP2, as described in said copending application.
Similarly, ingress port C makes request for an address to AGS for packets CP1 and CP2. These packets AP1, AP2, CP1 and CP2 can be of different sizes.
The address requests can happen simultaneously or in any order, and the address generator AGS of the invention processes these requests from port A in the required time and generates addresses A1 and A2 for input port A in the manner before detailed, and processes the requests from port B also in the required time, generating addresses C1 and C2 for input port C.
The addresses A1, A2 are returned to input port A and the addresses C1 and C2 are independently returned to input port C and this can happen in any order. Packets AP1 and AP2 which are waiting at input port A to get their addresses now travel to the shared memory M with their corresponding address tags of A1 and A2; and similarly, Packets CP1 and CP2 which are waiting at port C to get their addresses, now travel to the shared memory with their corresponding address tags of C1 and C2. The shared memory system carries these packets in non-blocking fashion and these packets are stored in queue Qn dedicated to output port B, completing the write operation of packets into the shared memory as more fully detailed in said copending application.
The addresses A1, A2 and C1, C2 need not be contiguous addresses in Qn since there can be packets from other input or ingress ports that may occupy the regions between A1, A2, C1, C2. The output or egress port B is programmed to drain queue Qn based on its bandwidth allocation −20% as illustrated in this example of FIG. 8. According to this rate, the output port B makes a data request for data from queue Qn and the shared memory subsystem M returns appropriate data from queue Qn in appropriate time to the output port B. Other egress ports may also be active simultaneously with the shared memory handling of all these read requests appropriately. In due time, packets AP1, AP2, CP1, CP2 are drained out by the output port B, completing their intended travel from input ports A and C to output port B as per allocated bandwidth of Qn for output port B. This system performs these operations for 64 OC-192 in current experimental implementation of the assignee of the present invention, but the scheme, as before explained, is scalable with existing semiconductor technology and to more than 64 OC-192 ports.
Further modifications will also occur to those skilled in this art, and such are considered to fall within the spirit and scope of the invention as defined in the appended claims.
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|International Classification||H04L12/933, H04L12/935|
|Cooperative Classification||H04L49/3027, H04L49/103|
|Sep 27, 2002||AS||Assignment|
Owner name: AXIOWAVE NETWORKS, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, XIAOLIN;SOMAN, SATISH;MARSHALL, BENJAMIN;AND OTHERS;REEL/FRAME:013375/0638
Effective date: 20011219
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Owner name: WEST LANE DATA LLC, NEVADA
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