US 6732126 B1 Abstract A programmable and configurable datapath unit (DPU) includes a configuration of single-bit multi-function processing units (PUs). The DPU can perform any of a variety of functions depending on the control applied to each PU. Functionality can be increased by utilizing multiplexers to direct data into, out of, and through each DPU dependent on the selected function being performed. Datapath units can also be configured and interconnected to form larger datapath circuits, arrays, and systems so as to increase the data throughput of the datapath system. A configurable and programmable datapath array includes rows of datapath units which can be interconnected to provide DPU circuits having varying input operand widths and functions. A datapath system can be constructed with a plurality of arrays of DPUs to further increase system data throughput.
Claims(31) 1. A datapath unit for operating on input data according to a given operation and to generate output data, said datapath unit comprising:
a configuration of multi-function processing units interconnected into at least a row of processing units, each processing unit being controllable to perform a selected one of a plurality of operations, wherein no more than N processing units are required to perform some of the plurality of operations on first and second N-bit operands; and
a control input, coupled to the configuration of multi-function processing units, to dynamically (re)configure at least a subset of the multi-function processing units to perform any operation from a set of operation including an arithmetic operation, a logic operation, a conditional arithmetic operation and a conditional logic operation.
2. The datapath unit as described in
3. The datapath unit as described in
4. A datapath circuit including the datapath unit as described in
5. The datapath unit as described in
6. The datapath unit as described in
7. A datapath unit for operating on input data according to a given operation and to generate output data, said datapath unit comprising:
a configuration of multi-function processing units interconnected into at least two rows of processing units, each processing unit being controllable to perform any of a plurality of operations from a set of operations including arithmetic operations, logic operations, conditional arithmetic operations and conditional logic operations, wherein no more than N processing units in each of the at least two rows are required to perform some of the plurality of operations on first and second N-bit operands; and
a plurality of path selection means for determining the dataflow path into, through, and out of said configuration dependent on said selected operation.
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9. The datapath unit as described in
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18. A datapath circuit for operating on input data according to a given operation and to generate output data, said datapath circuit comprising:
a plurality of datapath units, each datapath unit including a configuration of multi-function processing units interconnected into at least two rows of processing units, each processing unit of a given datapath unit being controllable to perform any of a plurality of operations from a set of operations including arithmetic operations, logic operations, conditional arithmetic operations and conditional logic operations, wherein the number of processing units in each of said path units determines an associated datapath input operand bit width of said datapath units, wherein no more than 8ΧN processing units are required to perform the plurality of operations on first and second N-bit operands, and said datapath units each including a plurality of path selection means for determining the dataflow path into, through, and out of said configuration dependent on said selected operation;
wherein said plurality of datapath units include ports for connecting to other of said datapath units so as to form said datapath circuit having a wider input operand bit width than said associated input operand bit width; and
wherein said plurality of datapath units perform the same selected operation.
19. The datapath circuit as described in
wherein ports of four rows of four adjacent datapath units are interconnected to form an array of sixteen datapath units which perform a first step of a 16Χ16 bit multiplication operation, and wherein additional circuitry performs a second step of said 16Χ16 bit multiplication operation.
20. The datapath circuit as described in
21. A datapath circuit for operating on input data according to a given operation and to generate output data, said datapath circuit comprising:
a plurality of datapath units each including a configuration of multi-function processing units interconnected into at least a row of processing units, each processing unit being controllable to perform any of a plurality of operations from a set of operations including arithmetic operations, logic operations, conditional arithmetic operations and conditional logic operations, wherein the number of processing units in each of said datapath units determines an associated datapath input operand bit width of said datapath units, wherein no more than N processing units are required to perform some of the plurality of operations on first and second N-bit operands;
wherein said plurality of datapath units include ports for connection to other of said datapath units so as to form said datapath circuit having a wider input operand bit width than said associated input operand bit width; and
wherein said plurality of datapath units are programmable to perform the same selected operation.
22. The datapath circuit as described in
23. A configurable programmable datapath system having an associated bus width, said datapath system comprising:
an array of datapath units, each datapath unit including a configuration of multi-function processing units, each processing unit of a given datapath unit and programmable to perform any of a plurality of operations from a set of operations including arithmetic operations, logic operations, conditional arithmetic operations and conditional logic operations, wherein the number of processing units in each of said datapath units determines an associated datapath input operand bit width of said datapath units, wherein no more than N processing units are required to perform some of the plurality of operations on first and second N-bit operands;
said datapath units being interconnectable so as to form datapath circuits having an associated input operand bit width greater than said associated input operand bit width of said datapath unit;
said array being configurable into a combination of groups of interconnected datapath units; and
said array being programmable to perform at least one operation by applying control signals to said individual datapath units and groups of datapath units.
24. The datapath system as described in
25. The configurable programmable datapath system as described in
26. An apparatus comprising:
a dynamically adaptive datapath unit including a plurality of multi-function processing units, selectively coupled in one or more row(s) of processing units, each processing unit being controllable to perform any of a plurality of arithmetic operations, logic operations, conditional arithmetic operations and conditional logic operations; and
a control input, coupled with the dynamically adaptive datapath unit, to receive control signal(s) during operation of the apparatus to dynamically (re)configure one or more of the plurality of multi-function processing units, wherein the control signals selectively modify one or more of the functional operation of the datapath unit, the number of multi-function processing units enabled, and a bandwidth of the datapath unit.
27. An apparatus according to
28. An apparatus according to
29. An apparatus according to
additional dynamically adaptive datapath units, wherein multiple dynamically adaptive datapath units are simultaneously controlled by the received control signal(s) to function together to form a datapath circuit having a greater datapath input operand than a single datapath unit.
30. An apparatus according to
31. An apparatus according to
Description 1. Field of the Invention The present invention relates to datapath circuits in computing systems. 2. State of the Art Computing systems typically include a datapath for operating on data within the system. In general, the datapath of a computing system includes functional blocks (implemented in either software or hardware) each dedicated to performing a single function. FIG. 1 shows an example of a simplified datapath system having a typical set of functional blocks including an adder block, an incrementor block, logic function blocks (each performing a different logic function), a barrel shifter block. A common bus having a fixed width couples a dataword to the inputs of the functional blocks wherein only one of the outputs of functional blocks is multiplexed to the output of the datapath. One problem with this design is that the datapath system is exclusively dedicated to the current operation it is performing such that only a single dataword can be operated on by a single functional block at one time thereby causing a bottleneck at the input of the datapath. In the field of communications in which high frequency real-time data is processed, a bottleneck at the input of the datapath represents a significant reduction in overall system performance. Alternatively, more functional blocks can be added, however, this represents an increase in design size. In addition, since the common input bus is a fixed width, if a dataword having a width that is smaller than the common bus width is processed by the datapath only a portion of the common bus width is used and the remainder is wasted resulting in an inefficient utilization of bandwidth. Finally, in prior art systems the bus width into the datapath becomes the limit of your data throughput. For instance, if you have a 32-bit bus width into the datapath and it is desired to transfer 64-bits, it would be necessary to perform this in two transfer operations. The present invention is a system and method of designing a configurable datapath which allows for a variable width datapath and which is programmable so as to perform a variety of data functions using the same datapath unit. A programmable and configurable datapath unit (DPU) includes a configuration of N interconnected single-bit multi-function processing units (PUs) configured into at least a row of PUs. The PUs are controlled by the same control signal such that the datapath unit is programmable to perform a selected N-bit function dependent on the control signal. The DPU is configurable in that it can be interconnected with other DPUs to increase its data throughput. In one embodiment each PU is implemented as a modified adder, each having at least first and second single-bit inputs, a carry input, a control signal input, a carry output, and a sum output. In this embodiment, the adders are interconnected such that the carry output of a given PU in the configuration is coupled to the carry input of the adjacent PU in the configuration. Each of the adders are implemented with logic gates such that intermediate logic operation resultants can be obtained from each adder. The intermediate operation resultants are internally multiplexed to the sum output port of the adder along with the addition resultant. The control applied to the control input of each adder selects which resultant is internally multiplexed to the sum output port of each PU. Each PU can also include boolean logic circuitry for performing other logic functions which are multiplexed to its sum output port. In one embodiment, the DPU is controlled to perform any of the following functions including addition, subtraction, multiplexing, incrementing, standard and custom logic functions, and conditional operations. In another embodiment, multiplexers are used to direct input and output data through each PU dependent on the selected function being performed. The DPU input operand width is dependent on the number of single-bit PUs in a given row. In accordance with a system and method of the present invention, more than one DPU can be interconnected and programmed to form a datapath circuit having a wider input/output bit operand. In one embodiment, each individual DPU has four single-bit PUs in a single row so that it can be combined with other similar DPUs to form 4(n)-bit datapath circuits. In accordance with another system and method of the present invention, more than one DPU is configured into an array. Groups of DPUs are interconnected and programmed to form multiple datapath circuits. The datapath circuits, in turn, are interconnected to form a datapath system made-up of the multiple datapath circuits each capable of performing a different function and having a different input and output operand widths. In one embodiment, the array comprises eight DPUs in each row and the array includes 32 rows. In another embodiment, the DPU is designed so that it can be configured to perform a multiplication function in addition to standard and customized logic functions, conditional functions, and arithmetic functions. The DPU includes an array of eight single-bit modified adders, having four adders in a top row and four adders in a bottom row so as to form four pairs of stacked adders. The DPU further includes sets of multiplexers for directing the dataflow through the configuration of adders dependent on the function being performed by the DPU. The DPU is adapted for stacking and interconnecting rows of DPUs to form an array of DPUs which performs a first step of the multiplication operation. Additional adder circuitry performs a second step of the multiplication operation. In one embodiment a portion of a 16Χ16 bit multiplication circuit is formed by stacking and interconnecting 4 rows of DPUs, each row including 4 DPUs. The present invention may be further understood from the following written description in conjunction with the appended drawings. In the drawings: FIG. 1 is a prior art datapath system; FIG. 2A is one embodiment of a datapath unit (DPU) in accordance with the present invention; FIG. 2B is one embodiment of a datapath circuit in which two DPUs are connected; FIG. 2C shows a datapath system implemented with a plurality of configureable and programmable arrays of datapath units; FIGS. 2D-2F show different configurations of interconnecting and programming rows of DPUs in an array of DPUs according to the present invention. FIG. 2G is one embodiment of a single-bit processing unit (PU) embodied as a modified adder; FIG. 3A shows one embodiment of the selective application of the operands to the PUs of the present invention; FIG. 3B shows a PU circuit implementation for performing a absolute value operation (ABS); FIG. 3C shows a PU circuit implementation for performing a conditional subtraction (CSUB); FIG. 3D shows a PU circuit implementation for performing a MAX or MIN operation; FIG. 4 shows a second embodiment of the DPU of the present invention adapted to perform a multiplication operation; FIG. 5A shows a 16Χ16 bit multiplier implemented with a 4Χ4 array of DPUs; FIG. 5B shows a block diagram of two rows of DPUs and their associated PUs in the 4Χ4 array of DPUs shown in FIG. 5A; and FIG. 5C shows interconnections of the sumout values and carryout values between rows of PUs in the 4Χ4 array of DPUs shown in FIG. A first embodiment of the datapath unit (DPU) is shown in FIG. 2A which includes N=4 multi-function processing units (PUs) each having two single bit inputs A(n) and B(n) (n=0-3), a carry-in input (C The same control signal, DPU ctrl, applied to each PU which programs the DPU to perform a given function. In one embodiment, the control signal is derived from an opcode in a computing system. The DPU, dependent on the DPU ctrl signal, performs a selected operation on all or some of the input operands A, B, and Cin and outputs a resultant value to both or one of the S and Co outputs. Specifically, in response to the DPU ctrl signal, each PU performs the same single bit function on their single bit input A, B, and Cin operands. For instance, if DPU ctrl signal corresponds to an AND logic operation, the following simultaneous operations are performed on 4-bit A and B operands: PU( PU( PU( PU( It should be noted that the Cin and C(out) values are not used when performing the above simple logic functions, as well as all other operations not involving addition, subtraction, incrementing, and decrementing. As a result, multiplexer In the case in which the DPU ctrl signal corresponds to an operation involving addition, subtraction, incrementing, and decrementing, a Cin value is provided by multiplexer Hence, in the case in which the DPU shown in FIG. 2A is controlled to perform, for example, an addition operation between 4-bit A and B operands in which Cin( PU( PU( PU( PU( In accordance with another embodiment of the present invention, groups of DPUs are configured together to form a datapath circuit having a greater datapath input operand than the single DPU shown in FIG. FIG. 2C shows an embodiment of a datapath system implemented with a plurality of configureable and programmable arrays of DPUs FIGS. 2D-2F show different manners in which rows in an array FIG. 2D shows a Row FIG. 2E shows two successive rows, a Row FIG. 2F shows five successive rows, a Row FIG. 2G shows one embodiment of a PU(n) which can perform a plurality of operations in accordance with the present invention. The PUs are implemented as modified adders having three single bit inputs A(n), B(n) and carry-in input, C The PU shown in FIGS. 2A and 2G can perform the following functions as shown below. In some cases additional circuitry is necessary as will be described herein and shown in FIGS. 3A-3D.
The SUB operation is equivalent to performing the corresponding 1's complement addition operation A+invB+1. In this case, Cin is set to 1 and the input B operand is inverted before being applied to the DPU. In one embodiment, the inversion of the B operand is performed external to the DPU where the B operand and the inverse of the B operand is applied to the input of a multiplexer and is selectively coupled to the input of each PU as shown in FIG. The saturated addition operation, SADD, is performed by adding the A and B operands and then checking the results to see if the adder is saturated (i.e., in an overflow/underflow condition). In the case of an overflow, the result is set back to the maximum value and in the case of an underflow condition, the result is set to the minimum value. To implement this operation, the DPU performs the A+B operation and the two most significant bits of the sumout output of the DPU or a row of DPUs are used to select either a MAX value, a MIN value, or the A+B value from the Sumout output of each PU. In particular, if the two most significant bits of the sumout value are equal to 0 then an overflow condition has occurred and the MAX value is selected. If the two most significant bits of the sumout value are equal to 1 then an underflow condition has occurred and the MIN value is selected. Otherwise, the A+B value is selected. In one embodiment, the selection is performed using a multiplexer. The SADDC and SADDCNT operations are performed in the same manner as the SADD operation except that Cin is set as indicated. The saturated substraction operations, SSUB, SSUBC, and SSUBCNT, are implemented by performing a subtraction operation as described for the SUB, SUBC, and SUBCNT operations followed by a saturation check at the end of the operation as described for the saturated addition operations, to select either a MAX, a MIN, or a A−B value. The increment operation, INC, is performed by applying the value to be incremented to the B input and setting the A operand=0 and Cin=1. INCC is performed in a similar manner except the Cin value is set to Cin( The DEC operation is performed by setting Cin=0 and A=1 which results in a 1's complement subtraction of B−A. The DECC operation is performed by setting Cin=Cin( The NEG operation is performed by setting Cin=1, selecting the negated B operand and adding invB+Cin. The NEGC operation is similarly performed except Cin=Cin( The ABS operation is performed by setting Cin=1, selecting the negated B operand, adding invB+Cin, and then selecting either the sumout output of the DPU or the B operand using a multiplexer dependent on whether the highest order bit of the B operand is positive (B[ The conditional subtraction (CSUB) is implemented by performing a subtraction operation (SUB) and then determining if the sumout highest order bit is positive or negative. If the sumout is positive, the sumout result is selected and if sumout is negative, the B operand is selected. FIG. 3C shows one embodiment of a PU circuit implementation utilized to perform the CSUB operation. The CSUBC operation is performed similarly by setting Cin=Cin( The logical operations AND, OR, NAND, NOR, XOR, and XNOR are obtained from within each PU and are multiplexed to the output of the PU using the control signal to select which operation resultant is passed to the S(O) of each PU in the DPU. The PASSA and PASSB operations which pass either the A or B operands through the DPU can be implemented is several manners. For instance, an addition operation can be performed where the A operand is added to a B operand that is set to 0 or visa versa. Alternatively, the A and B operands can be coupled directly to the multiplexer The MIN and MAX operations are implemented by performing a conditional SUB and using the higher order bit of the sumout to select either A or B depending on whether a MAX or MIN operation is being performed. FIG. 3D shows one embodiment of a PU circuit implementation utilized to perform the MIN and MAX operations and depending on which operation is performed (MAX or MIN) the most positive or negative operand is chosen by S[ Hence, in accordance with the embodiments shown in FIGS. 2A, FIG. 4 shows an embodiment of a DPU which can perform all of the functions as described above and which is also adapted to perform a multiplication operation thereby providing an even more functionally powerful datapath unit. The datapath unit (DPU) shown in FIG. 4 has a configuration of logical modified adders including a top row of four 1-bit modified adders, PU( The DPU includes input data ports A( The PUs are arranged so as to form four stacks of PU pairs, including stacks PU( The DPU also includes an input port AP(I) for receiving a single A operand bit from a previous DPU in order to implement a single-bit shift operation. The AP(I) port provides a means of multiplying the A operand by 2 by shifting it to the left by one bit location. This operation (i.e., multiply by 2) is useful when using the DPU to perform a Booth's Algorithm multiplication as will be described herein. The DPU also includes a plurality of multiplexers that direct data into, through, and out of the configuration of modified adders dependent on select control signals (not shown) coupled to the plurality of multiplexers. In particular, when the DPU is used to form a multiplication unit, the multiplexers are set into a particular setting to direct data within the DPU in a manner as required to perform the multiplication operation. Alternatively, when the DPU is controlled to perform other operations such as operations A first set of eight multiplexers The DPU further includes a second set of four multiplexers The DPU also includes a third set of four multiplexers The DPU also includes a 2-to-1 multiplexer The DPU further includes multiplexer In one embodiment, the PUs in the DPU shown in FIG. 4 are implemented as shown in FIGS. 2B, To perform a bitwise logic operation, such as an A bitwise AND B operation, the DPU shown in FIG. 4 is set in the following manner: 1) multiplexers 2) multiplexers 3) the DPU ctrl signal is set to control each PU(n) to perform a single bit AND operation on each pair of single bits A(n) and B(n) coupled to each PU(n); 4) multiplexers 5) the remainder of the inputs, PUs, and multiplexers are in a don't care condition. In the case in which each PU is implemented as shown in the embodiment of FIG. 2G, the AND operation is performed by the DPU ctrl signal controlling multiplexer To perform an operation involving addition, subtraction, incrementing, and decrementing which utilizes carry values, the DPU is set in the following manner: 1) multiplexers 2) multiplexers 3) multiplexers a) PU(n) receives its carryin value from the previous PU(n−1) for PU( b) PU( c) PU( 4) the DPU ctrl signal is set to control each PU(n) to perform a single bit addition operation on each pair of single bits A(n) and B(n) coupled to each PU(n) such that each of the top and bottom rows of PUs generate a 4-bit sumout value and a single bit carryout value from PU( 5) multiplexers a) if the carryin signal is to be 0 (i.e., Cin=0, FIG. 4) then the NextC( b) if the carryin signal is to be 1 (i.e., Cin=1, FIG. 4) then the NextC( 6) multiplexer Hence, for operations involving addition, subtraction, incrementation, or decrementation, a 4-bit addition is performed on the A and B operands by each of the top and bottom rows of PUs to generate a 4-bit top sumout value and a 4-bit bottom sumout value as well as a single bit top carry out value from PU( It should also be noted that in the case in which the DPU is the first in a row of DPUs (e.g., DPU( In accordance with the embodiment of the DPU shown in FIG. 4, a group of DPUs can be interconnected into stacked rows of DPUs to form a first portion of a multiplier. The second portion of the multiplier is formed by first and second adder stages to generate the final multiplication product. FIG. 5A shows an embodiment of a 16Χ16 bit multiplier having a first portion implemented with an array of 16 DPUs (DPU( The multiplication operation performed by the multiplier shown in FIG. 5A is based on the Booth's algorithm multiplication technique and consequently in accordance with this technique, certain input operands and carry bits are shifted before being coupled to the DPU input ports and to individual PUs within each DPU. Alternatively, some operands are set to 0 or 1 values. Since each DPU includes two rows of four single bit PUs as shown in FIG. 4, each row of four DPUs includes a top and bottom row of 16 PUs. For instance, row FIG. 5B shows a detailed block diagram of DPU row Each row of 16 PUs performs a 16 bit addition operation and generates a 16-bit sumout value and a 16-bit carryout value which is coupled to the next row of PUs. For instance, referring to FIG. 5B, the top row of 16 PUs in row Sumout and carryout values from each PU are coupled to the next row of PUs to facilitate the Booth's algorithm multiplication technique wherein sum and carry values are shifted from one row of PUs to the next. The shifting of values is achieved using multiplexers FIG. 5C shows the shifted interconnections of the sumout values and carryout values generated by a row of PUs As can be seen in FIG. 5C, the single bit A(n) input operand is coupled to the A input port of the column of PU(n). For instance A( The carryin input port (C It should be noted that the A operand can be set to A(n) by setting multiplexers Summarizing the above description, when performing a multiplication operation using the 4Χ4 array of DPUs shown in FIG. 5A, each DPU is set in the following manner: 1) all of the A input ports of each DPU are coupled in the same manner to one of the following: a) A(n)=A(n) by setting multiplexers b) A(n)=A(n−1) by setting multiplexers c) A(n)=0 or 1 using circuitry shown in FIG. 3A; 2) multiplexers 3) multiplexers 4) multiplexers 5) multiplexer In operation, the A operand, B operand, and multiplexer controls are coupled to the 4Χ4 array of DPUs. Each row of PUs (two per DPU row) performs a 16-bit addition operation and generates partial product values (P( In the preceding description, numerous specific details are set forth, such as specific bus widths in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known logic structures and components have not been described in order to avoid unnecessarily obscuring the present invention. Moreover, although the components of the present invention have been described in conjunction with certain embodiments, it is appreciated that the invention can be implemented in a variety of other ways. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration is in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention. Patent Citations
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