US 6735609 B2 Abstract An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers
23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27. The buffers 29 store the values output from the adders 28. Claims(4) 1. An inverse discrete-cosine transform apparatus for performing inverse discrete-cosine transform on a discrete-cosine block that is a matrix composed of at most 8×8 discrete-cosine coefficients, said apparatus comprising:
eight discrete-cosine transform multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients;
ten field, compression discrete-cosine transform multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients;
eight selecting means for receiving the discrete-cosine coefficients multiplied by the coefficients in the eight discrete-cosine transform multipliers and the discrete-cosine coefficients multiplied by the coefficients in the ten field, compression discrete-cosine transform multipliers;
control means for controlling the eight selecting means so that, when the discrete-cosine block is not subjected to field division, one of the values input from the eight discrete-cosine transform multipliers to the eight selecting means may be selected in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected, and when the discrete-cosine block is subjected to field division and the discrete-cosine coefficients are input in the from of a vertical bit stream, one of the values input from the ten field, compression discrete-cosine transform multipliers to the eight discrete-cosine transform multipliers may be in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected; and
eight adding means associated with the eight selecting means, respectively, each for adding the values output from the associated selecting means,
wherein each of the eight discrete-cosine transform multipliers has, as coefficient, any one of eight inverse discrete-cosine coefficients which are some of the elements of a first matrix applied to perform inverse discrete-cosine transform on the discrete-cosine block and which have absolute values not identical to those of any other elements of the first matrix, and each of the ten field, compression discrete-cosine transform multipliers has, as coefficient, any one of the ten inverse discrete-cosine coefficients which are some of the elements of a second matrix applied to perform field, compression discrete-cosine transform and which have absolute values not identical to those of any other elements of the second matrix.
2. The apparatus according to
3. An inverse discrete-cosine transform apparatus for performing inverse discrete-cosine transform on a discrete-cosine block that is a matrix composed of at most 8×8 discrete-cosine coefficients, said apparatus comprising:
eight multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients;
eight selecting means for receiving the discrete-cosine coefficients multiplied by the coefficients in the eight discrete-cosine transform multipliers;
control means for controlling the eight selecting means so that one of the values input from the eight discrete-cosine transform multipliers to the eight selecting means may be selected in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected,
wherein said control means causes the eight selecting means to output values in accordance with a Table which shows a relation between the values output from the eight selecting means and the positions the discrete-cosine coefficients take in the discrete-cosine block, in which said Table is as follows:
eight adding means associated with the eight selecting means, respectively, each for adding the values output from the associated selecting means,
wherein each of the eight multipliers has, as coefficient, any one of eight inverse discrete-cosine coefficients which are some of the elements of a matrix applied to perform inverse discrete-cosine transform on the discrete-cosine block and which have absolute values not identical to those of any other elements of the first matrix.
4. The apparatus according to
Description The present invention relates to an inverse discrete-cosine transform apparatus for transforming input discrete cosine coefficients to inverse discrete-cosine coefficients. An inverse discrete-cosine transform apparatus is incorporated into an image-decoding apparatus that is designed to decode compressed image data. In the image-decoding apparatus, the inverse discrete-cosine transform apparatus transforms image data provided in the form of discrete-cosine coefficients, into inverse discrete-cosine coefficients. More precisely, the inverse discrete-cosine transform apparatus transforms input coefficients, in units of discrete-cosine blocks, thereby to generate image data. Each discrete-cosine block is, for example, an 8×8 matrix that is composed of discrete-cosine coefficients arranged in rows and columns. Discrete-cosine coefficients can be transformed to inverse discrete-cosine coefficients by applying the following equation (1) of inverse transform: where D As seen from the equation (1), the inverse discrete-cosine transform can be accomplished by performing matrix calculus on discrete-cosine coefficients and inverse discrete-cosine coefficients. Hence, the inverse discrete-cosine transform apparatus may have a matrix algebraic circuit that comprises multipliers and adders. In this case, the apparatus can effect inverse discrete-cosine transform on an input image of standard resolution or high resolution, which has been subjected to discrete-cosine transform, thereby to generate image data that has the same resolution as the input image. To provide such a matrix algebraic circuit, various methods have been devised. Each method is designed to reduce the number of operations that the matrix algebraic circuit needs to perform. In November 1984 Mr. Beyong Gi Lee published a fast cosine transform (FCT) algorithm in IEEE Transaction on Acoustics, Speech and Signal Processing, Vol. 32, No. 6, pp. 1243. This algorithm describes a method of reducing the number of necessary operations. A circuit, designed totally on the basis of the algorithm, has been developed. Thus, a fast algorithm optimal for an inverse discrete-cosine transform of discrete-cosine blocks of a specific size, for example 8×8 inverse discrete-cosine blocks, may be formulated and applied. Then, it is possible to provide a small, high-speed matrix algebraic circuit. An inverse discrete-cosine transform apparatus is known which converts a high-resolution image subjected to discrete-cosine transform, to an image having standard resolution. That is, the apparatus accomplishes compression inverse discrete-cosine transform. Japanese Patent Application Publication No. 2000-041261 discloses an inverse discrete-cosine transform apparatus of this type. Compression inverse discrete-cosine transform may be performed on a discrete-cosine block subjected to discrete-cosine transform in field discrete-cosine mode, thereby providing first pixel data. Further, compression inverse discrete-cosine transform may be carried out on a discrete-cosine block subjected to discrete-cosine transform in frame discrete-cosine mode, thereby providing second pixel data. The first pixel data and the second pixel data, thus provided, inevitably have a phase difference in the vertical direction. If an image-decoding apparatus incorporates an inverse discrete-cosine transform apparatus that effects the same compression inverse discrete-cosine transform on these two discrete-cosine blocks of different types, the quality of the image the apparatus outputs will deteriorated. In order to eliminate the phase difference in the vertical direction, two types of compression inverse discrete-cosine transform apparatuses have been invented. The first type is a field-mode, compression, inverse discrete-cosine transform apparatus that performs compression inverse discrete-cosine transform on a discrete-cosine block subjected to discrete-cosine transform in field discrete-cosine mode. The second type is a frame-mode, compression, inverse discrete-cosine transform apparatus that divides a discrete-cosine block subjected to discrete-cosine transform in frame discrete-cosine mode, into fields, thereby to accomplish the compression inverse discrete-cosine transform on the discrete-cosine block. The field-mode, compression, inverse discrete-cosine transform apparatus will be described first, which performs compression inverse discrete-cosine transform on a discrete-cosine block subjected to discrete-cosine transform in field discrete-cosine mode. The field-mode, compression, inverse discrete-cosine transform apparatus receives an 8×8 discrete-cosine block input in the form of a bit stream. The apparatus then performs inverse discrete-cosine transform on only the lower 4×4 coefficients of the 8×8 discrete-cosine block. In other words, the apparatus performs compression inverse discrete-cosine transform on the basis of four lower points existing in a lower region with respect to both the horizontal and the vertical direction. The field-mode, compression, inverse discrete-cosine transform apparatus can convert one discrete-cosine block to 4×4 pixel data as it carries out the compression inverse discrete-cosine transform. It will be described how the frame-mode, compression, inverse discrete-cosine transform apparatus divides a discrete-cosine block subjected to discrete-cosine transform in frame discrete-cosine mode, into fields, thereby to accomplish compression inverse discrete-cosine transform on the discrete-cosine block. As shown in FIG. 1, the frame-mode, compression, inverse discrete-cosine transform apparatus receives a bit stream that has been generated by compressing and encoding a high-resolution image. The bit stream is input to the apparatus, in the form of a discrete-cosine block. First, in Step S In Step S In Step S In Step S In Step S In Step S Performing Steps S The frame-mode, compression, inverse discrete-cosine transform apparatus effects Steps S A to J in the equation (2) are as follows: Fast algorithm may be used to effectuate the 4×4 compression inverse discrete-cosine transform in the field-mode, compression, inverse discrete-cosine transform apparatus and to perform Steps S In both apparatuses, applying a fast algorithm can carry out the compression inverse discrete-cosine transform. An example of a fast algorithm is the Wang algorithm (see Zhong DE Wang., “Fast Algorithms for the Discrete W Transform and for the Discrete Fourier Transform”, IEEE Tr. ASSP-32, No. 4, pp. 803-816, Aug. 1984). The matrix representing the compression discrete-cosine transform that the field-mode, compression, inverse discrete-cosine transform apparatus executes can be decomposed as shown in the following equation (3), by applying the Wang algorithm: FIG. 2 is a flowchart explaining how the Wang algorithm is applied in the field-mode, compression, inverse discrete-cosine transform apparatus. As can be understood from the flowchart, five multipliers The Wang algorithm is applied, decomposing the matrix [FS] into one expressed by the following equation (4). Note that the matrix [FS] is processed by the frame-mode, compression, inverse discrete-cosine transform apparatus. A to J in the equation (4) are as follows: FIG. 3 is a flowchart explaining how the Wang algorithm is applied in the frame-mode, compression, inverse discrete-cosine transform apparatus. As seen from this flowchart, ten multipliers Hitherto, the inverse discrete-cosine transform has been effected by three different methods. The first method performs inverse discrete-cosine transform on a high-resolution image or a standard-resolution image, either subjected to discrete-cosine transform, while maintaining the resolution of the image. (Hereinafter, the first method will be referred to as “standard inverse discrete-cosine transform.”) The second method carries out inverse discrete-cosine transform on a high-resolution image subjected, converting the image to one having a reduced resolution. (Hereinafter, the second method will be called “compression, inverse discrete-cosine transform.”) The third method effects field discrete-cosine transform on a discrete-cosine block subjected, thus dividing the block into fields. (Hereinafter, the third method will be referred to as “field-division, inverse discrete-cosine transform.”) The inverse discrete-cosine transform apparatuses that perform these three methods, respectively, are dedicated hardware units. Recently, image data is digitized. More and more apparatuses complying with the MPEG (Moving Picture Experts Group) system are used in broadcast stations and data-receiving sites such as households, for two reasons. First, the apparatuses perform orthogonal transformation and motion compensation on digital image data that has redundancy, thereby compressing the image data. Second, the image data can be transmitted and stored with higher efficiency than in the case it is not so compressed at all. The image data that will be transmitted in digital broadcasting in increasing amounts contains both standard-resolution data and high-resolution data. The data-receiving apparatus that receives the image data needs to have an inverse discrete-cosine transform apparatus that can decode both the standard-resolution data and the high-resolution data. To perform the above-mentioned different methods, however, a inverse discrete-cosine transform apparatus needs to have many multipliers and adders and will become complex, large and expensive. This is inevitably because the discrete-cosine blocks processed in the methods differ in size. The present invention has been made in consideration of the foregoing. An object of the invention is to provide an inverse discrete-cosine transform apparatus that has a simple structure and can, nonetheless, perform both standard inverse discrete-cosine transform and compression, inverse discrete-cosine transform and field-division, and/or inverse discrete-cosine transform. To achieve the object, an inverse discrete-cosine transform apparatus according to the invention is designed to perform inverse discrete-cosine transform on a discrete-cosine block that is a matrix composed of at most 8×8 discrete-cosine coefficients. The apparatus comprises: eight discrete-cosine transform multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients; ten field, compression discrete-cosine transform multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients; eight selecting means for receiving the discrete-cosine coefficients multiplied by the coefficients in the eight discrete-cosine transform multipliers and the discrete-cosine coefficients multiplied by the coefficients in the ten field, compression discrete-cosine transform multipliers; control means for controlling the eight selecting means so that, when the discrete-cosine block is not subjected to field division, one of the values input from the eight discrete-cosine transform multipliers to the eight selecting means may be selected in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected, and when the discrete-cosine block is subjected to field division and the discrete-cosine coefficients are input in the from of a vertical bit stream, one of the values input from the ten field, compression discrete-cosine transform multipliers to the eight discrete-cosine transform multipliers may be in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected; and eight adding means associated with the eight selecting means, respectively, each for adding the values output from the associated selecting means. Each of the eight discrete-cosine transform multipliers has, as coefficient, any one of eight inverse discrete-cosine coefficients which are some of the elements of a first matrix applied to perform inverse discrete-cosine transform on the discrete-cosine block and which have absolute values not identical to those of any other elements of the first matrix. Each of the ten field, compression discrete-cosine transform multipliers has, as coefficient, any one of the ten inverse discrete-cosine coefficients which are some of the elements of a second matrix applied to perform field, compression discrete-cosine transform and which have absolute values not identical to those of any other elements of the second matrix. The inverse discrete-cosine transform apparatus outputs discrete-cosine coefficients multiplied by inverse transform coefficients in the field-mode multiplier, when the input discrete-cosine block is not subjected to field division. The apparatus outputs discrete-cosine coefficients multiplied by inverse transform coefficients in the frame-mode multiplier, when a discrete-cosine block is input in the from of a vertical bit stream and then subjected to field division. According to the invention, there is provided an inverse discrete-cosine transform apparatus that is designed to perform inverse discrete-cosine transform on a discrete-cosine block that is a matrix composed of at most 8×8 discrete-cosine coefficients. This apparatus comprises: eight multipliers for multiplying the discrete-cosine coefficients input in the form of a bit stream, by coefficients; eight selecting means for receiving the discrete-cosine coefficients multiplied by the coefficients in the eight discrete-cosine transform multipliers; control means for controlling the eight selecting means so that one of the values input from the eight discrete-cosine transform multipliers to the eight selecting means may be selected in accordance with the positions the discrete-cosine coefficients take in the discrete-cosine block and may then be output after a plus sign or a minus signal is added to the value selected; and eight adding means associated with the eight selecting means, respectively, each for adding the values output from the associated selecting means, In the apparatus, each of the eight multipliers has, as coefficient, any one of eight inverse discrete-cosine coefficients which are some of the elements of a matrix applied to perform inverse discrete-cosine transform on the discrete-cosine block and which have absolute values not identical to those of any other elements of the first matrix. This inverse discrete-cosine transform apparatus effects inverse discrete-cosine transform on a discrete-cosine block that is a matrix composed of at most 8×8 elements. As can be understood from the foregoing, an inverse discrete-cosine transform apparatus according to the invention has a simple structure. It needs only eight inverse discrete-cosine transform multipliers and only ten field, compression discrete-cosine transform multipliers. This is because standard inverse discrete-cosine transform, compression, inverse discrete-cosine transform, and field, compression, inverse discrete-cosine transform are effected on the inverse transform coefficients of a matrix, thereby extracting the inverse transform coefficients that overlap the others of the matrix in terms of absolute value. The apparatus further comprises eight selecting means, control means and eight adding means. Therefore, it can perform standard inverse discrete-cosine transform, maintaining the resolution of a high- or standard-resolution image subjected to discrete-cosine transform. The apparatus can also effect compression, inverse discrete-cosine transform, converting a high-resolution image subjected to discrete-cosine transform, to a standard-resolution image. Further, the apparatus can execute field, compression, inverse discrete-cosine transform, dividing a discrete-cosine block subjected to field, discrete-cosine transform, into fields, thereby achieving compressed, discrete-cosine transform. As seen from the foregoing, another inverse discrete-cosine transform apparatus according to the invention has a simple structure. It needs only eight multipliers. This is because standard inverse discrete-cosine transform and compression, inverse discrete-cosine transform are effected on the inverse transform coefficients of a matrix, thereby extracting the inverse transform coefficients that overlap the others of the matrix in terms of absolute value. The apparatus further comprises eight selecting means, control means and eight adding means. Therefore, it can perform standard inverse discrete-cosine transform, maintaining the resolution of a high- or standard-resolution image subjected to discrete-cosine transform. The apparatus can also effect compression, inverse discrete-cosine transform, converting a high-resolution image subjected to discrete-cosine transform, to a standard-resolution image. FIG. 1 is a diagram explaining how a frame-mode, compression, inverse discrete-cosine transform apparatus performs its function; FIG. 2 is a flowchart illustrating how the transform apparatus of FIG. 1 operates when the Wang algorithm is applied to the apparatus; FIG. 3 is a flowchart explaining how a field-mode, compression, inverse discrete-cosine transform apparatus operates when the Wang algorithm is applied to it; FIG. 4 is a block diagram showing an image decoding apparatus incorporating an inverse discrete-cosine transform apparatus that is the first embodiment of this invention; FIG. 5A is a diagram explaining how the inverse discrete-cosine transform apparatus shown in FIG. 4 processes data in the first mode; FIG. 5B is a diagram illustrating how the inverse discrete-cosine transform apparatus depicted in FIG. 4 processes data in the second mode; FIG. 5C is a diagram explaining how the inverse discrete-cosine transform apparatus illustrated in FIG. 4 processes data in the third mode; FIG. 6 is a circuit diagram of the inverse discrete-cosine transform apparatus shown in FIG. 4; FIG. 7 is a circuit diagram of an inverse discrete-cosine transform apparatus that is the second embodiment of the present invention; FIG. 8A is a diagram explaining how the inverse discrete-cosine transform apparatus of FIG. 6 processes data in the fourth mode; and FIG. 8B is a diagram explaining how the inverse discrete-cosine transform apparatus illustrated in FIG. 4 processes data in the fifth mode. Inverse discrete-cosine transform apparatuses, which are embodiments of this invention, will be described with reference to the accompanying drawings. FIG. 4 illustrates an image decoding system The image decoding As shown in FIG. 4, the image decoding system The bit stream analyzing apparatus The inverse discrete-cosine transform apparatus The adder apparatus The frame memory The motion compensating apparatus The inverse discrete-cosine transform apparatus In the first mode, the inverse discrete-cosine transform apparatus In the second mode, the inverse discrete-cosine transform apparatus In the third mode, the inverse discrete-cosine transform apparatus More specifically, in the first mode, the inverse discrete-cosine transform apparatus In the second mode, the inverse discrete-cosine transform apparatus In the third mode, the inverse discrete-cosine transform apparatus In the field discrete-cosine transform mode, the apparatus In the frame discrete-cosine transform mode, the apparatus FIG. 6 shows the circuit configuration of the inverse discrete-cosine transform apparatus As FIG. 6 shows, the apparatus The buffer section The FK multiplying section Table 1 presented below shows the values of the inverse transform coefficients FK0 to FK9. The coefficient FK0 to FK9 will be described.
The matrix [FS] expressed by the equation (2), described in conjunction with the conventional, inverse discrete-cosine transform apparatus, has 8×4 elements. Of these elements, only ten elements A to J can be extracted in terms of their absolute values. If elements A to J are multiplied first by 1/{square root over (2)} and then by 8192, inverse transform coefficients FK0 to FK9 will be obtained. Each of the coefficients FK0 to FK9 consists of 14 bits (−8192 to 8192), as is shown in Table 1. Hence, the number of multipliers, which the FK multiplying section As shown in FIG. 6, the K multiplying section Table 2 presented below shows the values of the inverse transform coefficients K0 to K7. The coefficient K0 to K7 will be described.
The step of effecting inverse discrete-cosine transform on discrete-cosine coefficients, without carrying out field division, can be replaced by the matrix calculus performed on matrix [NFS] that is obtained from the equation (1) and represented by the following equation (5). The elements K to R in the equation (5) have the values specified below: The matrix [NFS] shown in the equation (5) has 8×8 elements. Of these elements, only eight elements K to R can be extracted in terms of their absolute values. If elements K to R are multiplied first by 1/{square root over (2)} and then 8192, inverse transfer coefficients K0 to K7 will be obtained. Each of the coefficients K0 to K7 consists of 14 bits (−8192 to 8192), as is shown in Table 2. Thus, the number of multipliers, which the multiplying section The matrix [NFS] is utilized to effectuate HIDCT 8×8 and VIDCT 8×8, which are shown in FIGS. 5A and 5B. In the inverse discrete-cosine transform apparatus The step of achieving HIDCT 4×4 shown in FIG. Therefore, it suffices for the apparatus
The selector section More specifically, the bit stream analyzing apparatus The bit stream analyzing apparatus The selector section
The selector section As indicated above, the selector section The values the elements of the matrix [NFS′] have are those selected from Table 5, as is shaded in the following Table 6.
Thus, what should be stored in the memory section (not shown) are Tables 4 and 5. The method in which the selector section The buffer section The values may be input from the selectors The sign multiplying section
The following table 9 corresponds to the matrix [NFS′]. The elements of the matrix [NFS′], which are shaded in Table 9, have been extracted from Table 8.
Hence, what are stored in the memory section (not shown) are Table 7 and Table 8. Each value output from the buffer section The adding section The buffer section How the inverse discrete-cosine transform apparatus First, the apparatus The two-figure suffix to each discrete-cosine coefficient indicates the ordinal numbers of the row and column in which the coefficient exists. It should be noted that the suffix “0” designates the first row and the first column. Thus, coefficient D The discrete-cosine coefficient D Consider the selector In Table 5, indices V0 to V7 are arranged in the vertical direction, and indices U0 to U7 are arranged in the horizontal direction. The indices V0 to V7 correspond to the selectors As for the selectors The value K0·D The control section causes the sign multiplying section How the sign multiplier Similarly, the values output from the selectors Assume that the value D The control section causes the selectors The sign multipliers The adding section When values D Thus, the inverse discrete-cosine transform apparatus Thus, the apparatus In this case, the matrix (8) may be input to the inverse discrete-cosine transform apparatus The elements P The functional sections of the inverse discrete-cosine transform apparatus Assume that the following pixel data S, or the following matrix (9), which is composed of pixel data items S The matrix calculus performed on the matrix [NFS] and the matrix obtained by transposing the matrix (8) results in a matrix that the matrix (9) transposed. Therefore, the matrix resulting from this matrix calculus is identical to the results provided by the inverse discrete-cosine transform apparatus It will be now described how the inverse discrete-cosine transform apparatus Next, inverse discrete-cosine transform is executed in the vertical direction. As indicated above, the 4×8 horizontal pixel block is input to the inverse discrete-cosine transform apparatus How the inverse discrete-cosine transform apparatus In the third mode, the apparatus Assume that the inverse discrete-cosine transform apparatus In this case, the inverse discrete-cosine transform is first executed in the horizontal direction. In the third mode, the apparatus Next, the apparatus It will be described how the inverse discrete-cosine transform apparatus First, the apparatus Next, the apparatus Thus, in the inverse discrete-cosine transform apparatus FIG. 7 illustrates the circuit configuration of an inverse discrete-cosine transform apparatus The inverse discrete-cosine transform apparatus Like the inverse discrete-cosine transform apparatus As mentioned above, the inverse discrete-cosine transform apparatus In the fourth mode, the inverse discrete-cosine transform apparatus More specifically, in the fourth mode, the inverse discrete-cosine transform apparatus In the fifth mode, the inverse discrete-cosine transform apparatus More precisely, in the fifth mode, the apparatus The circuit configuration of the inverse discrete-cosine transform apparatus As shown in FIG. 7, the apparatus The buffer section The multiplying section The step of effecting inverse discrete-cosine transform on discrete-cosine coefficients can be replaced by the matrix calculus performed on matrix [NFS] that is obtained from the equation (1) and represented by the following equation (5). As indicated above, the matrix [NFS] has 8×8 elements. Of these elements, only eight elements K to R can be extracted in terms of their absolute values. The number of multipliers required in the multiplying section 103 can, therefore, be reduced from 8×8 (the number of elements the matrix [NFS] has) to eight. If the elements K to R are multiplied first by 1/{square root over (2)} and then by 8192, inverse transform coefficients K0 to K7 will be obtained. Each of the coefficients K0 to K7 consists of 14 bits (−8192 to 8192). These coefficients K0 to K7 may be allocated to the multipliers of the multiplying section
The matrix [NFS] is utilized to effectuate HIDCT 8×8 and VIDCT 8×8, which are shown in FIG. The step of achieving HIDCT 4×4 and VIDCT 4×4, shown in FIG. 8B, can be replaced by the matrix calculus effected on the matrix [NFS′] (equation (6)) derived from the equation (5) and on the discrete-cosine coefficients. Therefore, it suffices for the apparatus
The selector section
The selector section The values the elements of the matrix [NFS′] have are those selected from Table 12, as is shaded in the following Table 13.
The sign multiplying section
The following Table 15 corresponds to the matrix [NFS′]. The elements of the matrix [NFS′], which are shaded in Table 14, have been extracted from Table 14.
The adding section The buffer section How the inverse discrete-cosine transform apparatus The fourth mode is identical to the first mode in which the inverse discrete-cosine transform apparatus First, the apparatus The discrete-cosine coefficient D Consider the selector In Table 12, indices V0 to V7 are arranged in the vertical direction, and indices U0 to U7 are arranged in the horizontal direction. The indices V0 to V7 correspond to the selectors As for the other selectors The value K0·D The control section causes the sign multiplying section How the sign multiplier Similarly, the values output from the selectors Assume that the value D The control section causes the selectors The sign multipliers The adding section When values D Thus, the inverse discrete-cosine transform apparatus The apparatus How the inverse discrete-cosine transform apparatus In the fifth mode, the apparatus The discrete-cosine block (10) is a 4×4 block that has been generated by extracting high-frequency vertical components and some horizontal components from the discrete-cosine block (7). First, the apparatus The discrete-cosine coefficient D Consider the selector In Table 13, indices V0 to V3 are arranged in the vertical direction, and indices U0, U2, U4 and U6 are arranged in the horizontal direction. The indices V0 to V7 correspond to the selectors As for the other selectors The value K0·D The control section causes the sign multiplying section How the sign multiplier Similarly, the values output from the selectors Assume that the value D The control section causes the selectors The sign multipliers The adding section When values D Thus, the inverse discrete-cosine transform apparatus The apparatus As described above, in the inverse discrete-cosine transform apparatus Patent Citations
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