|Publication number||US6747855 B2|
|Application number||US 10/053,685|
|Publication date||Jun 8, 2004|
|Filing date||Jan 24, 2002|
|Priority date||Jan 24, 2002|
|Also published as||US7132764, US20030137787, US20040165328, WO2003063326A2, WO2003063326A3|
|Publication number||053685, 10053685, US 6747855 B2, US 6747855B2, US-B2-6747855, US6747855 B2, US6747855B2|
|Inventors||Pavan M Kumar, Lilly Huang|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (18), Classifications (12), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to the field of power supply regulators, and, more specifically, to power supply regulators for microelectronic equipment.
2. General Background and Related Art
As the speed and performance of microelectronics devices have continued to increase, so too have the input power requirements for these microelectronics devices continued to increase. Such microelectronics devices include, for example, a microprocessor device utilizing a processor die embodied in an integrated circuit. However, it is desirable to reduce input power requirements from an engineering perspective in order to limit power consumption and to permit relatively smaller form factors still capable of providing the required heat dissipation. Therefore, techniques have been developed for reducing input power requirements while maintaining and increasing processing performance and speed.
For microprocessor devices, for example, reduction in the Central Processing Unit (CPU) supply voltage has been a widely employed technique used to achieve a reduction in power consumption. Another technique includes providing microelectronics devices designed to operate using multiple supply voltages in order to reduce the overall total power consumption of the device. One such technique in particular involves providing a microelectronics device (for example, a single processor die) designed for operation with either of two different input voltage ranges.
The amount of permissible deviation in the input supply voltage is a critical parameter in the design of microelectronics devices. The choice of design techniques and circuit configurations to be used in realizing the design of the microelectronics device may be limited due to a particular input supply voltage tolerance specification. Furthermore, if the input power (voltage or current) is not maintained within its required tolerances (also known as “out of regulation”), the behavioral characteristics of the microelectronics device's circuitry may be adversely affected to cause a variety of unwanted behaviors, including device latchup or transitions into indeterminate states. For at least these reasons, it is desirable to maintain input power voltage and current within specified tolerances. Toward this end, power supply regulators are used to maintain input power received from a power source such as, for example, a battery or a loosely regulated source, within the required design tolerances.
The amount of permissible deviation in input voltage in particular may be expressed as a percentage tolerance centered at a particular voltage level. For example, an input voltage specification may require an input voltage VCC to be +2 VDC±10%. In other words, the input voltage must be maintained by a regulator to within 10% of +2 VDC in order to be considered within regulation.
Microelectronics devices designed to utilize two or more input voltage specifications may present particularly challenging design issues. One such challenge is that the actual amount of permissible deviation in the input voltage may become smaller, or tighter, as the required input voltage level is reduced. Thus for the lower of the two (or more) input voltage levels, the permissible deviation of the input voltage can be significantly tighter than for the larger input voltage level(s), even as microcircuit devices demand increasing amounts of input current, ICC, at the lower VCC.
FIG. 1 is an exemplary illustration of the relatively tighter tolerance required to be maintained “in regulation” for the lower of two input voltage requirements. Referring to FIG. 1, in order to provide regulated input power for a given microelectronics device at a nominal voltage of VCC, under any load conditions the input voltage is required to be within a tolerance of, for example, a 10% VCC window, or VCCmin≧90%*VCC. Such a scheme is typically employed to limit the excursion of the supply voltage to a small window. As for an upper limit, device reliability may be reduced if the supply voltage presented to the microelectronics device rises above VCCx, a reliability limit voltage level greater than VCC nominal. The 10% window required for voltage regulation places a heavy burden on the power supply and power delivery system to meet a tight dynamic impedance range (ZDYN
The exemplary voltage values depicted in FIG. 1 are shown in an example for a dual VCC system. As shown in FIG. 1, in the case of the higher supply voltage (VCC=2.0 VDC) the regulation window available, or range, is about 200 mV whereas the regulation window decreases to 140 mV at the lower input voltage level of 1.4 VDC. As the microelectronics device supply voltage drops to the sub ˜1 Volt range, the regulation window increasingly becomes a critical design issue. In particular, the stringent tolerance requirement on the lower input voltage may be the cause of design difficulties and significantly increased product cost due to design constraints for avoiding electrical phenomena such as droops using decoupling effects, and also due to the increased circuitry required to regulate the input voltage to within such fine tolerances. In the environment of multiple input voltage required values, this problem may be exacerbated by, for example, static and transient voltage “droop” characteristics occurring for the lower VCC input voltage required value when the microelectronics device demands relatively high supply current. Voltage droop describes a situation in which the input voltage provided by the regulator to the microelectronics device moves toward or is presented at a voltage level that is lower than the specified input voltage required value but is still within the specified tolerance level to maintain supply voltage in regulation.
Utility of the embodiments of the present invention will be readily appreciated and understood from consideration of the following detailed description of the embodiments:
FIG. 1 is an exemplary illustration of the relatively tighter voltage tolerance required to be maintained for the lower of two input voltage requirements according to prior regulators;
FIG. 2 is a schematic block diagram of an embodiment of an electronic system according to the present invention;
FIG. 3 illustrates a regulation scheme in accordance with an embodiment of the present invention;
FIG. 4 is graph showing a pair of linear voltage-current loadlines for two input voltages for a voltage regulation scheme;
FIG. 5 is a graph showing a set of voltage-current loadlines for multiple input voltages provided by an embodiment of a regulator in accordance with the present invention;
FIG. 6 is a schematic diagram of a power supply regulator for a prior regulation scheme;
FIG. 7 is a schematic diagram of an embodiment of a regulator for a power delivery scheme in accordance with the present invention; and
FIG. 8 is a flow chart illustrating a method for regulating device input power in accordance with an embodiment of the present invention.
In some embodiments the present invention may include a system and method for a power regulator that supplies regulated power to one or more microelectronics devices, such as a microprocessor, at lower cost in terms of power consumption without sacrificing performance, speed, or reliability in the microelectronics device. In particular, in at least one embodiment there is provided a system and method for a voltage regulation scheme addressing the static and transient droop characteristics on lower Vcc input voltages supplied under the environment of multiple device or CPU voltage levels.
FIG. 2 provides an overall block diagram description of an embodiment of the present invention. The term “an embodiment” as used herein is understood to mean “at least one embodiment.” Further, the term “may” as used herein is understood to mean “could, but not necessarily must.” Referring to FIG. 2, an electronic system 10 may include a power source 20, one or more microelectronics devices 30, and a power supply regulator 100. Power supply regulator 100 may be coupled to power source 20 via a power source interface 25 and to microelectronics device 30 via one or more input power interfaces 35. Regulator 100 may include a controller 120 configured to cause regulator 100 to produce regulated input voltages as described herein. In an embodiment, power source 20 may be a source of rectified direct current (DC) voltage such as, but not limited to, a battery or an output of an AC power transformer/adapter. Regulator 100 may receive source voltage from power source 20 via power source interface 25. Further, regulator 100 may provide regulated input voltages to one or more microelectronics devices 30 via input power interface 35.
Microelectronics device 30 may be any electronic device having an integrated circuit component. In an embodiment, microelectronics device 30 may consist of electronic circuitry in the form of a processor die embodied in an integrated circuit package. Microelectronics device 30 may be designed to require more than one input voltage for operation in accordance with multiple modes. For example, microelectronics device 30 may require a higher input voltage of, for example, VCC1=2.0 VDC, as a principal supply voltage for normal operation and may also require a lower input voltage of, for example, VCC2=1.4 VDC as a secondary supply voltage for normal operation or an idle mode or reduced functionality operating mode.
Electronic system 10 may be, for example, a desktop computer, a laptop computer, a notebook computer, a wireless telecommunications terminal, a personal communications services terminal, a card reader, a transmitter and/or receiver, or any other such electronic system. Power source 20, microelectronics device 30, and regulator 100 may be positioned interior to a housing of electronic system 10. Alternatively, power source 20 may be located exterior to the housing of electronic system 10. Power source interface 25 coupling power source 20 to regulator 100 may consist of two or more conductive elements such as metal filament wires. In an embodiment, regulator 100 and microelectronics device 30 may be mounted on a circuit card substrate 40 which may also be located interior to the housing of electronic system 10. In this embodiment, input power interface 35 may be provided in the form of one or more circuit traces of circuit card substrate 40 providing electrical connectivity between regulator 100 and microelectronics device 30.
FIG. 3 illustrates a regulation scheme in accordance with an embodiment of the present invention. Referring to FIG. 3, a principal supply voltage is still operated within a 10% tolerance window or level with an upper limit bounded by reliability voltage value Vccx, as was the case for FIG. 1. However, for the present embodiment the secondary supply voltage is operated within a range having an upper limit that is the same as for the principal supply voltage, i.e., Vccx. The principal supply voltage is operated within a range having a lower limit of the 0.90 multiplied by a first input voltage required value (Vcc1), i.e., 0.90×Vcc1 or one minus the tolerance level 10% multiplied by the first input voltage required value. The secondary supply voltage, Vcc2, is operated within a range having a lower limit of 0.90 multiplied by a second input voltage required value (Vcc2), i.e. 0.90×Vcc2, or one minus the tolerance level (10%) multiplied by the second input voltage required value. For example, if Vcc2 is 1.4 volts, the lower limit of the range that the secondary supply voltage Vcc2 is operated within would be 1.26, or (0.9×1.4).
The lower limit may also be determined based upon the change in dynamic impedance, ZDYN
A regulating scheme in accordance with an embodiment of the present invention is further described using an exemplary numerical example in reference to FIG. 3. Referring to FIG. 3, the second input voltage required value, Vcc2, where Vcc2<Vcc1, may be for example, 1.4 VDC, and the first input voltage required value, Vcc1, may be, for example, 2.0 VDC. As shown in FIG. 2, for each different input voltage required value, the regulator provided in accordance with an embodiment may maintain each of the distinct input voltages presented to microelectronics device 30 within the same upper limit, Vccx, which is the same upper limit for Vcc1. However, the regulator provided in accordance with the embodiment may maintain the lower limit for the second input voltage required value, Vcc2 (1.4 VDC, for example), equal to the lesser of the product of one minus the tolerance level (in this example 10%) multiplied by the first input voltage required value (2.0 VDC) and one minus the tolerance level multiplied by the second input voltage required value (1.4 VDC). In the exemplary regulating scheme of FIG. 3, this determination yields a lower limit of 1.26 VDC, thus giving the power supply in accordance with an embodiment a dynamic window from the second input voltage required value, of 740 mV instead of the relatively tight range of 140 mV.
A regulation scheme of an embodiment, as shown in FIG. 3, therefore may provide a looser (i.e., larger) regulation window or range required to be provided by the regulated power supply 100 without sacrificing the performance of the microelectronics device 30. Furthermore, the reliability of microelectronics device 30 (such as, for example, a processor) may not be compromised under the scheme according to an embodiment because the upper limit, Vccx, the reliability limit, is not breached. Vccx may represent a thermal design point (TDP) for microelectronics device 30, and as such may constitute a reliability limit to be maintained by regulator 100. In addition, the thermal design (TDP) advantage of utilizing multiple input voltage required values, or Vcc's, over a single input voltage required value as realized by microelectronics device 30 may still be maximized if the excursion of the lower Vcc supply is tightly controlled in response to changes in the microelectronics device 30 load current.
A regulating scheme in accordance with an embodiment may also be further described in terms of supply voltage loadlines illustrated in the voltage-current curves of FIGS. 4 and 5. FIG. 4 shows a regulating scheme in which the loadline for each input voltage required value has a continuous slope from the required value to within a lower limit based on a required tolerance level of, for example, 90% of their nominal values.
FIG. 5 shows a further set of loadlines that may be provided by a regulator 100 in accordance with an embodiment. Referring to FIG. 5, the loadlines for the secondary supply voltage may be continuous or discontinuous at a particular current value such as, for example, but not limited to, a value equal to the leakage current of the microelectronics device 30. The loadline may be discontinuous for any load current between zero and the maximum load current. When microelectronics device 30 operates in a lower demand state such as, for example, a standby state, the load current may equal the device leakage current (i.e., Icc=Icc−leakage). In this exemplary case, the voltage supplied by regulator 100 such as VCC2 may drop and move toward its lower limit, VCC2MIN, at device leakage current, ILK2, and may reach VCC2MIN at device maximum current, IMX2. As shown in FIG. 5, only as device current demand approaches ILK1 from ILK2 does VCC2=VCC1. Therefore, in this example as long as regulator 100 controls the excursion of voltage-current supplied to microelectronics device 30 according to any one of the V-I curves shown in FIG. 5 in a manner that maintains I=Pmax/V, where Pmax is a constant that may be, for example, determined by the microelectronics device 30 thermal design envelope, then the thermal design advantage derived from using multiple input voltages is achieved. The regulating scheme of an embodiment of the present invention thereby provides favorable power supply design characteristics as well as supporting improved thermal design characteristics associated with microelectronics device 30. Other regulation schemes are possible without departing from the spirit and scope of the present invention.
As described in further detail below, an exemplary embodiment of the present invention for regulation of multiple supply voltages for microelectronics devices may use the buck converter power supply regulation topology. In a microelectronics device 30 such as, for example, a microprocessor, the power delivery scheme can be represented as shown in FIG. 6. Referring to FIG. 6, a buck converter 200 (which may be a multiphase buck converter) may include a switch (S) 205, a diode (D) 210, an inductor (L) 215, and an output filter capacitor (C) 220. Buck converter 200 may further include a controller 230 having a comparator 240 and a threshold detector 250. In FIG. 6, the value ZT represents the total interconnect impedance between the output of the voltage regulator and the microelectronics device 30.
In the buck converter 200, the regulator output voltage VO may be adjusted by a controller 230 configured to vary the duty cycle of the switch 205. Controller 230 may also sense the output current, multiply the sensed current by a current feedback gain factor (G), and provide the current feedback value to controller 230. By varying the duty cycle of switch 205, controller 230 may cause the regulator output voltage VO to conform to a voltage-current loadline as shown in FIG. 4 or 5 restricting the excursion of the output voltage to be within a range based on a particular tolerance level. For example, for a 10% tolerance level, regulator output voltage VO value may be maintained at a level that is lower than the associated input voltage required value, or reference voltage VR. The tolerance level of 10% may be due to, among other things, an input voltage level for which microelectronics device performance reaches an unacceptably degraded level due to supply voltage falling more than 10% below the set value VR. In the buck converter 200, the value of the current feedback gain (G) may be computed based on the value of the load current ILD, the percentage droop value of VR (e.g., 10%), and the resistance value of the total interconnect impedance ZT.
FIG. 7 illustrates an embodiment of a regulator circuit 300 for a power delivery scheme in accordance with an embodiment. As shown in FIG. 7, the system of an embodiment for multiple supply voltage regulation may be implemented using the buck converter topology in accordance with similar principles as those described above with respect to FIG. 6. However, an embodiment may also be implemented in accordance with a variety of power supply regulator topologies such as, but not limited to, the boost and flyback arrangements. FIG. 7 illustrates a conceptual implementation of a variable droop regulation scheme in accordance with an embodiment for a microelectronics device (such as, but not limited to, a processor) requiring dual input supply voltages. However, other embodiments of the present invention are possible; for example, an embodiment may provide regulation for multiple input voltages in excess of the exemplary two input voltage embodiment described in detail herein.
Referring now to FIG. 7, microelectronics device 30 may be, for example, designed to operate using two input voltage required values, Vcc1 and Vcc2. In this case the regulator circuit 300 provided in accordance with an embodiment may include two conceptually distinct regulator circuits 310 and 315. As shown in FIG. 7, regulator circuit 310 may be used to provide power supply regulation for a principal supply voltage to track a first input voltage required value, Vcc1, while regulator circuit 315 may be used to provide power supply regulation for a secondary supply voltage to track a second input voltage required value, Vcc2, in accordance with an embodiment. In an embodiment, the first input voltage required value, Vcc1, may be a higher input voltage of, for example, 2.0 VDC, while the second input voltage required value, Vcc2, may be a lower input voltage of, for example, 1.4 VDC. In an exemplary embodiment of FIG. 7, regulator circuits 310 and 315 are each provided in accordance with buck technology. The corresponding exemplary buck regulator embodiment shown in FIG. 7 includes the appropriate suffixes (e.g., “1” and “2”) to designate a component regulating the principal supply voltage and the secondary supply voltage to track the first or second input voltage required values, respectively. While shown schematically as being logically separate, the components of regulator circuits 310 and 315 may be implemented using one or more of the same components, or different components, without departing from the scope of the present invention.
Referring now to FIG. 7, regulator circuits 310 and 315 may include a switch 320 (S1 and S2), a diode 325 (D1 and D2), an inductor 330 (L1 and L2), an output capacitor 335 (C1 and C2), a compensation network 345 (ZN1/ZF1 and ZN2/ZF2), and a controller 355. Controller 355 may include a comparator 360 and a threshold detector 365. Input voltage VIN from a power source may be connected to one side of switch 320. The other side of switch 320 may be connected to an inductor 330 and a diode 325 as shown in FIG. 7. The second terminal of diode 325 may be connected to ground. The second terminal of inductor 330 may be connected to one terminal of an output capacitor 335. The second terminal of capacitor 335 may be connected to ground.
Present at the second terminal of the inductor 330, after the connection to capacitor 335, may be the load current ILD. Load current ILD may be sensed to provide a current feedback signal that may be multiplied by a gain factor (G1 or G2) and then provided to threshold detector 365. Load current ILD may be coupled to one or more microelectronics devices 30 by interfaces 370 and 380. Interfaces 370 and 380 coupling the load current ILD to the microelectronics device 30 may be characterized by an interconnect impedance, ZT1 and ZT2 respectively. Regulator output voltage VO may be also tapped and coupled to compensation network 345. The output of ZN may be connected to one input terminal of threshold detector 365 and also to ZF to complete compensation network 345. A second input terminal of threshold detector 365 may be coupled to a reference voltage, VCC1 or VCC2. The output of compensation network 345 may be coupled to the output of threshold detector 365, which may be in turn connected to the input of comparator 360. In one embodiment, comparator 360 may include an internal reference. In another embodiment, comparator 360 may include an external reference. The output of comparator 360 may be coupled to switch 320. Switch 320 operates (i.e., switches between “on” and “off” states) in accordance with a signal provided by controller 355 via comparator 360.
The operation of regulator circuits 310 and 315 will now be described with respect to FIG. 7. In operation, supply voltage VIN is presented to switch 320, which may be in either an open or closed state as determined by controller 355. The duty cycle of switch 320 may be used to control or regulate the input voltage provided by the regulator circuits 310 and 315 to microelectronics device 30. In particular, threshold detector 365 may produce an error signal based upon the magnitude of the difference between a reference voltage, VCC1 or VCC2, and the sensed actual device input voltage present at the output of the regulator circuit 310 or 315 (e.g., VO). The magnitude of the error signal may be provided as a function of the sensed output voltage and the value of compensation network 345. Comparator 360 may control the duty cycle of switch 320 based upon the magnitude of the error signal generated by threshold detector 365. Generally, the device input voltage, VO, produced by regulator 300 increases as the duty cycle of switch 320 increases.
The lower value reached by regulator output voltage, VO, (which is also the device input voltage) may be controlled by selecting the gain factor, G, to achieve a desired VO within a particular lower limit of the permissible input voltage range for different values of the load current, ILD. The gain factor may be determined by the impedance values selected for ZT1 and ZT2, for example. In particular, regulator circuits 310 and 315 may produce VO in accordance with the following equation:
VO is the output voltage,
VCC is the source voltage,
G is the gain factor, and
ILD is the load current.
Therefore, the current sense gain, G1 or G2, may determine the percentage of input voltage “droop” experienced for a given load current ILD1 or ILD2, respectively. The values of G1 and G2 can be selected and computed for different embodiments as required. In particular, controller 355 may be configured to regulate supply voltage according to a variety of control criteria including, but not limited to, linear loadline, non-linear loadline, stepped, or constant power.
A method 400 regulating device input power in accordance with an embodiment of the present invention is shown in FIG. 8. Referring to FIG. 8, regulator 100 may receive one or more supply voltages from a power source 20 at 405. Regulator 100 may measure the regulator output voltage, VO, at 410 as well as the load current, ILD, at 415. Further, regulator 100 may determine a lower limit of a regulation range for device input voltage VO in accordance with a voltage-current loadline at 420. As described elsewhere herein, the loadline may specify a linear or non-linear relationship between voltage and current. In an embodiment, the loadline is represented by a series of discrete voltage-current values stored in memory accessible by controller 355 such as, but not limited to, persistent values stored in an erasable programmable read only memory (EPROM) device. Multiple sets of loadline values may be maintained by regulator 100 corresponding to a variety of loadlines such as, but not limited to, the linear and non-linear loadlines as described herein. Controller 355 may select a particular loadline in response to a variety of events such as, for example, changes in microelectronics device power demand or input power requirements. The series of values for a given loadline may form the desired voltage-current output produced by regulator 100 for power input to one or more microelectronics devices.
The measured values from 410 and 415 may next be compared, at 425, to the associated loadline values from 420. Based on the difference between the measured values and the associated reference loadline values, controller 355 may adjust a gain factor in order to cause input voltage VO to approach the associated loadline values, at 430. In one embodiment, controller 355 may statically adjust the gain factor in response to the occurrence of a particular event such as, but not limited to, load current reaching one or more predetermined values, or at discrete intervals of elapsed time, which may or may not be periodic. In another embodiment, controller 355 may dynamically adjust the gain factor by repeatedly computing the gain factor to cause input voltage VO to closely track the loadline. Further, controller 355 may transmit a signal to a switch (reference FIG. 7) to control the duty cycle of the switch, in an exemplary switching power supply embodiment, in order to maintain device input voltage VO in accordance with the loadline values, at 435. The thus regulated device input voltage VO may then be supplied to one or more microelectronics devices at 440.
In one embodiment, controller 355 may be configured to maintain device input voltage, VO, according to a linear loadline 160 as shown in FIG. 5. In this case, device input voltage may be required to be maintained above the lower limit of a percentage droop of less than 10%. By way of comparison, for regulators previous to an embodiment, the gain factor, G, could only be set such that the value of the product (G1*ILD1) is equal to (0.1*VCC1), and (G2*ILD2) to (0.1*VCC2), respectively, and as shown in FIG. 4.
For a regulator 100 according to an embodiment, however, a larger percentage voltage droop may be provided (e.g., >10% decrease in VCC1) for the lower limit of the supply voltages. In one embodiment, for input voltage required values less than the largest of the multiple input values, the gain factor (i.e., G2) may be computed and set such that the product (G2*ILD2) is equal to the product (x*VCC2) where 0.1≧x≧1 and may be based upon the design characteristics of a particular microelectronics device. This embodiment is shown as linear loadline 160 in FIG. 5.
In other embodiments of regulator 100 according to the present invention, controller 355 may be configured to maintain device input voltage, VO, according to a variable or non-linear loadline 150 or 170 as shown in FIG. 5. A non-linear loadline can be implemented for any one of the multiple input voltage required values, such as the exemplary two voltages VCC1 and VCC2, by computing the value of the gain factor G using a concept of constant power or a stepped type of load.
For example, for an embodiment of regulator 100 in which device input voltage, VO, is regulated according to a constant power loadline, the output voltage, VO, of the regulator can be computed based on the principle of constant power. In accordance with this embodiment, the total power output by regulator 100 is maintained as a constant according to a voltage-current curve such as the constant power loadline 150 shown in FIG. 5. In order to maintain regulator 100 output power constant, the output voltage, VO, may be repeatedly computed as VCC2=(P/ILD2) at any fixed value of ILD2. Based on the instantaneous value of ILD2, controller 355 may statically or dynamically change the output voltage VO based on the total power, P, rather than as a fixed percentage droop as in the linear loadline embodiment.
Furthermore, for an embodiment of regulator 100 in which device input voltage VO is regulated according to a discontinuous or stepped loadline, the output voltage VO of the regulator can be computed based on a particular instantaneous value of ILD2. In accordance with this embodiment, regulator 100 maintains output voltage VO according to a non-linear loadline 170 such as that shown in FIG. 5. In this embodiment, the value of G may also be computed in discrete steps for instantaneous values of load current ILD. Up to a certain intermediate value of ILD between zero and maximum ILD such as, for example, ILK2, controller 355 may require regulator 100 to follow a 10% droop specification as shown for loadline 170. For ILD greater than the value of ILK2, the droop could be more or less than 10% depending on the design tolerances of the microelectronics device. ILK2 may correspond to a leakage current value for a given microelectronics device.
In a further embodiment, regulator 100 may make a step change in the output voltage VO at any given point, or at various points for different values of ILD, along a particular loadline between the minimum and maximum values of the load current. Such regulation schemes may require more complex embodiments for computing the value of G. Therefore, controller 355 may be implemented using a Digital Signal Processor (DSP) to provide rapid calculation of the gain factor, in order to provide dynamic adjustment of the gain factor G in response to near instantaneous changes in load current ILD.
Alternatively, controller 355 according to an embodiment may be implemented using a microprocessor, microcontroller, a programmable logic array, a portion of an application specific integrated circuit (ASIC), or other integrated circuit device, or using discrete components, or any combination thereof. For DSP, microprocessor and microcontroller embodiments, controller 355 may operate in accordance with a sequence of programmed instructions that are executed by the DSP, microprocessor, or microcontroller to provide power regulation as described herein. For programmable logic and ASIC embodiments, controller 355 may be configured to operate in accordance with a sequence of Hardware Descriptive Language (HDL) statements. Referring back to FIG. 2, controller 355 may be implemented on a die, which die may be shared with the microelectronics device and with some of the other components of the regulator 100 being external to the die.
Thus, a system and method for providing efficient power supply regulation for one or more microelectronics devices that require multiple input voltages has been shown. As is apparent from the description shown herein, embodiments of the present invention may be configured to support many different and variable regulation schemes for the different supply voltages as determined by a system designer.
In particular, an embodiment serves to provide a larger dynamic window for the second (or multiple lower) processor power supply voltages, thereby allowing less stringent regulation schemes that permit power delivery and decoupling to be implemented at relatively lower cost while achieving the same performance of the microelectronics device. Furthermore, the thermal characteristics of the microelectronics device are not compromised as the total power dissipation is not adversely impacted for the system according to an embodiment. The small extra thermal dissipation during light load conditions (e.g. leakage current draw) adds no considerable thermal burden on the microelectronics device because its system thermal cooling is designed for the worst case scenario.
While embodiments of the present invention have been described hereinabove, these embodiments are intended to be illustrative, and should not be construed as limitations on the scope of the invention. Many variations are possible without departing from the spirit and scope of the present invention. Accordingly, the scope of the present invention should be determined not by the embodiments illustrated above, but by the claims appended hereto and their legal equivalents.
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|DE112007002238T5||Sep 21, 2007||Jul 23, 2009||Intel Corporation, Santa Clara||Spannungswandler mit Mehrfachausgang und Mehrfachtopologie|
|U.S. Classification||361/18, 323/272|
|International Classification||G06F1/26, H02J1/08, H02M3/156|
|Cooperative Classification||H02J1/08, H02M3/156, Y10T307/50, G06F1/26|
|European Classification||H02M3/156, G06F1/26, H02J1/08|
|Jan 24, 2002||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KUMAR, PAVAN M.;HUANG, LILLY;REEL/FRAME:012536/0260
Effective date: 20020122
|Dec 11, 2007||FPAY||Fee payment|
Year of fee payment: 4
|Dec 11, 2007||SULP||Surcharge for late payment|
|Dec 17, 2007||REMI||Maintenance fee reminder mailed|
|Sep 21, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Jan 15, 2016||REMI||Maintenance fee reminder mailed|
|Jun 8, 2016||LAPS||Lapse for failure to pay maintenance fees|
|Jul 26, 2016||FP||Expired due to failure to pay maintenance fee|
Effective date: 20160608