|Publication number||US6775282 B1|
|Application number||US 09/472,858|
|Publication date||Aug 10, 2004|
|Filing date||Dec 27, 1999|
|Priority date||Dec 27, 1999|
|Publication number||09472858, 472858, US 6775282 B1, US 6775282B1, US-B1-6775282, US6775282 B1, US6775282B1|
|Inventors||Ramamohan R. Vakkalagadda, Venu M. Kuchibhotla, Michael N. Derr|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (8), Classifications (10), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to bus communication.
A digital device often includes a bus that enables components to communicate with each other. Bus communication between the components may consume a substantial portion of the power available to a device.
In one aspect, the invention features an apparatus that includes at least two circuits having interfaces for transmitting and receiving bus formatted messages and a port coupled to receive messages from the interfaces. The port broadcasts a first received message that is not destined for one of the circuits to the bus. The port blocks broadcast of a second received message that is destined for one of the circuits to the bus.
Other features and advantages will be appreciated from the following description taken together with the drawings.
FIG. 1 shows a chip in which two circuits share a port on an external bus;
FIG. 2 shows a specific embodiment of the shared port of FIG. 1;
FIG. 3 is a flow chart showing a method of operating the shared port of FIG. 1;
FIG. 4 shows an alternate embodiment of the shared port of FIG. 1;
FIG. 5 is a flow chart showing a method of operating the shared port of FIG. 4;
FIG. 6 shows another integrated circuit in which two circuits share a port on a bus; and
FIG. 7 shows a computer using the chip of FIG. 1.
FIG. 1 shows an integrated chip 10 in which separate circuits 12, 14 share a single communication port 16 to an external bus 18. The circuits 12, 14 communicate with external hardware devices 19 via the port 16 and bus 18 combination. The bus 18 transmits and receives messages according to a selected bus protocol.
In some embodiments, the bus protocol is the Peripheral Component Interconnect (PCI) protocol. This protocol is described in the “PCI Local Bus Specification” maintained by the PCI Special Interest Group, P.O. Box 14070, Portland Oreg. 97214.
Each circuit 12, 14 has an interface 20, 22 capable of both sending and receiving messages formatted in the protocol supported by the external bus 18. Each bus formatted message includes portions for control, address, and data content. The address and data portions of the messages are sent sequentially.
The shared port 16 does not broadcast a message from one of the circuits 12, 14 over the bus 18 if the message has the other circuit 14, 12 sharing the same port 16 as a destination. Instead such messages are sent directly to the other circuit 14, 12 via the shared port 16. For such messages, the port 16 does not toggle the external bus 18. Since the external bus is not toggled, the transmission of such messages uses less power than if messages were communicated over the bus 18.
The port 16 couples to circuits 12, 14 that have interfaces 20, 22 with output terminals 31, 32 and input terminals 33, 34. The interfaces 20, 22 transmit and receive messages according to the protocol of the bus 18. Thus, each interface 20, 22 includes hardware for decoding address and control portions of the messages.
In some embodiments, the circuits 12, 14 are digital bridges that transmit digital bus communications originating from internal buses to the bus 18. Then, each circuit 12, 14 may connect to a different internal bus. For example, the circuit 12 may be a north bridge that couples a bus from a CPU to the bus 18, and the circuit 14 may be a south bridge that couples a second bus from a memory to the bus 18.
FIG. 2 shows one embodiment 30 of the shared port 16 of FIG. 1 that couples to the interfaces 20, 22. Each interface 20, 22 transmits outgoing messages to an associated pair of multiplexers (MUXes) 36, 38, 40. The MUXes 36, 38 also receive messages from the external bus 18. These MUXes 36, 38 selectively connect either one of the circuits 20, 22 or the external bus 18 to the input terminals 34, 33 of the other circuit 22, 20. The MUX 40 can transmit signals from one circuit 12, 14, at a time. The circuits 12, 14 broadcast messages to the external bus via the MUX 40.
The MUX 40 transmits messages to the bus 18 via a line 42. The line 42 connects to a set of input terminals of a MUX 44. The MUX 44.has a second set of input terminals 46′ that receives a constant signal. The constant signal indicates to devices supporting the bus protocol that the port 16 is inactive. At any one time, the MUX 44 is either sending a bus formatted message from one of the circuits 12, 14 or an inactive signal to the external bus 18.
Input terminal selection for the MUXes 36, 38, 40, 44 is controlled by select terminals A, B, C, D. The select terminals A, B, C, D receive control signals from a control module 46. The control module 46 receives address portions of bus formatted messages from the lines 48, 50, 52, prior to arrival of the messages at temporary storage registers R, e.g., parallel banks of digital flip-flops. Each of the lines 48, 50, 52 carries control, address, and data information. Some embodiments do not include the register R on the line 52, because logic of the control module 46 is fast enough to route signals from the line 52 with the register R.
The control module 46 performs destination decoding of the received addresses and transmits select signals responsive to the decoded destinations to select terminals A, B, C, D of the MUXes 36, 38, 40, 44. For example, in response to a message on the line 48 whose destination is an external address, the control module 46 sends signals to terminals C and D to select lines 48 and 42. The control module 46 also sends signals to line B to select line 52 so that messages received back from the bus 18 are routed to the circuit 12. Similarly, in response to a message on the line 48 whose destination address is in the circuit 14, the control module 46 sends a signal to terminal A to select the line 48. At the same time, the control module 46 sends a signal to the terminal B to select line 50 and route data from the circuit 14 back to the circuit 12. The select signals control hardware routing of bus formatted messages to message destinations.
The shared port 30 also has drivers 54, 56 for sending messages to and for receiving messages from the external bus 18. The output driver 54 is an amplifier that toggle bus lines to send digital information. The driver 54 has an enable terminal EN that receives a transmission enable signal. The transmission enable signal of one embodiment is the logical OR of transmission enable signals sent by the interfaces 20, 22 of the two circuits 12, 14.
FIG. 3 is a flow chart illustrating a method 60 of one embodiment for transmitting bus formatted messages. Transmission begins when one of internal circuits 12, 14 of FIG. 1 starts to transmit a message according to the bus protocol (step 62). The transmission starts with control and address portions of the message. The control module 46 receives and decodes the destination address for the message (step 64). While destination decoding proceeds, the address portion of the message is stored in a register R connected to the line 48, 50, 52 transmitting the message.
From decoding results, the control module 46 decides whether the destination address belongs to one of the circuits 12, 14 sharing the port 16 (step 66). If the destination belongs to one of the circuits 12, 14, the control module 46 sends signals to the terminal D and to terminal A or B as appropriate (step 68). The signal to the terminal D causes the MUX 44 to block the message from being broadcast on the external bus 18 and also broadcasts a “port inactive” signal over the bus 18. The signal to terminal A or B directs the message to the circuit 12, 14 that is the message's destination. If the destination is not one of the circuits 12, 14, the control module 46 sends signals to terminals C and D that cause the MUXes 40, 44 to broadcast the message on the external bus 18.
In some embodiments, only messages for preselected address ranges in the circuits 12, 14 are not broadcast on the external bus 18. If one of the circuits 12, 14 transmits a message directed to an address outside of the preselected ranges, the port 16 broadcasts the message to the external bus 18. Then, the message is received back from the port 16 and delivered, via the line 52, to the target circuit 12, 14.
Sending such messages via the external bus 18 may enable the control module 46 to employ less address decode hardware. Using less decode hardware can result in a faster and/or less expensive control module 46.
In the shared port 16, the direct delivery of some messages, i.e., without broadcasting on the bus 18, consumes less power, because the output driver 54 does not have to toggle external bus lines to deliver such messages.
FIG. 4 shows an alternate embodiment 80 of the shared port 16 of FIG.1. The port 80 broadcasts to the external bus 18 control and address portions of all bus formatted messages from the circuits 12, 14. The port 80 does not broadcast to the external bus 18 data portions of messages that have destinations in the circuits 12, 14. The port 50 consumes less power by not toggling bus lines to transmit the data portions of messages between the internal circuits 12, 14.
In the port 80, line 82 and line 84 carry respective control portions and address/data portions of bus formatted messages from the circuits 12, 14. The control portion of all messages is broadcast to the external bus 18 via line 82. For the PCI protocol, the control portion includes FRAME#, IRDY#, TRDY#, DEVSEL#, and STOP# signals. The address and data portions are broadcast to the external bus 18 via the line 84 and the MUX 44 if the destination address does not belong to the circuits 12, 14. For the PCI protocol, the address and data portions of the messages include signals transmitted by AD[31:0], C/BE[3:0]#, and PAR pins of the PCI bus.
In the port 80, message routing is controlled by enable signals from the circuits 12, 14 and by control signals from a control module 86.
Digital signals activate or deactivate the output drivers 88, 89 to transmit signals to the external bus 18. The output drivers 88, 89 receive these signals at enable terminals EN. The activating and deactivating signals are formed by logically ORing the activating/deactivating signals produced by the interface 20, 22 of the circuits 12, 14. Thus, the output drivers 88, 89 are activated if either circuit 12, 14 transmits a signal enabling message transmission.
The control signals control message routing by the MUXes 36, 38, 40 in a manner similar to the signals from the control module 46 shown in FIG. 2. But, the control signals are produced by the control module 86, which lacks address decode hardware and consequently does not decode destination addresses on the lines 48, 50, 52. Instead the control module 86 sends detected bus formatted messages to each potential destination aid monitors for message acceptance signals on the lines 48, 50, 52. From the identity of the lines 48, 50, 52 providing the acceptance signals, the control module 86 determines how to route the messages.
FIG. 5 is a flow chart showing a method 100 of one embodiment for routing a bus formatted message with the port 80 of FIG. 4. The control and address portions of a detected message are routed to all potential targets by the control module 86 (step 102). For example, control and address portions of a message from the circuit 12 are routed to both the circuit 14 and to the external bus 18. Similarly, control and address portions of a message from the external bus 18 would be routed to both internal circuits 12, 14.
Initial routing of control and address portions of the message is performed by sending select signals to the MUXes 36, 38, 40, 44. The values of the select signals are determined by the identity of the line 48, 50, or 52 on which control portions of a message were detected. The control module 86 monitors the lines 48, 50, 52 for messages and sends the select signals to select terminals A, B, C, and/or D.
After routing the control and address portions of the message to the potential destinations, the control module 86 monitors the lines 48, 50, and 52 for message acceptance signals (step 104). One of the lines 48, 50, 52 may transmit an acceptance signal from the actual destination device. The actual destination device generates the acceptance signal in response to internal address decoding, which determines that the destination address matches one of its internal addresses.
If none of the lines generates an acceptance signal, the control module 86 assumes that the destination is the external bus 18. Some busses do not generate acceptance signals in response to specific errors.
The control module 86 determines whether both transmitting and accepting devices are the internal circuits 12, 14 (step 106). Both transmitting and accepting devices are internal circuits 12, 14 if both the transmission and acceptance signals come from the lines 48 and 50. Thus, this determination does not require decoding of the address portion of the message in the port 80.
If both the transmitting and accepting devices are internal circuits 12, 14, the control module 86 blocks transmission of data portions of the message to the external bus 18 (step 108). In response to the acceptance signal, the control module 86 also routes the data portion of the message to the accepting device (step 110).
To block transmission to the external bus 18, the control module signals terminal D to select feedback loop 90 as an input line for the MUX 44. While the feedback loop 90 is selected, MUX 44 broadcasts the previously broadcast signal, e.g., the address signal, to the external bus 18. The control module 86 continues to signal the MUX 44 to select the feedback loop 90 while the data portion of the message is being transmitted between circuits 12, 14. Then, the signal from the output driver 88 remains the same as long as the data portion is being transmitted. Broadcasting the same signal reduces power consumption, because the output driver 88 does not toggle the lines of the external bus 18.
FIG. 6 shows an alternate integrated chip 120 in which the circuits 12, 14 share a port to the external bus 18. The chip 120 includes a control module 122 that monitors lines 48, 50 for outgoing bus formatted messages. If an outgoing message is detected, the control module 122 sends a signal to the terminal C of the MUX 40 so that the line 48, 50 sending the message is connected to output driver 124. The output driver 124 broadcasts the message on the external bus 18 in response to an enable signal received at t terminal EN. As described above, the signal received by the terminal EN is the logical OR of activation/deactivation signals produced by each interface 20, 22.
In the chip 120, each bus formatted message from the circuits 12, 14 is broadcast on the external bus 18. Similarly, each message received from the external bus is sent to the interface 20, 22 of both circuits 12, 14 by amplifier 126 and line 128.
In the chip 120, each internally generated bus formatted message is broadcast to the external bus 18, i.e., even messages having the other internal circuit 12, 14 as destination are broadcast to the bus 18. Thus, the chip 120 does not conserve power by not broadcasting a portion of the bus cycles to the external bus 18. Nevertheless, the circuits 12, 14 do share the same output driver 124 and reception amplifier 126. Sharing these devices lowers engineering, construction, and/or product costs for the chip 120.
FIG. 7 is a block diagram of a computer 130 that uses the chip 10 of FIG. 1 or another embodiment as a bridge between internal busses 144, 146 and the external bus 18′. The computer 130 includes a central processing unit (CPU) 132, a memory 134, a graphics controller 136, a cardbus controller 138, a hard or CDROM drive 140, and a keyboard 142. The graphics and cardbus controllers 136, 138 connect to the external bus 18′, i.e., a PCI bus, which is bridged to busses 144, 146 via the chip 10. The busses 144 and 146 connect to the CPU 132 and the memory 134, respectively.
The two circuits 12, 14 are controllers of operations between the internal busses 144, 146, 148, 150 and between the internal busses 144, 146, 148, 150 and the external bus 18′. In-some embodiments, the circuit 12 is a north bridge that controls transactions between the CPU 132, the memory 134, and the PCI and internal busses 18′, 148, 150. In these embodiments, the circuit 14 is a south bridge that controls transactions between peripherals such as the hard or CDROM drive 140 and keyboard 142 and the PCI and internal busses 18′, 144, 146.
Other aspects, advantages, and modifications are within the scope of the following claims.
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|U.S. Classification||370/392, 710/313, 710/107, 370/438|
|International Classification||H04L12/28, G06F13/40|
|Cooperative Classification||G06F13/4027, Y02B60/1235, Y02B60/1228|
|Apr 10, 2000||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VAKKALAGADDA, RAMAMOHAN R.;KUCHIBHOTLA, VENU M.;DERR, MICHAEL N.;REEL/FRAME:010737/0457;SIGNING DATES FROM 20000328 TO 20000404
|Feb 8, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Feb 18, 2008||REMI||Maintenance fee reminder mailed|
|Sep 21, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Mar 18, 2016||REMI||Maintenance fee reminder mailed|
|Aug 10, 2016||LAPS||Lapse for failure to pay maintenance fees|
|Sep 27, 2016||FP||Expired due to failure to pay maintenance fee|
Effective date: 20160810