|Publication number||US6782611 B2|
|Application number||US 09/398,652|
|Publication date||Aug 31, 2004|
|Filing date||Sep 17, 1999|
|Priority date||Dec 19, 1997|
|Also published as||US5991161, US6097611, US20010047882|
|Publication number||09398652, 398652, US 6782611 B2, US 6782611B2, US-B2-6782611, US6782611 B2, US6782611B2|
|Inventors||William A. Samaras, Paul T. Phillips, Michael P. Brownell|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (1), Classifications (45), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of application Ser. No. 08/993,793, which was filed Dec. 19, 1997 now U.S. Pat. No. 5,991,161.
1. Field of the Invention
The invention relates generally to chip carriers, and more specifically, to a multi-chip land grid array carrier.
2. Description of Related Art
Computer processors include various cache memories, including memory caches and disk caches. A memory cache is a portion of memory made of high-speed static random access memory (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory. Memory caching is effective because most programs access the same data or instructions over and over. By keeping as much of this information as possible in SRAM, the computer avoids accessing the slower DRAM.
Some memory caches are built into the architecture of microprocessors. Such internal caches are often called primary, or Level 1 (L1) caches. Many computers also come with external cache memory, called Level 2 (L2) caches. The L2 cache is coupled to a dedicated bus, sometimes referred to as a “backside bus.” Like L1 caches, L2 caches are composed of SRAM but they are typically much larger. The L2 cache improves system-level performance by improving the processor's memory read and write performance, as well as decreasing the system bus utilization. The large L2 cache results in less processor read requirements to main memory, thereby reducing the number of times the processor needs to access the system bus.
For example, the IntelŪ PentiumŪ Pro processor package includes the microprocessor chip and an L2 cache die packaged in a single package. The microprocessor chip and the L2 cache memory die are both mounted in a dual-cavity microprocessor package. The microprocessor package may then be mounted on a system motherboard. The tight coupling of the microprocessor chip and the L2 cache improves system performance and efficiency. The PentiumŪ Pro processor architecture is described in the Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, 1996/1997, available from IntelŪ Corporation, and in PentiumŪ Pro Processor System Architecture, Mindshare, Inc., 1997, both of which are incorporated by reference herein in their entirety.
While cache devices are often implemented using multiple memory chips, a design such as the PentiumŪ Pro L2 cache comprises a single die. The size of the L2 cache varies according to various models of the PentiumŪ Pro available. For example, the processor may be implemented with 256 KB, 512 KB, 1 MB, etc. of L2 cache capacity. Manufacturing the single, large memory die for the L2 cache may be difficult and expensive. Defects in a single-die L2 cache may not be discoverable until after the processor and L2 cache die are assembled into their shared package. If a defect is found in the L2 cache after it is assembled into the microprocessor package, the entire package often must be scrapped. Thus, it may be desirable to implement the L2 cache in a manner that allows additional flexibility and simplifies manufacturing and testing.
Mounting the cache memory chips directly to a motherboard, as in many prior art cache implementations, greatly reduces performance. With cache memory implemented on the motherboard, each semiconductor die comprising the memory device is typically mounted in a conventional single-die package. The single-die packages are then soldered directly to the motherboard or mounted in sockets. The speed at which the cache runs is significantly slower when implemented on the motherboard.
In a compromise solution, single-die memory devices are coupled to a daughterboard along with the microprocessor. The daughterboard is then plugged into the motherboard. While this cache implementation improves performance over directly mounting the cache memory packages on the motherboard, it requires a larger footprint since the cache comprises several conventional single-die packages. Moreover, the daughterboard implementation still operates at a significantly slower speed than an integrated L2 cache. In one prior art daughterboard L2 cache implementation, the L2 cache operates at only half the speed of the processor.
Rather than using several single-die memory devices for an L2 cache, several semiconductor dice could be directly mounted in a processor package using conventional methods, such as controlled collapse chip connection (C4). This also has drawbacks. For example, the memory device semiconductor die may not be tested until mounted along with the microprocessor chip. If a single memory chip is defective, the entire microprocessor package must be scrapped, as removing and replacing a single semiconductor die is, at best, very difficult if not impossible.
The present invention addresses some of the above mentioned and other problems of the prior art.
In one aspect of the invention, a land grid array (LGA) carrier includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conductive pads coupled thereto.
In another aspect of the invention a method of assembling a multi-chip device includes fabricating an interposer having a first surface and a second surface and populating the second surface with a plurality of conductive pads. A solder ball is coupled to each of predefined conductive pads, and a plurality of semiconductor dice and a plurality of passive devices are coupled to the first surface.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
FIG. 1 is a plan view of a first surface of a multi-chip land grid array (LGA) carrier in accordance with an embodiment of the invention;
FIG. 2 is an end view of the multi-chip LGA carrier of FIG. 1;
FIG. 3 is a plan view illustrating the bottom portion of an embodiment of the LGA chip carrier in accordance with the invention;
FIG. 4 is a partial plan view showing a portion of the bottom portion of an embodiment of the LGA chip carrier in accordance with the invention, illustrating solder balls coupled to some of the conductive pads;
FIG. 5 is a partial end view of the embodiment illustrated in FIG. 4; and
FIG. 6 is a plan view illustrating an embodiment of an LGA carrier in accordance with the invention, coupled to a substrate with a single chip package.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
FIG. 1 is a plan view and FIG. 2 is an end view illustrating an exemplary land grid array (LGA) carrier 10 in accordance with an embodiment of the invention. The LGA carrier 10 includes an interposer 12, which in one embodiment of the invention is fabricated out of organic advanced circuit board material, as is known in the art. The interposer provides a substrate to which electronic components are coupled, thus acting as a multi-chip subassembly in a multi-chip package. The top surface 13 of the interposer 12 includes a first portion 14 that is adapted to receive a plurality of semiconductor dice 16 and passive components 18, such as capacitors, resistors and inductors. The semiconductor dice 16 may be coupled to the first portion 14 using controlled collapse chip connection (C4), as is known in the art. Other methods of coupling the semiconductor dice 16 may also be employed.
The interposer 12 may include a second portion 20 located about the periphery of the interposer 12 top surface 13. Particular embodiments of the interposer 12 employ the second portion 20 to provide a “handling area,” supplying adequate space for assembly machines, such as automated pick-and-place devices, to handle the interposer 12. In one embodiment, the second portion 20 is about 5 to 7 mm wide (reference 22).
The interposer 12 further includes a bottom surface 24 that has a plurality of conductive pads 26 coupled thereto. A plurality of conductive traces (not shown) are placed within the interposer 12 in a predefined manner to route power, signals, etc. to the components 16, 18 and electrically couple the various components 16, 18 together. The conductive traces also selectively couple the components 16, 18 to a plurality of vias 28, which in turn, couple the components 16, 18 to at least some of the conductive pads 26.
FIG. 3 illustrates the bottom surface 24 of an embodiment of the interposer 12 in accordance with the present invention. In the embodiment of the interposer 12 illustrated in FIG. 3, the plurality of conductive pads 26 cover essentially the entire bottom surface 24. In the embodiment of FIG. 3, the conductive pads 26 are arranged in an array of rows and columns, though alternate arrangements may be used. In one embodiment, the array of conductive pads 26 includes 41 rows and 27 columns, while in another embodiment, the array includes 41 rows and 45 columns. Thus, the bottom surface 24 may include over 1,800 conductive pads. Some of the conductive pads 26 are coupled to the vias 28, in turn coupling the conductive pads 26 to the components 16, 18 on the top surface 13, while other conductive pads 26 are not coupled to the vias 28.
FIG. 4 is a partial plan view of the bottom surface 24, and FIG. 5 is a partial end view of the interposer 12 of an embodiment of the invention. The conductive pads 26 that are electrically coupled to the components 16, 18 on the top surface 13 of the interposer 12 have a solder ball 30 attached thereto for coupling the interposer 12 to a surface of another substrate (not shown) or other device. Alternatively, the conductive pads 26 that are electrically coupled to the components 16, 18 may have pins (not shown) attached thereto for coupling the interposer 12 to the substrate or other device.
Moreover, the conductive pads 26 that are not coupled to the components 16, 18 on the top surface 13 do not have a solder ball 30 attached thereto. Thus, essentially the entire bottom surface 24 of the interposer 12 may be populated with conductive pads 26, but only preselected conductive pads 26 have a solder ball 30 coupled thereto. In other words, this embodiment of the present invention provides a large, ball grid array (BGA) device that includes unused pads 26 on the bottom surface 24. Pads that are unused in the specific device do not have solder balls attached thereto. This adds flexibility in design and rework of specific embodiments of the LGA carrier 10. Still further, in one embodiment, only a preselected portion of the conductive pads 26 having solder balls 30 coupled thereto are tested during the manufacturing process, additionally reducing manufacturing costs.
FIG. 6 is a plan view, illustrating an embodiment of an LGA carrier 10, in accordance with an embodiment of the invention, coupled to another substrate 50, along with a single-chip device 52. The interposer 12 includes a plurality of semiconductor dice 16 and passive devices 18 coupled to the interposer 12. In one embodiment, the single-chip device 52 comprises a microprocessor device, and the semiconductor dice 16 comprise memory chips that function as an L2 cache of the microprocessor device. The passive components 18 may include capacitors, resistors and inductors arranged as filters to facilitate high-speed device operation. Thus, the interposer acts as a multi-chip subassembly in a multi-chip package. In FIG. 6, the interposer 12 is shown having four semiconductor dice 16 coupled thereto, though other arrangements, including different quantities of semiconductor dice, are envisioned.
Coupling the semiconductor dice 16 to the interposer 12, as illustrated in FIG. 6, rather than coupling the semiconductor dice 16 directly to the substrate 50, allows pretesting of the semiconductor dice 16. For example, if the semiconductor dice 16 comprise memory chips of a microprocessor L2 cache, the memory chips may be tested “at speed” prior to being coupled to the substrate 50, along with the microprocessor device 52. If the pretesting discovers defects, the LGA carrier 10 may be reworked or scrapped prior to coupling the interposer 12 to the substrate 50. The LGA carrier 10 allows simpler attachment of multiple semiconductor dice 16 to the substrate 50. Once the LGA carrier 10 multi-chip subassembly is implemented in a multi-chip assembly, as in FIG. 6, the multiple semiconductor dice 16 may be simultaneously removed from the substrate 50 of defective assemblies, if necessary.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5334857 *||Apr 6, 1992||Aug 2, 1994||Motorola, Inc.||Semiconductor device with test-only contacts and method for making the same|
|US5483421 *||Mar 9, 1992||Jan 9, 1996||International Business Machines Corporation||IC chip attachment|
|US5635847 *||May 15, 1995||Jun 3, 1997||International Business Machines Corporation||Apparatus for testing circuits and/or burning-in chips|
|US5680936 *||Mar 14, 1995||Oct 28, 1997||Automated Technologies Industries, Inc.||Printed circuit board sorting device|
|US5689091 *||Sep 19, 1996||Nov 18, 1997||Vlsi Technology, Inc.||Multi-layer substrate structure|
|US5983490 *||Jul 3, 1997||Nov 16, 1999||Matsushita Electric Industrial Co., Ltd.||Conductive ball mounting apparatus|
|US5990564 *||May 30, 1997||Nov 23, 1999||Lucent Technologies Inc.||Flip chip packaging of memory chips|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20140177363 *||Dec 26, 2012||Jun 26, 2014||Broadcom Corporation||Method and system for automated device testing|
|U.S. Classification||29/840, 257/E23.067, 174/255, 257/E23.069, 29/593, 257/723, 361/768, 257/E25.029, 361/767, 257/724, 29/830, 29/832, 324/762.06, 324/754.18, 324/759.01, 324/754.08|
|International Classification||H05K3/34, H01L23/498, H05K1/14, H05K1/02, H01L25/16, H05K3/36|
|Cooperative Classification||Y10T29/49126, Y10T29/49149, Y10T29/49144, Y10T29/4913, Y10T29/49128, Y10T29/49004, H01L2924/0002, H01L23/49816, H01L25/16, H05K2201/10734, H05K3/3436, H05K2201/10674, H05K1/023, H05K3/368, H01L23/49827, H05K2201/09781, H05K2201/10719, H05K1/141|
|European Classification||H01L23/498C4, H01L23/498E, H05K1/14B, H05K1/02C2E, H01L25/16|
|Feb 28, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Mar 10, 2008||REMI||Maintenance fee reminder mailed|
|Sep 21, 2011||FPAY||Fee payment|
Year of fee payment: 8