Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6788605 B2
Publication typeGrant
Application numberUS 10/195,818
Publication dateSep 7, 2004
Filing dateJul 15, 2002
Priority dateJul 15, 2002
Fee statusPaid
Also published asCN1495899A, EP1383134A1, US6894918, US20040008542, US20040202022
Publication number10195818, 195818, US 6788605 B2, US 6788605B2, US-B2-6788605, US6788605 B2, US6788605B2
InventorsManish Sharma, Frederick Perner
Original AssigneeHewlett-Packard Development Company, L.P.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Shared volatile and non-volatile memory
US 6788605 B2
Abstract
The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.
Images(12)
Previous page
Next page
Claims(16)
What is claimed:
1. A memory back-up system comprising:
a first memory cell;
a non-volatile memory cell that is interfaced to the first memory cell;
control circuitry that allows data to be written to one of the first memory cell and the non-volatile memory cell, and that provides transfer of the data from one of the first memory cell and the non-volatile memory cell to the other one of the first memory cell and the non-volatile memory cell; and
a shared control line connected to the first memory cell and the non-volatile memory cell that allows the first memory cell and the non-volatile memory cell to be written to and read from at the same time.
2. The memory back-up system of claim 1, wherein the control circuitry further includes allowing data to be read from one of the first memory cell and the non-volatile memory cell.
3. The memory back-up system of claim 1, wherein the first memory cell and the non-volatile memory cell are integrated on a common substrate.
4. The memory back-up system of claim 1, wherein the non-volatile memory cell is an MRAM memory cell.
5. The memory back-up system of claim 1, wherein the first memory cell is formed adjacent to a substrate, and the non-volatile memory cell is formed adjacent to the first memory cell.
6. The memory back-up system of claim 1, further comprising a plurality of first memory cells and a plurality of non-volatile memory cells.
7. The memory back-up system of claim 6, wherein the plurality of first memory cells and the plurality of non-volatile memory cells are integrated on a common substrate.
8. The memory back-up system of claim 6, wherein the plurality of first memory cells and the plurality of non-volatile memory cells are accessed through a common set of access control lines.
9. The memory back-up system of claim 8, wherein the common set of access control lines comprise at least one of row select lines and column select lines.
10. The memory back-up system of claim 6, wherein the plurality of first memory cells and the plurality of non-volatile memory cells comprise a shared set of wide data lines.
11. The memory back-up system of claim 10, wherein the shared set of wide data lines comprises at least 256 data lines.
12. The memory back-up system of claim 1, wherein a single word line WL is connected to both the first memory cell and the non-volatile memory cell.
13. The memory back-up system of claim 12, wherein the first memory cell is DRAM memory cell and the non-volatile memory cell is an MRAM memory cell.
14. The memory back-up system of claim 13, wherein the single word line WL is connected to a DRAM controlling transistor gate of the DRAM memory cell and to a MRAM controlling transistor gate of the MRAM memory cell.
15. A memory back-up system comprising:
a plurality of first memory cells;
a plurality of non-volatile memory cells that are interfaced to the first memory cells;
control circuitry that allows data to be written to one of the first memory cells and the non-volatile memory cells, and that provides transfer of the data from one of the first memory cells and the non-volatile memory cells to the other one of the first memory cells and the non-volatile memory cells:
shared control lines connected to the first memory cells and the non-volatile memory cells that allows the first memory cells and the non-volatile memory cells to be written to and read from at the same time.
16. The memory back-up system of claim 15, wherein the control circuitry further includes allowing data to be read from one of the first memory cells and the non-volatile memory cells.
Description
FIELD OF THE INVENTION

The invention relates generally to electronic memory. More particularly, the invention relates to shared volatile and non-volatile memory.

BACKGROUND OF THE INVENTION

Electronic memory devices include both volatile and non-volatile memory. Volatile memory is memory that loses its content (data) when power connected to the memory is turned off. Presently, most random access memory (RAM) is volatile. Non-volatile memory is memory that retains its content (data) even when power connected to the memory is turned off. Read only memory (ROM), for example, is generally non-volatile memory.

Dynamic random access memory (DRAM) is a type of volatile memory. DRAM is the most common RAM used in personal computers and workstations. DRAM is dynamic, and unlike static RAM (SRAM), DRAM needs to have its storage cells refreshed or provided with a new electronic charge every few milliseconds. DRAM generally stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly, therefore requiring recharging.

FIG. 1 shows a DRAM cell 100. The DRAM cell 100 includes a charging capacitor CD, and a transistor QD. A logical state, or bit, is stored by the DRAM cell 100 by storing a charge on the charging capacitor CD. The charge on the capacitor CD can be sensed by selecting the DRAM cell 100 through a word line WL, and sensing the voltage across the capacitor CD through a bit line BL. Generally, sensing the voltage across the capacitor CD discharges the capacitor CD, requiring the capacitor CD to be recharged.

Magnetic random access memory (MRAM) is a type of non-volatile memory. MRAM includes storing a logical state, or bit, by setting magnetic field orientations of an MRAM cell. The magnetic field orientations remain even when power to the MRAM cell is turned off.

FIG. 2 shows an MRAM cell 200. The MRAM memory cell 200 includes a soft magnetic region 220, a dielectric region 230 and a hard magnetic region 210. The orientation of magnetization within the soft magnetic region 220 is non-fixed, and can assume two stable orientations as shown by the arrow M1. The hard magnetic region 210 (also referred to as a pinned magnetic region) has a fixed magnetic orientation as depicted by the arrow M2. The dielectric region 230 generally provides electrical insulation between the soft magnetic region 220 and the hard magnetic region 210.

As previously stated, the orientation of magnetization of the soft magnetic region 220 can assume two stable orientations. These two orientations, which are either parallel or anti-parallel to the magnetic orientation of the hard magnetic region 210, determine the logical state of the MRAM memory cell 200.

The magnetic orientations of the MRAM memory cells are set (written to) by controlling electrical currents flowing through the word lines and the bit lines, and therefore, by the corresponding magnetic fields induced by the electrical currents. Because the word line and the bit line operate in combination to switch the orientation of magnetization of the selected memory cell (that is, to write to the memory cell), the word line and the bit line can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic value stored in the memory cells.

The orientation of magnetization of the soft magnetic region 220 is determined in response to electrical currents applied to the bit lines (BL) and the word lines (WL) during a write operation to the MRAM memory cell. The electrical currents applied to the bit line and the word line set the orientation of the magnetization of the soft magnetic layer depending upon the directions of the currents flowing through the bit line and the word line, and therefore, the directions of the induced magnetic fields created by the currents flowing through the bit line and the word line.

The MRAM memory cells are read by sensing a resistance across the MRAM memory cells. The resistance is sensed through the word lines and the bit lines.

Reading and writing to MRAM memory cells can take longer than reading and writing to DRAM cells. However, MRAM memory cells offer the advantage of being non-volatile.

Some of the advantages offered by MRAM and DRAM can be realized by physically placing an MRAM integrated circuit that includes an array of MRAM cells proximate to a DRAM integrated circuit that includes an array of DRAM cells. The MRAM, for example, could be used to back up the DRAM. This configuration can be advantageous if a power supply to the DRAM is turned off. This configuration, however, is problematic because physical limitations require the DRAM and MRAM integrated circuits to have a relatively small number of input/output lines. Therefore, backing up an entire array of DRAM cells can be time consuming and complicated because generally the number of input/output lines that access the array of DRAM memory cells is much smaller than the number of memory cells within the array of DRAM memory cells.

It is desirable to have a memory system that includes the benefits of both volatile and non-volatile memory. It is desirable that the memory system should allow for efficient transfer of large amounts of data between the volatile and non-volatile memory.

SUMMARY OF THE INVENTION

The invention includes an apparatus and a method for providing a memory system that includes the benefits of both volatile and non-volatile memory. The memory system allows for efficient transfer of large amounts of data between the volatile and non-volatile memory.

A first embodiment of the invention includes a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell.

Another embodiment of the invention includes memory back-up system. The memory back-up system includes a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art DRAM memory cell.

FIG. 2 shows a prior art MRAM memory cell.

FIG. 3 shows a shared memory cell according to an embodiment of the invention.

FIG. 4 shows an array of memory cells according to an embodiment of the invention.

FIG. 5 shows a shared memory cell according to another embodiment of the invention.

FIGS. 6A, 6B, 6C, 6D, 6E show a process for forming the embodiment of FIG. 5.

FIG. 7 shows a shared memory system according to an embodiment of the invention.

FIG. 8 shows a computing unit that includes a CPU and a shared memory system according to an embodiment of the invention.

FIG. 9 shows an imaging system according to an embodiment of the invention.

DETAILED DESCRIPTION

As shown in the drawings for purposes of illustration, the invention is embodied in an apparatus and a method for integrating volatile and non-volatile memory. The memory system allows for efficient transfer of large amounts of data between the volatile and non-volatile memory.

FIG. 3 shows an embodiment of the invention. This embodiment includes a shared DRAM/MRAM memory cell 300 that includes a first memory cell 310, and a non-volatile memory cell 320 that is interfaced to the first memory cell 310.

The first memory cell 310 can include a DRAM memory cell. The DRAM memory cell shown in FIG. 3 includes a DRAM controlling transistor QD and a charging capacitor CD. Charge is both stored on the charging capacitor CD, and sensed from the charging capacitor CD through a word line WL and a bit line DBL.

The non-volatile memory cell 320 can include an MRAM memory cell. The MRAM memory cell shown in FIG. 3 includes an MRAM controlling transistor QM and a magnetoresistive tunnel junction (MTJ) memory cell. Magnetic states of the MRAM memory cell 320 are set by magnetic fields generated by current flowing through bit line MBL and write word line MWL. The magnetic state of the MRAM cell 320 is sensed, by sensing a resistance of the MTJ memory cell through a sense line MSL and a bit line MBL. As previously described, the magnetic orientation of the MTJ memory cell determines the resistance across the MTJ memory cell.

The MTJ memory cell includes a reference (pinned) layer 326 that includes a preset magnetic orientation. The MTJ memory cell further includes a sense layer 322, and an insulating tunnel barrier 324 that separates the reference layer 326 and the sense layer 322.

The reference layer 326 and the sense layer 322 can be made of a ferromagnetic material.

If the magnetization of the sense layer 322 and the reference layer 326 of the MTJ memory cell are in the same direction, the orientation of the MTJ memory cell can be referred to as being “parallel.” If the magnetization of the sense layer 322 and the reference layer 326 of the MTJ memory cell are in opposite directions, the orientation of the MTJ memory cell can be referred to as being “anti-parallel.” The two orientations, parallel and anti-parallel, can correspond to MTJ memory cell states of low or high resistance respectively.

The insulating tunnel barriers 324 allow quantum mechanical tunneling to occur between the reference layer 326 and the sense layer 322. The tunneling is electron spin dependent, causing the resistance of the MTJ memory cell to be a function of the relative orientations of the magnetization directions of the reference layer 326 and the sense layer 322. The resistance state of the MJT memory cell can be sensed to determine the magnetization orientations of the reference layer 326 and the sense layer 322.

The resistance of the MTJ memory cell is a first value (R) if the magnetization orientation of the MTJ memory cell is parallel and a second value (R+delta) if the magnetization orientation is anti-parallel. The invention, however, is not limited to the magnetization orientation of the two layers, or to just two layers.

The insulating tunnel barrier 324 can be made of aluminum oxide, silicon dioxide, tantalum oxide, silicon nitride, aluminum nitride, or magnesium oxide. However, other dielectrics and certain semiconductor materials may also be used for the insulating tunnel barrier 324. The thickness of the insulating tunnel barrier 324 may range from about 0.5 nanometers to about three nanometers. However, the invention is not limited to this range.

The sense layer 322 may be made of a ferromagnetic material. The reference layer 326 can be implemented as a synthetic ferrimagnet (SF), also referred to as an artificial antiferromagnet.

The non-volatile memory cell can include other types of memory including ferro-electric FeRAM and Flash memory. These other non-volatile types of memory are well known in the art of digital electronics.

The MRAM/DRAM memory cell 300 structure of FIG. 3 allows both the first memory cell 310 and the non-volatile memory cell 320 to be written to and read from at the same time. A single word line WL is connected to both the first memory cell 310 and the non-volatile memory cell 320.

The shared MRAM/DRAM memory cell 300 provides for the integration of MRAM and DRAM memory cells on a common substrate. As will be shown later, the integrated memory cell allows for the formation of integrated memory cell arrays in which large amounts of data can be easily transferred from MRAM cells to DRAM cells, and/or from DRAM cells to MRAM cells.

FIG. 4 shows an array of memory cells according to an embodiment of the invention. That is, a memory cell array 400 can be formed from a plurality of MRAM/DRAM memory cells 300 of FIG. 3. As will be described later, an array of the MRAM/DRAM memory cells can be used to easily transfer large amounts of data between the MRAM and DRAM memory cells.

Many applications exist that can utilize the advantages of the memory cell array 400. The memory cell array 400 can offer the advantages of both volatile and non-volatile memory. The volatile memory can offer fast access, while the non-volatile memory can provide memory back up of the volatile memory.

FIG. 5 shows a shared memory cell according to another embodiment of the invention. FIG. 5 is an embodiment of a physical implementation of the MRAM/DRAM memory cell 300 of FIG. 3.

This embodiment can be fabricated on a substrate 500 of silicon. Diffusion regions in the substrate 500 can be used to form the drain (D) and source (S) of the MRAM controlling transistor QM and the DRAM controlling transistor QD.

A trench formed in the substrate 500 can be filled with conductive material and dielectric material to form the DRAM capacitor CD.

A first metallization layer can be used to form conductive contacts to the source (S) of the MRAM controlling transistor, the gate (G) of the MRAM controlling transistor, the drain (D) of the DRAM controlling transistor (D), the gate (G) of the DRAM controlling transistor and the DRAM capacitor. The source of the MRAM controlling transistor can be connected to ground (GND). The gate (G) of the MRAM controlling transistor can be connected to the word line (WL). The drain (D) of the DRAM controlling transistor can be connected to the DRAM bit line DBL. The source (S) of the DRAM controlling transistor is connected to a first terminal of the DRAM capacitor CD. This connection can be formed by forming the source (S) of the DRAM controlling transistor so close to the first terminal of the DRAM capacitor CD that source (S) and the first terminal are electrically connected. A second terminal of the DRAM capacitor CD can be connected to ground (GND).

A second metallization layer can be used to form a conductive contact to the magnetic tunnel junction (MTJ) memory cell of the MRAM memory cell. The conductive contact can be connected to the MRAM bit line MBL.

A third metallization layer can also be used to form a conductive contact to the magnetic tunnel junction device of the MRAM memory cell. The conductive contact can be connected to the MRAM sense line MSL.

A fourth metallization layer can be used to form the MRAM write word line MWL.

The metallization layers can be formed from Tantalum, Copper or Aluminum.

FIGS. 6A, 6B, 6C, 6D, 6E show a process that can be used for forming the embodiment of FIG. 5. Several processing steps are required to form each of the structures shown in FIGS. 6A, 6B, 6C, 6D, 6E. Only a subset of the complete set of processing steps required to form the embodiment have been included in this description.

FIG. 6A shows a first set of processing steps. This set of processing steps includes forming diffusion regions in the substrate 500. The diffusion regions form the sources (S) and drains (D) of the DRAM controlling transistor and the MRAM controlling transistor.

A trench is formed in the substrate. The trench can be formed by a reactive ion etching process. A first metallic layer is deposited in the trench. A dielectric is then deposited in the trench. Finally, a second metallic layer or a poly-silicon is deposited over the dielectric forming the DRAM capacitor CD. The source (S) of the DRAM controlling transistor and the first metallic layer of the DRAM capacitor CD can be formed close enough that they are in electrical contact with each other. The formation of trench capacitors is well known in the art of semiconductor processing.

FIG. 6B shows a second set of processing steps. This set of processing steps includes forming the gates (G) of the MRAM controlling transistor and the DRAM controlling transistor. The gates (G) can be formed by patterning a gate oxide, and then depositing and patterning a poly-silicon to complete the formation of the gates (G).

A dielectric can then be deposited. The dielectric is then etch according to a pattern to allow for creation of a set of vias. The vias are then created by depositing a conductive material into the patterned etched holes. The conductive material can be Tantalum Nitride.

The dielectric and the vias are then typically chemically-mechanically polished to planarize the dielectric and the vias before depositing the previously described first metallization layer. The first metalization layer is then deposited and patterned to form conductive contacts to the source (S) of the MRAM controlling transistor, the gate (G) of the MRAM controlling transistor, the drain (D) of the DRAM controlling transistor (D), the gate (G) of the DRAM controlling transistor and the DRAM capacitor. A via is also formed that is connected to the drain (D) of the MRAM controlling transistor QM, and eventually leads to a connection to the MRAM sense line MSL.

FIG. 6C shows a third set of processing steps. This set of processing steps includes depositing another dielectric layer. The dielectric layer then etch according to a pattern to continue the formation of the MRAM sense line (MSL) connection. The dielectric is typically then chemically-mechanically polished to planarize the dielectric and the via before depositing the previously described second metallization layer.

The second metallization layer is then deposited and patterned to form a conductive contact to the magnetic tunnel junction (MTJ) memory cell of the MRAM memory cell. The conductive contact can be connected to the MRAM bit line MBL.

FIG. 6D shows a third set of processing steps. This set of processing steps includes forming the magnetic tunnel junction (MTJ) memory cell over the MRAM bit line MBL. The formation of the magnetic tunnel junction (MTJ) memory cell includes formation of the previously described sense layer, reference layer and insulating tunnel barrier.

The insulating tunnel barrier 324 can be made of aluminum oxide, silicon dioxide, tantalum oxide, silicon nitride, aluminum nitride, or magnesium oxide. However, other dielectrics and certain semiconductor materials may also be used for the insulating tunnel barrier 324. The thickness of the insulating tunnel barrier 324 may range from about 0.5 nanometers to about three nanometers. However, the invention is not limited to this range.

The sense layer 322 may be made of a ferromagnetic material. The reference layer 326 can be implemented as a synthetic ferrimagnet (SF), also referred to as an artificial antiferromagnet.

Another dielectric layer can then be deposited over the MTJ memory cell and the second metallization layer. This dielectric layer is then etched according to a pattern to allow continuation of the MSL via, and to allow creation of a via to the MTJ memory cell. The vias are then formed by depositing a conductive material in holes created by the etching. The vias and the dielectric layer are then typically chemically-mechanically polished before deposition of the previously described third metallization layer.

The third metallization layer is then deposited to form a conductive contact to the MTJ memory cell of the MRAM memory cell, and the drain (D) of the MRAM controlling transistor QM.

FIG. 6E shows a fourth set of processing steps. This set of processing steps includes depositing another dielectric layer. This dielectric layer can then be chemically-mechanically polished before deposition of the previously described fourth metallization layer.

The fourth metallization layer can then be deposited and patterned to form the MRAM word line MWL. The MRAM word line MWL must be formed in the vicinity of the MTJ memory cell to allow current flowing through the MRAM word line MWL is set magnetic field orientations within the MTJ memory cell.

FIG. 7 shows a shared memory system according to an embodiment of the invention. This system allows large amounts of data to be transferred from DRAM to MRAM, and from MRAM to DRAM, in a single operation. The number of data lines between the DRAM memory cells and the MRAM memory cells can greater than 1024.

An MRAM/DRAM address controller 710 receives a memory address to be accessed from a central processing unit (CPU) or some other type of controller. As with a standard address controller, the MRAM/DRAM address controller 710 generates a row address and a column address. The row address and the column address select one of N rows within either the DRAM or the MRAM, and one of M columns within the DRAM or the MRAM.

The row address is received by an MRAM/DRAM row address decoder 720. The MRAM/DRAM row address decoder 720 effectively generates a word line (WL) selection. The selected word line WL selects one of the N rows of memory of the MRAM and the DRAM.

The column address is received by an MRAM/DRAM column address decoder 730. The MRAM/DRAM column address decoder 730 effectively generates a word line (BL) selection. The selected bit line BL selects one of the M columns of memory of the MRAM and the DRAM.

An array of MRAM memory cells 740 includes N rows and M columns of MRAM memory cells. The array of MRAM memory cells 740 further includes standard MRAM read/write circuitry.

An array of DRAM memory cells 750 includes N rows and M columns of DRAM memory cells. The array of DRAM memory cells 750 further includes standard DRAM read/write circuitry.

A multi-port data register 760 includes wide data registers that are connected to the sense amplifiers and columns of both the array of MRAM memory cells 740 and the array of DRAM memory cells 750. The multi-port data register 760 includes a shared memory I/O which provides the data input and output to the shared arrays of MRAM and DRAM memory. The multi-port data register 760 receives the selected bit line BL from the MRAM/DRAM column address decoder 730. External control lines (not shown) determine whether the registers within the multi-port data register 760 are transferring data to or from the memory cells of the DRAM and/or the MRAM. Multi-port data registers are well known in the art of digital electronics.

Operation of the external control lines, along with the address selection received by the MRAM/DRAM address controller 710, determines which data is being written or read from either the DRAM or the MRAM. The inclusion of the wide data line multi-port data register 760 that is connected to a large number of both DRAM memory cells and MRAM memory cells allows a large amount of data to be transferred from either the DRAM memory cells to the MRAM memory cells, or from the MRAM memory cells to the DRAM memory cells is a single operation.

Many different applications exist for the share memory system of FIG. 7. For example, FIG. 8 shows a computing unit 810 that includes a CPU 830 and a shared memory system 840 according to an embodiment of the invention.

The computing unit 810 can be, for example, a laptop computer. The DRAM memory can be used during normal operation of the laptop, providing fast memory accesses. Sectors of the DRAM can be backed up with the MRAM during periods of time in which the sectors of the DRAM are not being accessed.

If the laptop computer is powered down or put in standby mode, the DRAM is no longer refreshed, and the DRAM loses its data. Through operation of the shared memory system 840, thehe MRAM back up memory can be used to restore the back up data in the DRAM in a single operation.

In some situations, the MRAM memory cells can include faster write operations than the DRAM memory cells. FIG. 9 shows an imaging system 910 in which graphics buffer or camera storage device utilizes the fast write operation of the MRAM memory cells to store images. The fast read capabilities of the DRAM may be used for fast reading of the data. The imaging system 910 generally includes a CPU 930 that controls operation of a shared memory system 940

Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The invention is limited only by the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5250827Jun 18, 1991Oct 5, 1993Seiko Instruments Inc.Semiconductor integrated circuit having a DRAM cell unit and a nonvolatile cell unit
US5640343Mar 18, 1996Jun 17, 1997International Business Machines CorporationMagnetic memory array using magnetic tunnel junction devices in the memory cells
US6285575Apr 4, 2000Sep 4, 2001Nec CorporationShadow RAM cell and non-volatile memory device employing ferroelectric capacitor and control method therefor
US6285586Oct 16, 2000Sep 4, 2001Macronix International Co., Ltd.Nonvolatile static random access memory
US20010023992 *Mar 27, 2001Sep 27, 2001Andreas DollHighly integrated system-on-chip system with non-volatile memory unit
US20030007411 *Jun 26, 2002Jan 9, 2003Haruyasu FukuiData transfer control device, semiconductor memory device and electronic information apparatus
EP0299633A2Jun 22, 1988Jan 18, 1989Ramtron International CorporationProgrammable capacitance divider
JPH11251534A Title not available
Non-Patent Citations
Reference
1Patent Abstracts of Japan vol. 1999, No. 14 Dec. 22, 1999 & JP 11251534A (Fujitsu Ltd) Sep. 17, 1999.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6982445 *Oct 16, 2003Jan 3, 2006Applied Spintronics Technology, Inc.MRAM architecture with a bit line located underneath the magnetic tunneling junction device
US7304887 *Sep 3, 2004Dec 4, 2007Samsung Electronics Co., Ltd.Method and apparatus for multi-plane MRAM
US8174879 *Oct 26, 2009May 8, 2012Hynix Semiconductor Inc.Biosensor and sensing cell array using the same
US8315081Mar 22, 2010Nov 20, 2012Qualcomm IncorporatedMemory cell that includes multiple non-volatile memories
US8719652 *May 12, 2010May 6, 2014Stec, Inc.Flash storage device with read disturb mitigation
Classifications
U.S. Classification365/220, 365/158, 365/189.04, 365/149
International ClassificationH01L27/108, H01L21/8246, G06F12/16, H01L27/10, G11C11/404, G11C11/00, H01L27/105, H01L21/8247, G11C14/00, H01L43/08, H01L27/115, G11C11/22, G11C11/15, H01L21/8242, G11C11/405
Cooperative ClassificationG11C11/404, G11C11/005, G11C14/00, G11C14/0036, G11C11/405
European ClassificationG11C14/00D6, G11C11/405, G11C11/404, G11C11/00C, G11C14/00
Legal Events
DateCodeEventDescription
Sep 21, 2011FPAYFee payment
Year of fee payment: 8
Feb 8, 2008FPAYFee payment
Year of fee payment: 4
Aug 22, 2007ASAssignment
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:019733/0169
Effective date: 20070518
Jun 18, 2003ASAssignment
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., COLORAD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013776/0928
Effective date: 20030131
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. P.O. BOX
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY /AR;REEL/FRAME:013776/0928
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100203;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100420;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100504;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:13776/928
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:13776/928
Jul 15, 2002ASAssignment
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHARMA, MANISH;PERNER, FREDERICK;REEL/FRAME:013123/0007
Effective date: 20020712
Owner name: HEWLETT-PACKARD COMPANY INTELLECTUAL PROPERTY ADMI
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHARMA, MANISH /AR;REEL/FRAME:013123/0007