|Publication number||US6794251 B2|
|Application number||US 10/414,949|
|Publication date||Sep 21, 2004|
|Filing date||Apr 16, 2003|
|Priority date||Dec 31, 2001|
|Also published as||CN1610974A, CN100355086C, EP1476894A2, EP1476894A4, EP1476894B1, US6576516, US7224027, US20030203552, US20050042830, WO2003058684A2, WO2003058684A3|
|Publication number||10414949, 414949, US 6794251 B2, US 6794251B2, US-B2-6794251, US6794251 B2, US6794251B2|
|Inventors||Richard A. Blanchard|
|Original Assignee||General Semiconductor, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Non-Patent Citations (8), Referenced by (12), Classifications (25), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a division of co-pending U.S. patent application Ser. No. 10/039,241 entitled “High Voltage Power MOSFET Having A Voltage Sustaining Region That Includes Doped Columns Formed By Trench Etching And Diffusion From Regions of Oppositely Doped Polysilicon” filed on Dec. 31, 2001 now U.S. Pat. No. 6,576,516.
This application is related to U.S. patent application Ser. No. 09/970,972 entitled “Method For Fabricating A High Voltage Power MOSFET Having A Voltage Sustaining Region That Includes Doped Columns Formed By Rapid Diffusion,” filed in the United States Patent and Trademark Office on Dec. 31, 2001, now U.S. Pat. No. 6,465,304, issued Oct. 15, 2002.
This application is related to copending U.S. patent application Ser. No. 10/039,068 entitled “Method For Fabricating A High Voltage Power MOSFET Having A Voltage Sustaining Region That Includes Doped Columns Formed By Rapid Diffusion,” filed in the United States Patent and Trademark Office on Dec. 31, 2001.
This application is related to copending U.S. patent application Ser. No. 10/038,845 entitled “High Voltage Power MOSFET Having A Voltage Sustaining Region That Includes Doped Columns Formed By Trench Etching and Ion Implantation,” filed in the United States Patent and Trademark Office on Dec. 31, 2001.
This application is related to copending U.S. patent application Ser. No. 10/039,284 entitled “High Voltage Power MOSFET Having A Voltage Sustaining Region That Includes Doped Columns Formed By Trench Etching Using An Etchant Gas That Is Also A Doping Source,” filed in the United States Patent and Trademark Office on Dec. 31, 2001.
The present invention relates generally to semiconductor devices, and more particularly to power MOSFET devices.
Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state while having a low voltage drop and high current flow in the on-state.
FIG. 1 illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer 1 formed over an N+ silicon substrate 2 contains p-body regions 5 a and 6 a, and N+ source regions 7 and 8 for two MOSFET cells in the device. P-body regions 5 and 6 may also include deep p-body regions 5 b and 6 b. A source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1. A drain electrode is provided at the bottom of N+ substrate 2. An insulated gate electrode 18 typically of polysilicon lies primarily over the body and portions of the drain of the device, separated from the body and drain by a thin layer of dielectric, often silicon dioxide. A channel is formed between the source and drain at the surface of the body region when the appropriate positive voltage is applied to the gate with respect to the source and body electrode.
The on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1. The drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer 1. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased. Curve 20 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as curve 20 shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683. This MOSFET is similar to the conventional MOSFET shown in FIG. 2 except that it includes p-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into the drift region of the device. The p-type doped regions 40 and 42 define columns in the drift region that are separated by n-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the p-doped regions 40 and 42. The alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well. As a result, this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone. Curve 25 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG. 3. Clearly, at higher operating voltages, the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1, essentially increasing linearly with the breakdown voltage.
The improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type. The blocking voltage of the transistor thus remains unaltered. The charge compensating columns do not contribute to the current conduction when the device is in its on state. These desirable properties of the transistor depend critically on the degree of charge compensation that is achieved between adjacent columns of opposite doping type. Unfortunately, nonuniformities in the dopant gradient of the columns can be difficult to avoid as a result of limitations in the control of process parameters during their fabrication. For example, diffusion across the interface between the columns and the substrate and the interface between the columns and the p-body region will give rise to changes in the dopant concentration of the portions of the columns near those interfaces. The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture. Another technique for fabricating these devices is shown in copending U.S. application Ser. No. 09/970,972, in which a trench is successively etched to different depths. A dopant material is implanted and diffused through the bottom of the trench after each etching step to form a series of doped regions (so-called “floating islands”) that collectively function like the p-type doped regions 40 and 42 seen in FIG. 3. However, the on-resistance of a device that uses the floating island technique is not as low as an identical device that uses continuous columns.
Accordingly, it would be desirable to provide a method of fabricating the MOSFET structure shown in FIG. 3 that requires a minimum number of epitaxial deposition steps so that it can be produced less expensively while also allowing sufficient control of process parameters so that a high degree of charge compensation can be achieved in adjacent columns of opposite doping type in the drift region of the device.
In accordance with the present invention, a method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
The power semiconductor device formed by the inventive method may be selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a bipolar transistor, and a diode.
In accordance with another aspect of the invention, a power semiconductor device is provided. The device includes a substrate of a first or second conductivity type and a voltage sustaining region disposed on the substrate. The voltage sustaining region includes an epitaxial layer having a first conductivity type and at least one trench located in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. A first layer of polysilicon located in the trench and a second layer of polysilicon is located over the first layer of polysilicon. The column is formed by diffusion of the second dopant from the first layer of the polysilicon into the epitaxial layer. At least one region of the second conductivity is disposed over the voltage sustaining region to define a junction therebetween.
FIG. 1 shows a cross-sectional view of a conventional power MOSFET structure.
FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional power MOSFET.
FIG. 3 shows a MOSFET structure that includes a voltage sustaining region with columns of p-type dopant located below the body region, which is designed to operate with a lower on-resistance per unit area at the same voltage than the structure depicted in FIG. 1.
FIGS. 4(a)-4(d) show a sequence of exemplary process steps that may be employed to fabricate a voltage sustaining region constructed in accordance with the present invention.
In accordance with the present invention, a method of forming the p-type columns in the voltage sustaining layer of a semiconductor power device may be generally described as follows. First, one or more trenches are etched in the n-type doped epitaxial layer that is to form the voltage sustaining region of the device. Each trench is centered where a doped column is to be located. A first layer of p-type doped polysilicon is deposited in the trench. The p-type dopant in the polysilicon is diffused into the n-type doped epitaxial layer that surrounds the trench. Next, a second layer of n-type doped polysilicon is deposited to fill the trench. The dopants from the oppositely doped polysilicon layers interdiffuse, imparting electrical compensation to each other. However, the p-type doped region formed in the epitaxial layer does not undergo significant charge compensation because the diffusion rate of the n-type dopant is greater in polysilicon than in the single crystal silicon that forms the epitaxial layer. The resulting nearly electrically neutral column of polysilicon exhibits a high resistivity and does not contribute to device performance in any significant manner, while the p-type doped single crystal silicon region forms a continuous doped column with smooth sides similar to the one depicted in FIG. 3. In some embodiments of the invention the p-type dopant that is employed is boron and the n-type dopant that is employed is phosphorus, arsenic, or a combination of both.
A power semiconductor device similar to the one shown in FIG. 3 may be fabricated in accordance with the following exemplary steps, which are illustrated in FIGS. 4(a)-4(d).
First, the N-type doped silicon epitaxial layer 501 is grown on a conventionally N+ doped substrate 502. Epitaxial layer 501 is typically 15-50 microns in thickness for a 400-800 V device with a resistivity of 5-40 ohm-cm. Next, a dielectric masking layer is formed by covering the surface of epitaxial layer 501 with a dielectric layer, which is then conventionally exposed and patterned to leave a mask portion that defines the location of the trench 520. The trench 520 is dry etched through the mask openings by reactive ion etching to an initial depth that may range, for example, from 10-45 microns.
The sidewalls of each trench may be smoothed, if needed. First, a dry chemical etch may be used to remove a thin layer of oxide (typically about 500-1000 A) from the trench sidewalls to eliminate damage caused by the reactive ion etching process. Next, a sacrificial silicon dioxide layer is grown over the trench 520. The sacrificial layer is removed either by a buffer oxide etch or an HF etch so that the resulting trench sidewalls are as smooth as possible.
In FIG. 4(b), a layer of p-type doped polysilicon 510 is deposited in the trench 520. A diffusion step is then performed so that the p-type dopant diffuses from the trench 520 into the surrounding epitaxial layer 501, thus forming a p-type doped column 512 of single crystal silicon. In general, the trench depth, dopant dose and the magnitude and duration of the diffusion process should be selected to achieve the desired degree of charge compensation.
Referring to FIG. 4(c), a layer 516 of n-type doped polysilcon is then deposited to fill the trench. A diffusion step is then performed to cause the n-type dopant in polysilcon layer 516 to interdiffuse with the p-type dopant in the polysilicon layer 510. The interdiffusion process is allowed to proceed until the p- and n-type dopants electrically compensate one another so that polysilicon layers 510 and 516 are electrically neutral. The charge compensation can be achieved if the amount of n-type and p-type dopants are properly selected, as described in “On the Semi-Insulating Polcrystalline Silicon Resistor,” by M. K. Lee, C. Y. Lu, K. Z. Chang and C. Shih in Solid State Electronics, Vol. 27, No. 11, pp. 995-1001, 1984, which is hereby incorporated by reference in its entirety.
By providing electrical compensation to the polysilicon layers located in trench 520, a high resistance region is formed within the center of the trench 520. When a reverse voltage is applied to the completed device, this resistance causes a small leakage current to flow between the two high voltage terminals of the device, assuming that any excess charge in the high resistance polysilicon region has the same conductivity type as the doped column 512 of epitaxial silicon. If, however, the high resistance polysilicon region has a conductivity type opposite to doped column 512, it will float “electrically” in the doped column 512 unless the critical electric field is exceeded.
Finally, as shown in FIG. 4(d), the surface of the structure is planarized by removing the polysilicon from its surface.
The aforementioned sequence of processing steps resulting in the structure depicted in FIG. 4(d) provides a voltage sustaining layer with p-type doped columns on which any of a number of different power semiconductor devices can be fabricated. As previously mentioned, such power semiconductor devices include vertical DMOS, V-groove DMOS, and trench DMOS MOSFETs, IGBTs and other MOS-gated devices. For instance, FIG. 3 shows an example of a MOSFET that includes a voltage sustaining layer with doped columns similar to those employed in the present invention, except that in the present invention the doped columns have vertical sidewalls. It should be noted that while FIG. 4 shows a single trench that is used to form the doped column, the present invention encompasses a voltage sustaining regions having single or multiple trenches to form any number of doped columns. For example, a doped column or columns may be located below the center of the gate or in other locations when appropriate to decrease the on-resistance of the device.
Once the voltage sustaining region and the doped column or columns have been formed as shown in FIG. 4, a MOSFET similar to that shown in FIG. 3 can be completed in the following manner. The gate oxide is grown after an active region mask is formed. Next, a layer of polycrystalline silicon is deposited, doped, and oxidized. The polysilcon layer is then masked to form the gate regions. The p+ doped deep body regions 5 b and 6 b are formed using conventional masking, implantation and diffusion steps. For example, the p+-doped deep body regions are boron implanted at 20 to 200 KeV with a dosage from about 1×1014 to 5×1015/cm2. The shallow body regions 5 a and 6 a are formed in a similar fashion. The implant dose for this region will be 1×1013 to 5×1014/cm2 at an energy of 20 to 100 KeV.
Next, a photoresist masking process is used to form a patterned masking layer that defines source regions 7 and 8. Source regions 7 and 8 are then formed by an implantation and diffusion process. For example, the source regions may be implanted with arsenic at 20 to 100 KeV to a concentration that is typically in the range of 2×1015 to 1.2×1016/cm2 after which an oxide layer is formed on the surface. After implantation, the arsenic is diffused to a depth of approximately 0.5 to 2.0 microns. The depth of the body region typically ranges from about 1-3 microns, with the P+ doped deep body region (if present) being slightly deeper. The DMOS transistor is completed in a conventional manner by etching the oxide layer to form contact openings on the front surface. A metallization layer is also deposited and masked to define the source-body and gate electrodes. Also, a pad mask is used to define pad contacts. Finally, a drain contact layer is formed on the bottom surface of the substrate.
It should be noted that while a specific process sequence for fabricating the power MOSFET is disclosed, other process sequences may be used while remaining within the scope of this invention. For instance, the deep p+ doped body region may be formed before the gate region is defined. It is also possible to form the deep p+ doped body region prior to forming the trenches. In some DMOS structures, the P+ doped deep body region may be shallower than the P-doped body region, or in some cases, there may not even be a P+ doped body region.
In some embodiments of the invention it is not necessary to deposit doped layers of polysilicon. Rather, dopant may be added to the first polysilicon layer 510 using gas phase doping. Alternatively, a doped layer of silicon dioxide may be deposited on the polysilicon, which is used as a solid source before it is removed in an etch step. Similarly, dopant may be added to second polysilicon layer 516 from the gas phase or from a doped deposited layer of silicon dioxide, provided the second layer doesn't fill the trench. If gas phase doping is employed, a dielectric layer or a layer of undoped polysilicon is deposited or grown to fill the trench prior to planarization. In contrast, if doped polysilicon is used as the dopant source, it can be used to fill the trench. It is also possible to deposit only one layer of doped polysilicon (e.g., layer 510) and to introduce the dopant that electrically compensates the doped polysilicon using either gas phase doping or by introducing dopant from a solid dopant source as described above. As above, the trench is subsequently filled with a dielectric or undoped polysilicon.
The previous description indicates that the n-type dopant in layer 510 does not diffuse into p-type doped column 512. However, it is in fact possible to use the n-type dopant in layer 516 to compensate some of the p-type dopant in doped column 512, thus providing a technique for adjusting the charge in doped column 512 to obtain maximum (or optimal) breakdown voltage. It is also possible to initially fill the trench with polysilcon that is undoped, then diffuse the first dopant into the polysilicon and the surrounding portion of the epitaxial layer 501 (to form doped column 512) and then diffuse the second dopant into the polysilicon to compensate the first dopant. This approach will produce a doped region that has a dopant concentration gradient that extends from the surface of the wafer to a point beyond the bottom of the trench, which gradient is a function of the trench size, the polysilicon grain size, the trench depth, the amount of dopant introduced, and other variables.
Although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and are within the purview of the appended claims without departing from the spirit and intended scope of the invention. For example, a power semiconductor device in accordance with the present invention may be provided in which the conductivities of the various semiconductor regions are reversed from those described herein. Moreover, while a vertical DMOS transistor has been used to illustrate exemplary steps required to fabricate a device in accordance with the present invention, other DMOS FETs and other power semiconductor devices such as diodes, bipolar transistors, power JFETs, IGBTs, MCTs, and other MOS-gated power devices may also be fabricated following these teachings.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4140558||Mar 2, 1978||Feb 20, 1979||Bell Telephone Laboratories, Incorporated||Isolation of integrated circuits utilizing selective etching and diffusion|
|US4419150||Sep 16, 1982||Dec 6, 1983||Rockwell International Corporation||Method of forming lateral bipolar transistors|
|US4569701||Apr 5, 1984||Feb 11, 1986||At&T Bell Laboratories||Technique for doping from a polysilicon transfer layer|
|US4711017||Mar 3, 1986||Dec 8, 1987||Trw Inc.||Formation of buried diffusion devices|
|US4893160||Nov 13, 1987||Jan 9, 1990||Siliconix Incorporated||Method for increasing the performance of trenched devices and the resulting structure|
|US5108783||Dec 21, 1989||Apr 28, 1992||Sharp Kabushiki Kaisha||Process for producing semiconductor devices|
|US5216275||Sep 17, 1991||Jun 1, 1993||University Of Electronic Science And Technology Of China||Semiconductor power devices with alternating conductivity type high-voltage breakdown regions|
|US5675173||Jan 18, 1996||Oct 7, 1997||Kabushiki Kaisha Toshiba||Semiconductor device having a trench for isolating elements and a trench for applying a potential to a substrate|
|US6188104||Mar 27, 1998||Feb 13, 2001||Samsung Electronics Co., Ltd||Trench DMOS device having an amorphous silicon and polysilicon gate|
|US6215149||Aug 17, 1999||Apr 10, 2001||Samsung Electronics Co., Ltd.||Trenched gate semiconductor device|
|US6274904||Sep 2, 1999||Aug 14, 2001||Siemens Aktiengesellschaft||Edge structure and drift region for a semiconductor component and production method|
|US6455379||Mar 6, 2001||Sep 24, 2002||Fairchild Semiconductor Corporation||Power trench transistor device source region formation using silicon spacer|
|US6465304||Oct 4, 2001||Oct 15, 2002||General Semiconductor, Inc.||Method for fabricating a power semiconductor device having a floating island voltage sustaining layer|
|US6472678||Jun 16, 2000||Oct 29, 2002||General Semiconductor, Inc.||Trench MOSFET with double-diffused body profile|
|US6472708||Aug 31, 2000||Oct 29, 2002||General Semiconductor, Inc.||Trench MOSFET with structure having low gate charge|
|US6479352||Jan 19, 2001||Nov 12, 2002||General Semiconductor, Inc.||Method of fabricating high voltage power MOSFET having low on-resistance|
|US6495884||Jan 23, 2001||Dec 17, 2002||Seiko Instruments Inc.||Vertical MOS transistor|
|US20010026977||Mar 6, 2001||Oct 4, 2001||Hidetaka Hattori||Power semiconductor element capabale of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same|
|US20010036704||Apr 24, 2001||Nov 1, 2001||Koninklijke Philips Electronics N.V.||Trench semiconductor device manufacture with a thicker upper insulating layer|
|US20010053568||Mar 26, 2001||Dec 20, 2001||Gerald Deboy||Method for manufacturing a semiconductor component|
|1||G. Deboy et al., "A New Generation of High Voltage MOSFETs breaks the limit line of silicon," Int'l Electron Devices Meeting Dec. 1998, 26.2.1, pp. 683-685.|
|2||Ming-Kwang Lee et al., "On The Semi-Insulating Polycystalline Silicon Resistor," Solid State Electronics, vol. 27, No. 11, pp. 995-1001, 1984.|
|3||N. Cezac et al., "A New Generation of Power Unipolar Devices: the Concept of the Floating Islands MOS Transistor(FLIMOST)," Proceedings of the 12th International Symposium on Power Semiconductor Devices & ICs, Toulouse, France, May 22-25, 2000, pp. 69-72.|
|4||U.S. patent application Ser. No. 09/970,758, Blanchard et al., filed Oct. 4, 2001.|
|5||U.S. patent application Ser. No. 10/038,845, Blanchard, filed Dec. 31, 2001.|
|6||U.S. patent application Ser. No. 10/039,068, Blanchard, filed Dec. 31, 2001.|
|7||U.S. patent application Ser. No. 10/039,284, Blanchard et al., filed Dec. 31, 2001.|
|8||Xing Bi Chen et al., "A Novel High-Voltage Sustaining Structure With Buried Oppositely Doped Regions," IEEE Transactions on Electron Devices, vol. 47, No. 6, Jun. 2000, pp. 1280-1285.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7019360 *||Feb 23, 2004||Mar 28, 2006||General Semiconductor, Inc.||High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source|
|US7038272 *||Jul 31, 2003||May 2, 2006||Infineon Technologies Ag||Method for forming a channel zone of a transistor and NMOS transistor|
|US7279368||Mar 4, 2005||Oct 9, 2007||Cree, Inc.||Method of manufacturing a vertical junction field effect transistor having an epitaxial gate|
|US7355223||Mar 4, 2005||Apr 8, 2008||Cree, Inc.||Vertical junction field effect transistor having an epitaxial gate|
|US7943466 *||Jan 22, 2010||May 17, 2011||Semiconductor Components Industries, Llc||Method of forming a semiconductor device having sub-surface trench charge compensation regions|
|US8263450 *||Jan 8, 2009||Sep 11, 2012||Infineon Technologies Ag||Power semiconductor component with charge compensation structure and method for the fabrication thereof|
|US20040065909 *||Jul 31, 2003||Apr 8, 2004||Hans Weber||Method for forming a channel zone of a transistor and PMOS transistor|
|US20040164348 *||Feb 23, 2004||Aug 26, 2004||Blanchard Richard A.||High voltage power mosfet having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source|
|US20060199312 *||Mar 4, 2005||Sep 7, 2006||Christopher Harris||Method of manufacturing a vertical junction field effect transistor having an epitaxial gate|
|US20060220072 *||Mar 4, 2005||Oct 5, 2006||Christopher Harris||Vertical junction field effect transistor having an epitaxial gate|
|US20090130806 *||Jan 8, 2009||May 21, 2009||Infineon Technologies Austria Ag||Power semiconductor component with charge compensation structure and method for the fabrication thereof|
|US20100140694 *||Jan 22, 2010||Jun 10, 2010||Shanghui Larry Tu||Semiconductor device having sub-surface trench charge compensation regions and method|
|U.S. Classification||438/268, 438/526, 438/359|
|International Classification||H01L29/78, H01L21/329, H01L21/225, H01L29/10, H01L21/22, H01L29/732, H01L21/331, H01L29/06, H01L21/336|
|Cooperative Classification||H01L29/0649, H01L29/0634, H01L29/7802, H01L29/7395, H01L29/66333, H01L29/1095, H01L21/2257, H01L29/66712|
|European Classification||H01L29/66M6T6F14V, H01L29/66M6T2W4, H01L29/06B2B3R2, H01L29/78B2, H01L29/739C2|
|Aug 19, 2003||AS||Assignment|
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Effective date: 20030701
|Apr 12, 2005||CC||Certificate of correction|
|Oct 31, 2007||FPAY||Fee payment|
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|Mar 7, 2012||FPAY||Fee payment|
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|Apr 29, 2016||REMI||Maintenance fee reminder mailed|
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