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Publication numberUS6809575 B2
Publication typeGrant
Application numberUS 10/407,622
Publication dateOct 26, 2004
Filing dateApr 3, 2003
Priority dateSep 16, 2002
Fee statusPaid
Also published asCN1703659A, US20040051580
Publication number10407622, 407622, US 6809575 B2, US 6809575B2, US-B2-6809575, US6809575 B2, US6809575B2
InventorsGiorgio Oddone, Lorenzo Bedarida, Mauro Chinosi
Original AssigneeAtmel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Temperature-compensated current reference circuit
US 6809575 B2
Abstract
A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.
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Claims(10)
What is claimed is:
1. A current-reference circuit comprising:
a CMOS differential amplifier having first output node comprising a drain of a first n-channel MOS transistor and a second output node comprising a drain of a second n-channel MOS transistor;
a first p-channel MOS transistor having a source coupled to a supply potential, a gate coupled to said second output node, and a drain;
a first PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a first resistor and to a gate of said second n-channel MOS transistor, and a collector and a base both coupled to ground;
a second PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a second resistor in series with a third resistor, and a collector and a base both coupled to ground, a gate of said first n-channel MOS transistor coupled to a common node between said second and third resistors; and
a third n-channel MOS transistor having a drain coupled to said drain of said first p-channel MOS transistor, a source coupled to ground through a fourth resistor, and a gate coupled to a fixed reference potential.
2. The current-reference circuit of claim 1 wherein:
said first and second resistors each have resistance of about 12 K ohms;
said third resistors has a resistance of about 16 K ohms; and
said fourth resistor has a resistance of about 100 K ohms.
3. The current-reference circuit of claim 1 wherein said third n-channel MOS transistor is sized to operate in its subthreshold region.
4. The current-reference circuit of claim 1 wherein said fourth resistor is an n-doped polysilicon resistor.
5. The current-reference circuit of claim 1 wherein said CMOS differential amplifier comprises:
a first p-channel MOS load transistor having a source coupled to said supply potential, and a drain and a gate coupled to said drain of said first n-channel MOS transistor;
a second p-channel MOS load transistor having a source coupled to said supply potential, a gate coupled to said gate of said first p-channel MOS load transistor, and a drain coupled to said drain of said second p-channel MOS transistor; and
an n-channel bias transistor having a source coupled to ground, a drain coupled to a source of said first n-channel MOS transistor and to a source of said second n-channel MOS transistor, and a gate coupled to a bias potential.
6. A current-reference circuit comprising:
a CMOS differential amplifier having first output node comprising the drain of a first n-channel MOS transistor and a second output node comprising the drain of a second n-channel MOS transistor;
a first p-channel MOS transistor having a source coupled to a supply potential, a gate coupled to said first output node, and a drain;
a first PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a first resistor and to a gate of said second n-channel MOS transistor, and a collector and a base both coupled to ground;
a second PNP bipolar transistor having an emitter coupled to said drain of said first p-channel MOS transistor through a second resistor in series with a third resistor, and a collector and a base both coupled to ground, a gate of said first n-channel MOS transistor coupled to a common node between said second and third resistors; and
a third n-channel MOS transistor having a drain coupled to said drain of said first p-channel MOS transistor, a source coupled to ground through a fourth resistor, and a gate coupled to said gate of said first n-channel MOS transistor.
7. The current-reference circuit of claim 6 wherein:
said first and second resistors each have resistance of about 12 K ohms;
said third resistors has a resistance of about 16 K ohms; and
said fourth resistor has a resistance of about 100 K ohms.
8. The current-reference circuit of claim 6 wherein said third n-channel MOS transistor is sized to operate in its subthreshold region.
9. The current-reference circuit of claim 6 wherein said fourth resistor is an n-doped polysilicon resistor.
10. The current-reference circuit of claim 6 wherein said CMOS differential amplifier comprises:
a first p-channel MOS load transistor having a source coupled to said supply potential, and a drain and a gate coupled to said drain of said first n-channel MOS transistor;
a second p-channel MOS load transistor having a source coupled to said supply potential, a gate coupled to said gate of said first p-channel MOS load transistor, and a drain coupled to said drain of said second p-channel MOS transistor; and
an n-channel bias transistor having a source coupled to ground, a drain coupled to a source of said first n-channel MOS transistor and to a source of said second n-channel MOS transistor, and a gate coupled to a bias potential.
Description
PRIORITY CLAIM

This application claims priority to Italian Application Serial Number 2002A000803, filed Sep. 16, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to current-reference circuits. More particularly, the present invention relates to temperature-compensated current-reference circuits.

2. The State of the Art

In integrated circuit applications such as flash memory, EEPROM, and others, certain circuits require a constant current that is independent of variations in temperature and supply voltage.

Numerous techniques exist for designing current references to be unaffected by supply-voltage and temperature variations. One way to generate a current reference that is robust with respect to supply-voltage variation but sensitive to temperature variation is to employ two current mirrors and a resistor as shown in FIG. 1. The current through p-channel MOS transistor 10 is mirrored through p-channel MOS transistor 12. The current through n-channel MOS transistor 14 is mirrored through n-channel MOS transistor 16, having resistor 18 coupled between its source and ground.

The circuit of FIG. 1 has a current variation of up to about 30% as a function of temperature. For circuits of the type shown in FIG. 1, the current generated is equal to:

I=n*Ut*ln(M)/R

if the transistors are in weak inversion and

I=(2/Kn*R 2)*ψ(I)

if the transistors are in strong inversion. In both cases the current is independent of the supply voltage but temperature variation is uncompensated.

Another way to provide a current reference is to employ a resistor and a bipolar transistor as shown in FIG. 2 to generate a current that is proportional to both absolute temperature and the temperature coefficient of the resistor.

P-channel MOS transistors 20 and 22 have their gates driven from the output of operational amplifier 24. PNP bipolar transistor 26 has its emitter coupled to the drain of p-channel MOS transistor 20 and its base and collector coupled to ground. PNP bipolar transistor 28 has its emitter coupled to the drain of p-channel MOS transistor 20 through resistor 30 and its base and collector coupled to ground. One input of operational amplifier 24 is coupled to the drain of p-channel MOS transistor 20 and the other input of operational amplifier 24 is coupled to the drain of p-channel MOS transistor 22.

In the circuit of FIG. 2, the current is given by:

I=(Ut/R)*ln(N)

In order to provide temperature compensation, the temperature coefficient of the resistor must be opposite to Ut.

BRIEF DESCRIPTION OF THE INVENTION

The present invention provides a temperature-compensated current reference using only a MOS transistor and polysilicon resistor of the same type.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 is a schematic diagram of one prior-art current-reference circuit.

FIG. 2 is a schematic diagram of another prior-art current-reference circuit.

FIG. 3 is a schematic diagram of a first illustrative current-reference circuit according to the present invention.

FIG. 4 is a schematic diagram of a second illustrative current-reference circuit according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Persons of ordinary skill in the art will realize that the following description of the present invention is only illustrative and not in any way limiting. Other embodiments of this invention will be readily apparent to those skilled in the art having benefit of this disclosure.

The purpose of the present invention is to obtain a constant current reference that is voltage-supply and temperature compensated. The present invention does not require any special components and is compatible with standard CMOS processes and uses a MOS transistor and polysilicon resistor of one type.

Referring now to FIG. 3, a differential amplifier employs p-channel MOS current-source transistors 40 and 42, n-channel MOS input transistors 44 and 46, and n-channel bias transistor 48.

P-channel MOS transistor 50 supplies current to PNP bipolar transistor 52 through resistor 54 as well as PNP bipolar transistor 56 through a voltage divider comprising resistors 58 and 60. In one illustrative embodiment of the circuit, resistor 54 and 60 may have resistance of about 12 KΩ, and resistor 58 may have a resistance of about 16 KΩ. P-channel MOS transistor 50 also supplies current to N-channel MOS transistor 62 in driving resistor 64 as a source follower. Resistor 64 may have a resistance of about 100 KΩ. The gate of n-channel MOS transistor 62 is driven from a reference voltage Vref that is a fixed value or that can be obtained in different manner as shown in FIG. 4 N-channel MOS transistor 62 is sized such that it operates in its subthreshold region.

The gate of n-channel MOS transistor 44 is driven from the common connection between resistors 58 and 60 (the “MULTIPLE” node). The gate of n-channel MOS transistor 46 is driven from the common connection of PNP bipolar transistor 52 and resistor 54.

The current through the bipolar transistors 52 and 56 is:

I Bip =U t /R 2*[(R 3/R 1)*ln(R 3/R 2)+ln(N*R 3)/R 2)]

Ut is equal to KT/q: This current is a positive function of Ut normalized with respect to resistance.

As will be appreciated by persons of ordinary skill in the art, IBip increases when temperature rises and decreases when the temperature decreases.

The current through n-channel MOS transistor 62 is:

I 62 =Id 0*exp(V GS62 /U t)

Ut is equal to KT/q. This current is a positive function of the Vgs of n-channel MOS transistor 62 and a negative function of Ut.

In particular, the current through n-channel MOS transistor 62 decreases as temperature increases and increases as temperature decreases.

The total current through p-channel MOS transistor 50 is the sum of the currents through bipolar transistors 52 and 56 and n-channel MOS transistor 62:

I tot=(U t /R 2)*[R 3/R 2+ln((N*R 3)/R 2]+Id 0*exp(V GS62 /U t)

If only the n-channel MOS transistor 62 was employed to obtain the temperature compensation, there would have been a linear dependence with respect to temperature contributed by the bipolar portion of the circuit and an exponential dependence contributed by the MOS portion of the circuit. This would not be adequate compensation because, when temperature increases, the current reduction due to the second term of the equation would be too much with respect the current increase related to the first term. With the addition of resistor 64 to n-channel MOS transistor 62, when the temperature increases and the current through n-channel MOS transistor 62 decreases, the excessive reduction of current through n-channel MOS transistor 62 is compensated by the increase of its Vgs, due to the presence of resistor 64. In this way the total current is independent of the supply voltage and a good temperature compensation is obtained.

As previously mentioned, the signal VREF supplied to the gate of MOS transistor 62 can be obtained as a fixed value as illustrated in FIG. 3, or can be also obtained as function of circuitry behavior. Referring now to FIG. 4, a schematic diagram shows another illustrative current-reference circuit according to the present invention. Persons of ordinary skill in the art will observe that the circuit of FIG. 4 is very similar to that of FIG. 3, and the same reference numerals have been used to identify corresponding elements. In the illustrative current-reference circuit of FIG. 4, the signal at the MULTIPLE node at the common connection of resistors 58 and 60 can be used to drive the gate of n-channel MOS transistor 62 instead of the fixed value VREF to obtain a good matching with respect to the bipolar behavior of the circuit. The signal at the MULTIPLE node is in fact a function of bipolar characteristics (FIG. 4) and provides a feedback loop in the circuitry.

The circuit works briefly as follows: when, for example, the temperature rises the bipolar current rises but the voltage value at the MULTIPLE node (and at the node “SINGLE” at the collector of PNP bipolar transistor 52) decreases (the coefficient of the VBE respect the temperature is negative −1.56 mv/C) so that the current through n-channel MOS transistor 62 decreases because of its dependence on temperature and also because the VGS of n-channel MOS transistor 62 is reduced because the voltage at the node MULTIPLE decreases. Therefore, the current through n-channel MOS transistor 62 compensates the increment of the current sunk by the bipolar transistors and, as already mentioned, the excessive VGS reduction is limited by the resistance of resistor 64.

In this way there are two components of the total current, one that rises with increasing temperature and the other that falls with increasing temperature.

It has been shown that with this circuitry of FIGS. 3 and 4, a good temperature compensation has been obtained both with and without feedback.

With this structure, as mentioned, there are several ways to obtain this kind of compensation and the solutions are different both for results both for design approach. In particular it is possible to use n-channel MOS transistor 62 in several cases. It has been said that the current dependence of n-channel MOS transistor 62 is exponential so that the resistance of resistor 64 has been introduced to compensate for the excessive current reduction when the temperature increases. At this point it is possible to decide to drive the gate of n-channel MOS transistor 62 with a fixed voltage from, for example, a BAND GAP reference as shown in FIG. 3) to achieve the best solution or to accept some error, using the signal MULTIPLE to drive the gate of n-channel MOS transistor 62 gate as shown in FIG. 4.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5821564 *May 23, 1997Oct 13, 1998Mosel Vitelic Inc.TFT with self-align offset gate
US6388507 *Jan 10, 2001May 14, 2002Hitachi America, Ltd.Voltage to current converter with variation-free MOS resistor
US6392472 *Sep 18, 2001May 21, 2002Mitsubishi Denki Kabushiki KaishaConstant internal voltage generation circuit
US6407622 *Mar 13, 2001Jun 18, 2002Ion E. OprisLow-voltage bandgap reference circuit
US6452437 *Jul 21, 2000Sep 17, 2002Kabushiki Kaisha ToshibaVoltage generator for compensating for temperature dependency of memory cell current
US6501299 *Dec 18, 2001Dec 31, 2002Hynix Semiconductor Inc.Current mirror type bandgap reference voltage generator
US20030160649 *Aug 19, 2002Aug 28, 2003Mitsubishi Denki Kabushiki KaishaSemiconductor device less susceptible to variation in threshold voltage
Non-Patent Citations
Reference
1B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Series in Electrical and Computer Engineering, pp. 379 and 391, 2001.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7269092 *Apr 21, 2006Sep 11, 2007Sandisk CorporationCircuitry and device for generating and adjusting selected word line voltage
US7456678Oct 10, 2006Nov 25, 2008Atmel CorporationApparatus and method for providing a temperature compensated reference current
US7514987Oct 16, 2006Apr 7, 2009Mediatek Inc.Bandgap reference circuits
US7518930Apr 21, 2006Apr 14, 2009Sandisk CorporationMethod for generating and adjusting selected word line voltage
US20070080740 *Oct 6, 2005Apr 12, 2007Berens Michael TReference circuit for providing a temperature independent reference voltage and current
US20070247957 *Apr 21, 2006Oct 25, 2007Toru MiwaMethod for generating and adjusting selected word line voltage
US20080084240 *Oct 10, 2006Apr 10, 2008Atmel CorporationApparatus and method for providing a temperature compensated reference current
US20100166035 *Dec 23, 2009Jul 1, 2010Jang-Hyun YoonTemperature measuring device
Classifications
U.S. Classification327/539, 327/540
International ClassificationG05F3/24
Cooperative ClassificationG05F3/245
European ClassificationG05F3/24C1
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Apr 3, 2003ASAssignment
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