|Publication number||US6816918 B2|
|Application number||US 10/119,074|
|Publication date||Nov 9, 2004|
|Filing date||Apr 10, 2002|
|Priority date||Apr 10, 2002|
|Also published as||DE60329050D1, EP1359711A2, EP1359711A3, EP1359711B1, US7480741, US20030196005, US20050050080|
|Publication number||10119074, 119074, US 6816918 B2, US 6816918B2, US-B2-6816918, US6816918 B2, US6816918B2|
|Inventors||Weu-Cheng Tseng, Hsin-Min Yeh|
|Original Assignee||Broadcom Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Non-Patent Citations (1), Referenced by (1), Classifications (24), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method and apparatus of selectively configuring a network device using an Electrically Erasable Programmable Read Only Memory (EEPROM). More specifically, the method and apparatus allows for the use of dynamic configuration settings in the EEPROM interface that increases flexibility, has fewer limitations and is a low cost alternative.
2. Description of Related Art
Many types of network devices are necessary to allow an network to function properly. These network devices are composed of chips, with these chips allowing for the control and monitoring of data through the network device. Chip vendors may pre-set some register default values inside a network device, such as a switch/hub chip, to provide a low cost switch and hub application. That means it is not necessary for system integrators to change the internal register default values to build a workable system. The preconfigured chips allow for the network devices to be setup and to function quickly for a majority of system integrators.
Sometimes, these pre-set register default values might not suitable for some system integrators. Chip vendors should provide some methods so that system integrators can change some register values instead of using default values. Some chip vendors will provide a microprocessor interface (SPI, I2C, or PCI) to allow system integrators to change all write-able register. However, built-in microprocessors on the chip boards increase system costs and may not be needed by many customers.
Another alternative method to allow users to change the default values is to provide an Electrically Eraseable Programmable Read Only Memory (EEPROM) interface. With an EEPROM interface, a system integrator can change some register default values using a very low cost EEPROM. Most of chip vendors have provided an EEPROM interface for a low cost switch and hub application.
FIG. 1 provides as an example of a low cost pre-programmed EEPROM that is used to change some default values of a network switch/hub chip. When the external control signal (RESET) goes to in-active, network switch/hub chip start to change its some register default values via downloading the contents of EEPROM. And then network switch/hub chip start its normal operation after the download phase had been finished.
When the RESET signal goes to in-active, network switch/hub chip start to fetch data from external EEPROM automatically. Most of the network switch/hub chips will fetch data from EEPROM address 00h (the first entry), and fetch the other data in sequence. In order to change some register default values or set chip configuration, the chip vendor will provide a register set (a part of chip register file) which are downloadable from EEPROM. Each entry of EEPROM is pre-defined and will directly map to one (or some) entry of register set inside network switch/hub chip as described in FIG. 2.
However, in this kind of scenario, two major drawbacks may occur. First, different system integrators may want to change different registers. And it is not necessary for system integrators to configure all downloaded register. However, even if system integrators only want to configure some of chip downloadable registers, it is still necessary to fill all the contents of downloadable register set into EEPROM. Secondly, some register default values of network switch/hub chip are change-able via microprocessor interface, but they are not downloadable via EEPROM. In this case, the only way for system integrator to act is to build a microprocessor on his PCB instead of using a very low cost EEPROM.
Thus, there is a need for a mechanism and a process to be used with a network device that allows for a system integrator to make changes to default settings of the network device that is not costly or cumbersome. Additionally, there is also a need such a mechanism to change only certain defaults on a network device without the limitations imposed by the prior art processes and devices.
It is an object of this invention to overcome the drawbacks of the above-described conventional network devices and methods. The present invention provides for a new approach for chip vendors to provide system integrators a dynamic configuration using low cost EEPROM. With this approach, system integrators will have flexibility to change the default values of all configure-able registers inside a network device, such as a switch/hub chip.
According to one aspect of this invention, a method for flexibly configuring default values of a network device through an EEPROM interface. A header is received from an EEPROM through the EEPROM interface and it is determined from the header whether any default value of the network device should be updated. At least one configuration instruction is fetched from the EEPROM when it is determined that the network device should be updated. The at least one configuration instruction is interpreted and a register default value of the default values corresponding to the interpreted at least one configuration instruction is changed.
Additionally, the method can include monitoring a reset signal to determine whether the default values of the network device should be updated. In addition, the method can also determine the number of default values of the network device need to be updated. Also, in determining whether any default value of the network device should be updated includes determining a key value from the header and comparing the key value with a magic number pre-defined inside network device to determine whether any default value of the network device should be updated. The at least one configuration instruction can also be a plurality of configuration instructions and the step of fetching at least one configuration instruction from the EEPROM can be repeated until all of the plurality of configuration instructions have been fetched.
In another aspect of the invention, a network device, having default values, that is flexibly configurable, is also disclosed. The device includes an EEPROM interface, a register file containing the default values for the network device and a configuration instruction interpreter. The EEPROM interface is configured to receive configuration instructions, with each configuration instruction of the configuration instructions being composed of an address index and a corresponding value and wherein the configuration instruction interpreter is configured to interpret the received configuration instructions such that the corresponding values are mapped corresponding default values of the register file.
Also, the network device may have a configuration instruction interpreter that is configured to monitor a reset signal to determine if the default values should be updated. The configuration instruction interpreter may also be configured to receive a header from the EEPROM interface containing a key value from and configured to compare the key value with a pre-defined magic number to determine whether any default value of the default values should be updated. Similarly, the configuration instruction interpreter may be configured to repeatedly fetch configuration instructions from the EEPROM until all of the configuration instructions have been fetched.
These and other objects of the present invention will be described in or be apparent from the following description of the preferred embodiments.
For the present invention to be easily understood and readily practiced, preferred embodiments will now be described, for purposes of illustration and not limitation, in conjunction with the following figures:
FIG. 1 illustrates a network device that interfaces with an EEPROM;
FIG. 2 illustrates the how the contents of the EEPROM map into register file using the chip register map;
FIG. 3 illustrates an embodiment of the present invention where the EEPROM has a dynamic configuration;
FIG. 4 illustrates the operation of the system of the present invention.
At the heart of the present invention is the change in the contents of the EEPROM to a set of configuration instructions instead of configuration values only. Each configuration instruction is composed of address index and its corresponding desired value. An in-direct mapping mechanism is used to map EEPROM contents to their corresponding registers inside network switch/hub chip instead of original direct mapping method. Besides, a header, encapsulated with a specific key value and total number of configuration instructions, should be filled in the first entry of EEPROM content. This header is designed as an identifier during EEPROM download cycle. One embodiment of the present invention is illustrated in FIG. 3.
To achieve this flexible configuration apparatus, network switch/hub chip vendor should build-in a circuit (called Configuration Instruction Interpreter, CII) inside the chip to interpret configuration instruction. When RESET signal goes to in-active, the CII of network switch/hub chip start to fetch header (the first entry) from external EEPROM automatically, then the key is obtained. If the key value is not matched with the magic number pre-defined inside network switch/hub chip, it indicates that it is not necessary to change any chip default value, and download sequence might be skipped. While key is match, CII continuously fetches configuration instruction from EEPROM, and changes the corresponding (defined in address index of configuration instruction) register default value to the desired value by interpreting instruction. This process will be repeated until all instruction download completely. Additionally, since the number of default values needing to be updated is determined from the start, the time needed to perform the updated is less than the equivalent updating performed in the prior art methods and systems.
This process is illustrated in FIG. 4. The process continually checks to see if the RESET signal is set to in-active. Once the RESET signal is in-active, the header of the EEPROM is read. A key is determined and compared with a magic number inside the chip. If there is a match, then instructions are read from the EEPROM and the corresponding register default value is changed. If that instruction just read was the last, then the process ends. If it was not the last, then the next instruction is read from the EEPROM and the default values of the corresponding register are changed.
With this new configuration instruction of EEPROM content, it is not necessary for chip vendor to provide a pre-defined downloadable set. And system integrator could use a very cost EEPROM to change any downloadable register default value. System integrator could decide which registers he wants to change the default values without too much limitation. Additionally, the system integrator also could decide how many registers he wants to change. Such that, less capacity EEPROM could be used due to few register default values changed.
The above-discussed configuration of the invention is, in one embodiment, embodied on a semiconductor substrate, such as silicon, with appropriate semiconductor manufacturing techniques and based upon a circuit layout which would, based upon the embodiments discussed above, be apparent to those skilled in the art. A person of skill in the art with respect to semiconductor design and manufacturing would be able to implement the various modules, interfaces, and components, etc. of the present invention onto a single semiconductor substrate, based upon the architectural description discussed above. It would also be within the scope of the invention to implement the disclosed elements of the invention in discrete electronic components, thereby taking advantage of the functional aspects of the invention without maximizing the advantages through the use of a single semiconductor substrate.
Although the invention has been described based upon these preferred embodiments, it would be apparent to those of skilled in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention, therefore, reference should be made to the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5423015||Oct 20, 1989||Jun 6, 1995||Chung; David S. F.||Memory structure and method for shuffling a stack of data utilizing buffer memory locations|
|US5644784||Mar 3, 1995||Jul 1, 1997||Intel Corporation||Linear list based DMA control structure|
|US5727126||Feb 8, 1995||Mar 10, 1998||Siemens Aktiengesellschaft||Self-programming circuit|
|US5727207 *||Sep 7, 1994||Mar 10, 1998||Adaptec, Inc.||Method and apparatus for automatically loading configuration data on reset into a host adapter integrated circuit|
|US5781796 *||Jun 6, 1995||Jul 14, 1998||Lg Semicon Co., Ltd.||System for automatic configuration of I/O base address without configuration program using readout data on common bus by responding device|
|US5794033||Oct 24, 1995||Aug 11, 1998||International Business Machines Corporation||Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device|
|US5909686||Jun 30, 1997||Jun 1, 1999||Sun Microsystems, Inc.||Hardware-assisted central processing unit access to a forwarding database|
|US6061351||Dec 18, 1997||May 9, 2000||Advanced Micro Devices, Inc.||Multicopy queue structure with searchable cache area|
|US6199192||Mar 6, 1998||Mar 6, 2001||Xilinix, Inc.||Method and apparatus for assigning signal routes via an interconnect-multiplexer in a PLD|
|US6292848 *||Sep 16, 1999||Sep 18, 2001||International Business Machines Corporation||Computing system adapter card for supporting legacy and plug and play configurations|
|US6407960 *||Sep 1, 2000||Jun 18, 2002||Advanced Micro Devices||Arrangement for programming selected device registers during initialization from an external memory|
|WO1999000936A1||Jun 24, 1998||Jan 7, 1999||Sun Microsystems, Inc.||A highly integrated multi-layer switch element architecture|
|1||Ian Page, "Reconfigurable Processor Architectures," Microprocessors and Microsystems, IPC Business Press Ltd., London, Great Britain, vol. 20, No. 3, May 1, 1996, p. 185-196.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20050228917 *||Mar 30, 2004||Oct 13, 2005||Brink Peter C||Novel structure and method for interrupt detection and processing|
|U.S. Classification||710/8, 713/1, 709/220, 710/13, 710/104, 713/2, 713/100, 710/10, 709/221, 709/222|
|International Classification||G06F3/00, H04L29/06, G06F9/445, G06F17/00, H04L12/24, G06F13/14, G06F13/10, G06F15/177|
|Cooperative Classification||H04L69/22, H04L69/12, G06F9/4411|
|European Classification||G06F9/44A4, H04L29/06N, H04L29/06G|
|Apr 10, 2002||AS||Assignment|
Owner name: BROADCOM CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSENG, WEN-CHENG;YEH, HSIN-MIN;REEL/FRAME:012787/0130
Effective date: 20020408
|Apr 25, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Apr 18, 2012||FPAY||Fee payment|
Year of fee payment: 8
|Feb 11, 2016||AS||Assignment|
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:BROADCOM CORPORATION;REEL/FRAME:037806/0001
Effective date: 20160201