|Publication number||US6828987 B2|
|Application number||US 09/923,516|
|Publication date||Dec 7, 2004|
|Filing date||Aug 7, 2001|
|Priority date||Aug 7, 2001|
|Also published as||US20030030653|
|Publication number||09923516, 923516, US 6828987 B2, US 6828987B2, US-B2-6828987, US6828987 B2, US6828987B2|
|Inventors||Philip L. Swan|
|Original Assignee||Ati Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Referenced by (48), Classifications (10), Legal Events (11)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to the processing of video and graphics data, and more particularly to a method and apparatus accessing and using graphics data.
The processing of video and graphics data in multimedia systems is known. Graphics data is generally associated with computer systems, and is used to generate images displayed on computer monitors. For example, graphics data can include commands specifying specific shapes or textures can be processed for display. In a typical graphics system, graphics data is provided in a RGB format. Graphics scalers are used to manipulate the viewed size of a graphics image.
Video data is generally associated with the generation of television images. Protocols for video data include both analog and digital signals. Many standard and proprietary methods for accessing video data are known. The manner in which video data is accessed affects subsequent processing of video data. For example, more efficient processing may be obtained based by accessing data that has been stored in a certain format. However, such gained efficiencies in processing are often accomplished at the cost of increasing the hardware size and design time of the video backend display engine. Once the video backend display engine has accessed the video data, the data is processed and output for display at a display device. For video data to be accessed by a graphics engine has required the graphics engine to include hardware capable of reading the video data, thereby increasing the size of the graphics engine.
Therefore, an apparatus and method capable of efficiently accessing and using video and graphics data would be useful.
FIG. 1 illustrates, in block diagram form, a system in accordance with a specific embodiment of the present invention; and
FIG. 2, illustrates, in block diagram form, portions of the display engine of FIG. 1 in detail.
A method and apparatus is disclosed for using multiple scalers to scale video and graphics data. A video scalar is capable of accessing data formats not accessible by a graphics engine, pipeline, or scaler. The video data can be accessed by the video scaler and subsequently converted to a data format accessible by the graphics engine, pipeline or scaler. The converted video data can be routed to memory. Once stored in memory, the data can be accessed for further processing, such as additional scaling or graphics processing. In addition, the converted video data can be output directly to a processor, such as a graphics processor, for additional processing. Specific embodiments of the present invention are disclosed with reference to FIGS. 1 and 2.
FIG. 1 illustrates a system 100 in accordance with one embodiment of the present invention. System 100 includes a video/graphics data processor 102 and memory 104. The processor 102 is bidirectionally connected to memory 104 to access data. The processor 102 can be an integrated processor, such as a monolithic semiconductor device, or a device having multiple discrete components. The memory 104 can be integrated with the processor 102, a separate memory device, or a combination of integrated and separate memory devices.
The data processor 102, includes a memory controller 110, a backend display engine 120, a 3D/2D GUI (Graphical User Interface) graphics engine 130, an MPEG video decoder 140, a transport stream demultiplexer 150, and a host bus interface 160.
Video data to the system 100 can be received by a VIDEO IN signal, or from a multiplexed data stream such as the transport stream. For example, a multiplexed data stream for carrying multiple programs is received at the transport demultiplexer 150. One example of a multiplexed data stream is an MPEG2 transport stream. The transport stream demultiplexer 150 demultiplexes the components of the transport stream allowing a desired video channel to be isolated for processing. For example, the transport stream demultiplexer 150 can be used to select only those packets associated with a specific program. In this manner, the audio and video stream of a transport stream from a service provider can be selected and provided to the memory controller 110. Subsequently, a video client (not shown) can have the video stream data provided to the display engine 120 for processing.
The VIDEO IN signal received at the backend display engine 120 represents one or more signals from a source external the system 100. For example, the VIDEO IN signal can be from a cable connection, a terrestrial signal, a broadcast signal, a DVD player, or any other video source.
The DISPLAY OUT signals represents one or more signals used by a display device to generate an image. For example, the DISPLAY OUT signal can represent RGB data for a monitor, or a NTSC signal for a conventional television receiver.
The VIDEO OUT signal represents one or more signals intended for further processing by other video or graphics devices. Generally, the VIDEO OUT signal is a representation of video data that is not generated from a display driver portion of the display engine 120, but is capable of displaying images in real time similar to a display device.
In one embodiment, the memory controller 110, at the request of a client, will provide demultiplexed video data received from the transport demultiplexer 150 to the MPEG video decoder 140. The MPEG decoder 140 provides frames of decoded MPEG video data to either the memory controller 110 for storage in memory 104, or to the host bus interface 150 for storage, or use, by a host system (not shown). In an alternate embodiment, the decoded MPEG data from the decoder 140 can be provided directly to the display engine 120 through connections not shown FIG. 1.
In another embodiment, the video data from the MPEG decoder is stored in the memory 104, which is a frame buffer memory. Note the memory 104 can include multiple portions of memory such as a memory device and a memory cache, which may be integrated on to the processing device 102.
The host bus interface 160 is connected to the system bus through which system resources, such as system memory, can be accessed. In one embodiment, graphics data can be sent and received at the graphics engine 130 through the host bus interface 160. In addition, graphics or video data can be sent and received at the memory controller 110.
In accordance with specific embodiments of the invention, display engine 120 can receive video data from memory 104 or from a VIDEO IN signal. In operation, the video data protocols capable of being received by the display engine 120 are a superset of the graphics data protocols capable of being accessed by the graphics engine 130. For example, it may be desirable to access video data in a standard or proprietary format that is not capable of being accessed by a graphics engine. For example, it may be desirable to store video data in planer tiled format. In addition, the video data can be compressed and/or interleaved. In another embodiment, the video data can be stored in a color space that is not accessible by the graphics controller.
One type of graphics data that is accessible by a video decoder and not a graphics decoder includes planar data with sub sampled UV color components as is described in pending patent application having attorney docket number ATI.0001660, filed concurrently with the present application, which is hereby incorporated herein by reference, and in patent application Ser. No. 09/186,034, Patent No. 6,326,984 filed on Nov. 3, 1998 which is hereby incorporated herein by reference, describes another embodiment of graphics data that is accessible by a video decoder.
FIG. 2 illustrates a specific implementation of the display engine 120 of FIG. 1. Video and graphics data is received from one or more clients (not shown) at the video scaler 210 and graphics scaler 220. An output of the video scaler 210 is connected to a color converter 212 by nodes 213. An alpha output of the video scaler 210 is connected to a first input of multiplexer 234. An output of the graphics scaler 220 is connected to a color converter 222 by nodes 223. An alpha output of the graphics scaler 220 is connected to a second input of multiplexer 234. An output of color converter 212 provides a representation of the data received from the video scaler 210 to an alpha mixer 230 by nodes 215. Likewise, an output of color converter 222 provides a representation of the data received from the graphics scaler 220 to the alpha mixer 230 through nodes 225. An output of the multiplexer 234 is connected to a control input of the alpha mixer 230 by node 233. The output of alpha mixer 230 can be provided as an output (VIDEO OUT2), received by display driver 240, or provided to as an input to multiplexer 232. Multiplexer 232 is also connected to nodes 215 from color converter 212. The output of multiplexer 232 is connected to a first video packer 252, and a second video packer 250. The output of packer 252 can be provided as a video out signal labeled VIDEO OUT1. The output of packer 250 is connected to an input to multiplexer 276. A second input to multiplexer 276 is received from the VIDEO IN signal. An output of the multiplexer 276, node 277, is connected to the video capture module 280. The output node 281 connected to the output of video capture module 280 can provide data to a requesting client or to the output labeled VIDEO OUT3.
Operation of the display engine 120 illustrated in FIG. 2 is described with reference to specific flows of data. In one embodiment, a specific data flow is initiated when a client request is received at either scaler 210 or 220. Client requests are generally received from an arbiter in response to requests from one or more specific clients (not shown).
The video scaler 210 of FIG. 2 is capable of receiving any of a set of data formats that intersects data formats capable of being received by an associated 3D engine or pipeline, such as the graphics scaler 220, or the 3D engine 130 of FIG. 1. For example, in one embodiment, the video scaler 210 can receive a video data that is tiled, planar or semiplanar, and/or compressed. For example, the MPEG video decoder of FIG. 1 can store decoded MPEG video data in memory 104 in a tiled format such that the luma component is stored in a first plane, and the chroma components are stored in one or more other planes. Some or all of the planes storing either luma and/or chroma data may be compressed. The video scaler 210 is then capable of accessing the tiled planer and compressed data from memory.
In another implementation, the video scaler 210 can interact with the MPEG decoder to receive MPEG data. This is generally accomplished by providing control signals labeled MPEG CTL, which indicate when an image from the MPEG decoder is arriving and a signal to throttle the rate at which MPEG data is sent. It will be appreciated that other formats of stored video data can be accessed in addition to, or instead of the tiled planer format described.
In yet another implementation, video data from an external source (not shown), such as an analog or digital video decoder, or an external MPEG decoder, can be received directly at a video capture port of the display engine. For example, the signal labeled VIDEO IN is received at the multiplexer 276 and flows through and the video capture portion 280 before being stored in the memory 104. Once stored in the memory 104, the captured input data can be accessed by the video scaler 210 for further processing.
In a display mode of operation, the flow of video data is through video scaler 210, color converter 212, and multiplexer 232 to packer 252. Using this data path, the video data received from a client is scaled and an appropriate color conversion performed as necessary. For example, the video scaler 210 can access video data from a planer-tiled memory and provides scaled video data to the color converter 212 in a format such as a YCbCr color data format. The color converter 212, can leave the data in this color format or convert it to a different color format such as a YPbPr format. The multiplexer 232 can be configured to allow the data from the color converter 212 to be passed to the packer 252. In one implementation, the packer 252 can be a 656 packer that provides VIDEO OUT1 data to a device capable of receiving 656-type data. Note that the VIDEO OUT1 data can be provided to a display device, or to a video capture port of a graphics card. The ability of the described data path to convert the video data received at the video scaler to other formats, allows the video data to be converted to video texture data that can be provided to a graphics engine that itself is not capable of reading the more complicated video formats capable of being read by the video scaler.
In a capture mode, the flow of video data is through video scaler 210, color converter 212, multiplexer 232, packer 250, multiplexer 276 and video capture 280 before being output for storage. Specifically, the video data is received and scaled by the video scaler 210. Next, a color conversion is performed by the color converter 212, as necessary, to adjust the data for a desired protocol. For example, the video scaler 210 can access YUV video data stored in memory in a planer tiled format and provide the scaled result in a different format such as a YCbCr or a RGB color data format. The multiplexer 232 is configured to provide the data from the color converter 212 to packer 250. From packer 250, the data is provided to the multiplexer 276, which is configured to pass data the video capture block 280. The video capture block 280 can convert the video data to yet another format, as necessary, or pass the received data along to its output. From the output of the video capture device, the data can be output at as a signal labeled VIDEO OUT3, or sent to a client, or stored in memory 104.
By storing or capturing the scaled data from the backend display engine 120 at memory 104, the video data can be scaled multiple times by scalers of the display engine 120. This allows for a degree of scaling that surpasses the single pass scaling ability of any one scaler. For example, video data can be scaled multiple times by the video scaler 210 to obtain a greater degree of scaling than is possible by the video scaler 210 with a single pass. Therefore allowing a single video scaler to be implemented that has a smaller size and/or complexity than a more robust scaler capable of greater scaling in a single pass. The repeated scaling of an image is accomplished by repeatedly accessing the stored image from memory 104 until a desired scaling is achieved. Once a desired scaling is achieved, the image may be output.
In addition to being able to scale the video data multiple times using same video scaler, the video data can be converted to a texture format and manipulated using the 2D/3D engine 130. Converting data into a texture format is advantageous because texture formats are generally designed to work efficiently with 2D/3D graphics engine. Therefore, in a specific implementation of the present invention a texture representation of the video data is provided to an output (such as one of the signals VIDEO OUT1, VIDEO OUT2, and VIDEO OUT3) for use by a graphics engine, or to store the texture data in memory 104, so that it may be accessed by an internal or external graphics engine or pipeline.
In another example, texture data stored in a memory 104 can be transferred using the host bus interface 160 the system bus to another device for display or further processing. The host bus interface can act as a bus-mastering device, or receive video data from the memory controller 110 as a client. For example, the packer 250 can convert the video data to an αRGB format. The αRGB data can be stored in memory 104 for further access. In yet another example, the stored video data, now having a graphics readable format, can be accessed by the graphics engine 130 of FIG. 1.
In another display mode, data accessible by the graphics scaler 220 flows through the graphics scaler 220, color converter 222, alpha blender 230, multiplexer 232, and packer 252. Note that the data being accessed can be data that has been previously scaled, such as converted video data being scaled a second time. In this data flow, the graphics data received from a client is scaled at graphics scaler 220, and color converted by color converter 222, as necessary. For example, the graphics data can be received at the graphics scaler 220 as an αRGB data, scaled, and provided to the color converter in αRGB format. The color converter can convert the data into different format, such as YPbPr data, or maintain the data in an αRGB format. The color component of the data from the color converter is provided to the multiplexer 232 and the alpha mixer 230. In addition, the alpha value is provided to the alpha mixer. Data that passes through the alpha mixer 230 can either be passed directly through the mixer 230 (i.e. alpha=1), or can be blended with a second data from the video path described previously. Note, the specific implementation of the display engine of FIG. 2 indicates that alpha information from either the video scaler 210 or the graphics scaler 220 can be selected through the multiplexer 234 for use by the alpha mixer 230. The alpha blended data from the alpha mixer 230 is provided to an input of the multiplexer 232. The alpha blended data can either be displayed or stored by the display engine 120 when the alpha blended data is actively selected.
An alternate data path associated with the display engine of FIG. 2 includes providing the image data from the alpha mixer 230 directly to an output as a digital data labeled VIDEO OUT2. In yet another embodiment, the alpha blended image can be provided to a display driver 240 having one or more of an HDTV encoder 242, and a SDTV encoder 244, and/or others encoders 245, such as a 656 encoder, a DVI encoder, and a scan converter. One or more digital-to-analog converter (DAC) 260 follows the encoders to provide an analog output signal as the DISPLAY OUT signal when necessary. In other embodiments, the DISPLAY OUT signal represents digital data. Where multiple encoders are supported by the display driver 240, a single DAC may be used by more than one of encoders using multiplexing techniques. In another embodiment, multiple DACs may be dedicated to specific encoders.
It will be appreciated that encoders associated with display driver 240 may support a variety of protocols. For example, an HDTV encoder may support one or more HDTV standards proposed by the Society of Motion Picture and Television Engineers (SMPTE) generally referred to as SMPTE 240 M standards, or one or more versions proposed by the International Telecommunications Union (ITU) generally referred to as ITU-R standards, or standards proposed by the Motion Picture Experts Group (MPEG). Other encoders that may be included are encoders that support standard definition television (SDTV). Such SDTV standards may specify digital or analog signals, and include standards proposed by the European Broadcasting Union (EBU), the Electronic Industries Association (EIA), the Institute of Electrical and Electronics Engineers (IEEE), the ITU and the SMPTE. Examples of such standards include versions of NTSC encoding, PAL encoding, and SECAM encoding.
It will be appreciated that the versatility of system described allows for flexible scaling and manipulation of video data. For example, multipass scaling can be accomplished by using one or more of the 3D engine 130, the video scaler 210, and the graphics scaler 220. For example, a specific frame of video data can be scaled multiple times by the video scaler 210 to obtain a desired level of scaling. In another example, a frame of video data can be first scaled by the video scaler 210 and converted to a texture format. Subsequent scaling of the data stored in texture format can be done by either the 3D engine 130 or the video scaler 210. This allows for parallel processing of data.
A specific example of parallel processing of data includes video data being received by the video scaler 210. For example, video data received by the video scaler 210 in a video format not directly accessible by the 2D/3D engine 130 or the graphics scaler 220, such as planer YUV data. The video data is then scaled and color converted as necessary to provide a desired color format to the multiplexer 232. For purposes of example, it is assumed the data stored by the video scalar as an αRGB color format that is accessible by the other scalar(s) and graphics engines. Note, degradation of the video data due to data type conversion is reduced by maintaining the video data in a common format. The αRGB data can be packed by the packer 250 before being passed through the multiplexer 276 and video capture portion 280 for storage in the memory 104. Once stored in memory 104, a client can make a request to the 3D engine 130 of FIG. 1 to further scale or process the saved video data. The 3D engine 130 can process the data in parallel with a next video data being processed by the video scaler 210 as just described. In addition, a client can request that graphics scaler 220 further process data scaled by the video scaler 210 and/or the 3D graphics engine 130. The graphics scaler 220 can work in parallel with the video scaler and/or the 3D graphics engine 130. The data from the color converter 222 can be alpha mixed with the data being processed by the video scaler 210, or the data from the color converter 222 associated with the graphics scaler can be provided to the display driver 240 for display. For example, the stored video data that has been scaled and converted through the video scaler 210 can be received at the graphics scaler 220, passed to color converted converter 222 and the alpha mixer 230, with or without alpha mixing, and provided to the video driver 240. In this manner, a single video input stream can be scaled multiple times and provided as the DISPLAY OUT signal without having to stall any of the scalers. This allows for systems that are capable of scaling data by a greater amount than any one scaler is individually capable of achieving by itself in a single path.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, one of ordinary skill in the art will appreciate that the present application discloses additional data flows other than those specifically discussed. Likewise, various conversions between video formats besides those specifically listed are anticipated. In addition, the actual partitioning of the specific system can vary. For example, the DAC, or DACs, associated with the display driver 240 illustrated herein, may be incorporated onto a common semiconductor substrate with the encoders of the display driver 240, or may be discreet components separate from the encoders. In addition, it will be appreciated that not all components of the display engine 120 embodiment need be implemented, for example, only one of the packers 250 and 252 need be implemented. Likewise, additional components to the display engine 120 would be anticipated, such as additional processing modules between the VIDEO IN signal and the multiplexer 276. For example, an analog-to-digital converter or other decoder may be implemented before the multiplexer 276 Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5664162||Nov 3, 1994||Sep 2, 1997||Cirrus Logic, Inc.||Graphics accelerator with dual memory controllers|
|US5793693||Nov 4, 1996||Aug 11, 1998||Compaq Computer Corporation||Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation|
|US5844541 *||Feb 17, 1995||Dec 1, 1998||Intel Corporation||Generating a full-resolution image from sub-sampled image signals|
|US5854620||Dec 19, 1995||Dec 29, 1998||Cirrus Logic, Inc.||Method and apparatus for converting monochrome pixel data to color pixel data|
|US5878240||Jan 30, 1997||Mar 2, 1999||Lucent Technologies, Inc.||System and method for providing high speed memory access in a multiprocessor, multimemory environment|
|US5912676||Jun 14, 1996||Jun 15, 1999||Lsi Logic Corporation||MPEG decoder frame memory interface which is reconfigurable for different frame store architectures|
|US5937204||May 30, 1997||Aug 10, 1999||Helwett-Packard, Co.||Dual-pipeline architecture for enhancing the performance of graphics memory|
|US5938756||Apr 19, 1996||Aug 17, 1999||Sun Microsystems, Inc.||Central processing unit with integrated graphics functions|
|US5949428||Jun 27, 1996||Sep 7, 1999||Microsoft Corporation||Method and apparatus for resolving pixel data in a graphics rendering system|
|US5973696||Aug 8, 1997||Oct 26, 1999||Agranat Systems, Inc.||Embedded web server|
|US6064407||Apr 30, 1998||May 16, 2000||Ati Technologies, Inc.||Method and apparatus for tiling a block of image data|
|US6088355 *||Oct 11, 1996||Jul 11, 2000||C-Cube Microsystems, Inc.||Processing system with pointer-based ATM segmentation and reassembly|
|US6189064||Nov 9, 1999||Feb 13, 2001||Broadcom Corporation||Graphics display system with unified memory architecture|
|US6204863||Aug 6, 1998||Mar 20, 2001||Cirrus Logic, Inc.||Method for dynamic XY tiled texture caching|
|US6252612||Dec 30, 1997||Jun 26, 2001||Micron Electronics, Inc.||Accelerated graphics port for multiple memory controller computer system|
|US6297832||Jan 4, 1999||Oct 2, 2001||Ati International Srl||Method and apparatus for memory access scheduling in a video graphics system|
|US6326984 *||Nov 3, 1998||Dec 4, 2001||Ati International Srl||Method and apparatus for storing and displaying video image data in a video graphics system|
|US6330036||Aug 12, 1998||Dec 11, 2001||Mitsubishi Denki Kabushiki Kaisha||Digital video receiving apparatus|
|US6493036 *||Nov 17, 1999||Dec 10, 2002||Teralogic, Inc.||System and method for scaling real time video|
|US6538656 *||Aug 18, 2000||Mar 25, 2003||Broadcom Corporation||Video and graphics system with a data transport processor|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7511714 *||Nov 10, 2003||Mar 31, 2009||Nvidia Corporation||Video format conversion using 3D graphics pipeline of a GPU|
|US7535478 *||Dec 24, 2003||May 19, 2009||Intel Corporation||Method and apparatus to communicate graphics overlay information to display modules|
|US7728851 *||Dec 30, 2005||Jun 1, 2010||Kabushiki Kaisha Toshiba||Reproducing apparatus capable of reproducing picture data|
|US7760209||Dec 17, 2007||Jul 20, 2010||Nvidia Corporation||Video format conversion using 3D graphics pipeline of a GPU|
|US7777748||Sep 18, 2007||Aug 17, 2010||Lucid Information Technology, Ltd.||PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications|
|US7796129||Oct 23, 2007||Sep 14, 2010||Lucid Information Technology, Ltd.||Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus|
|US7796130||Oct 23, 2007||Sep 14, 2010||Lucid Information Technology, Ltd.||PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation|
|US7800610||Oct 23, 2007||Sep 21, 2010||Lucid Information Technology, Ltd.||PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application|
|US7800611||Oct 23, 2007||Sep 21, 2010||Lucid Information Technology, Ltd.||Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus|
|US7800619||Oct 23, 2007||Sep 21, 2010||Lucid Information Technology, Ltd.||Method of providing a PC-based computing system with parallel graphics processing capabilities|
|US7808499||Nov 19, 2004||Oct 5, 2010||Lucid Information Technology, Ltd.||PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router|
|US7808504||Oct 26, 2007||Oct 5, 2010||Lucid Information Technology, Ltd.||PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications|
|US7812844||Jan 25, 2006||Oct 12, 2010||Lucid Information Technology, Ltd.||PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application|
|US7812845||Oct 26, 2007||Oct 12, 2010||Lucid Information Technology, Ltd.||PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application|
|US7812846||Oct 26, 2007||Oct 12, 2010||Lucid Information Technology, Ltd||PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation|
|US7834880||Mar 22, 2006||Nov 16, 2010||Lucid Information Technology, Ltd.||Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction|
|US7843457||Oct 26, 2007||Nov 30, 2010||Lucid Information Technology, Ltd.||PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application|
|US7936360||Dec 30, 2005||May 3, 2011||Kabushiki Kaisha Toshiba||Reproducing apparatus capable of reproducing picture data|
|US7940274||Sep 25, 2007||May 10, 2011||Lucid Information Technology, Ltd||Computing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuit|
|US7944450||Sep 26, 2007||May 17, 2011||Lucid Information Technology, Ltd.||Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architecture|
|US7961194||Aug 30, 2007||Jun 14, 2011||Lucid Information Technology, Ltd.||Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system|
|US7973806||Apr 12, 2010||Jul 5, 2011||Kabushiki Kaisha Toshiba||Reproducing apparatus capable of reproducing picture data|
|US8085273||Jan 18, 2007||Dec 27, 2011||Lucid Information Technology, Ltd||Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control|
|US8125487||Sep 26, 2007||Feb 28, 2012||Lucid Information Technology, Ltd||Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board|
|US8134563||Oct 30, 2007||Mar 13, 2012||Lucid Information Technology, Ltd||Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control|
|US8284207||Aug 29, 2008||Oct 9, 2012||Lucid Information Technology, Ltd.||Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations|
|US8385726||Jan 25, 2007||Feb 26, 2013||Kabushiki Kaisha Toshiba||Playback apparatus and playback method using the playback apparatus|
|US8497865||Dec 31, 2006||Jul 30, 2013||Lucid Information Technology, Ltd.||Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS|
|US8497881 *||Feb 26, 2010||Jul 30, 2013||Samsung Electronics Co., Ltd.||Image processors, electronic device including the same, and image processing methods|
|US8629877||Oct 23, 2007||Jan 14, 2014||Lucid Information Technology, Ltd.||Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system|
|US8754894||Nov 8, 2010||Jun 17, 2014||Lucidlogix Software Solutions, Ltd.||Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications|
|US8754897||Nov 15, 2010||Jun 17, 2014||Lucidlogix Software Solutions, Ltd.||Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem|
|US8830300||Mar 5, 2011||Sep 9, 2014||Dolby Laboratories Licensing Corporation||Multiscalar stereo video format conversion|
|US9218792||Dec 11, 2008||Dec 22, 2015||Nvidia Corporation||Variable scaling of image data for aspect ratio conversion|
|US9405586||Jan 13, 2014||Aug 2, 2016||Lucidlogix Technologies, Ltd.||Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization|
|US9584592||Jun 16, 2014||Feb 28, 2017||Lucidlogix Technologies Ltd.||Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications|
|US9659340||Jun 16, 2014||May 23, 2017||Lucidlogix Technologies Ltd||Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem|
|US20050140695 *||Dec 24, 2003||Jun 30, 2005||Dunton Randy R.||Method and apparatus to communicate graphics overlay information|
|US20060164438 *||Dec 30, 2005||Jul 27, 2006||Shinji Kuno||Reproducing apparatus capable of reproducing picture data|
|US20060164938 *||Dec 30, 2005||Jul 27, 2006||Shinji Kuno||Reproducing apparatus capable of reproducing picture data|
|US20060176312 *||Dec 30, 2005||Aug 10, 2006||Shinji Kuno||Reproducing apparatus capable of reproducing picture data|
|US20070223877 *||Jan 25, 2007||Sep 27, 2007||Shinji Kuno||Playback apparatus and playback method using the playback apparatus|
|US20080122860 *||Dec 17, 2007||May 29, 2008||Nvidia Corporation||Video format conversion using 3D graphics pipeline of a GPU|
|US20080204468 *||Feb 28, 2007||Aug 28, 2008||Wenlong Li||Graphics processor pipelined reduction operations|
|US20090027383 *||Mar 14, 2008||Jan 29, 2009||Lucid Information Technology, Ltd.||Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition|
|US20100205648 *||Apr 21, 2010||Aug 12, 2010||Abbas Sasan Saadat||Secure Integrated Media Center|
|US20100220105 *||Feb 26, 2010||Sep 2, 2010||Jong Ho Roh||Image Processors, Electronic Device Including the Same, and Image Processing Methods|
|US20110221864 *||Mar 5, 2011||Sep 15, 2011||Dolby Laboratories Licensing Corporation||Multiscalar Stereo Video Format Conversion|
|U.S. Classification||345/660, 725/40, 345/629, 345/619, 345/636, 348/553, 348/563|
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