US 6829757 B1 Abstract Some embodiments of the invention provide a method of generating a multi-layer topological path for a layout that has multiple layers. This method specifies a set of path expansions from a first topological item to a second topological item on a first layer of the layout. For a potential via expansion from the second topological item to a third topological item on a second layer of the layout, the method (1) identifies a first region on the first layer for the second topological item, (2) identifies a second region on the second layer the third topological item, (3) determines whether an intersection of the first and second regions is sufficiently large to contain a via, and (4) if the intersection is sufficiently large, adds the potential via expansion to the specified set of path expansions.
Claims(24) 1. For a layout that has multiple layers, a method of generating a multi-layer topological path comprising:
a) specifying a set of path expansions from a first topological item to a second topological item, wherein the second topological item is on a first layer of the layout; and
b) for a potential via expansion from the second topological item to a third topological item on a second layer of the layout,
identifying a first region on the first layer for the second topological item;
identifying a second region on the second layer for the third topological item;
determining whether an intersection of the first and second regions is larger than a threshold area; and
if the intersection is larger than the threshold area, adding the potential via expansion to the specified set of path expansions.
2. The method of
3. The method of
before specifying the set of path expansions, decomposing the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;
wherein at least one of the second and third topological items represents an interior space of a face.
4. The method of
5. The method of
6. The method of
specifying a plurality of nodes along boundaries of the routable elements; and
defining edges between the nodes.
7. The method of
8. A computer program stored on a computer readable medium, wherein the computer program generates, for a layout that has multiple layers, a multi-layer topological path, the computer program comprising:
a) a first set of instructions for specifying a set of path expansions from a first topological item to a second topological item, wherein the second topological item is on a first layer of the layout;
b) for a potential via expansion from the second topological item to a third topological item on a second layer of the layout,
a second set of instructions for identifying a first region on the first layer for the second topological item;
a third set of instructions for identifying a second region on the second layer for the third topological item;
a fourth set of instructions for determining whether an intersection of the first and second regions is larger than a threshold area; and
a fifth set of instructions for adding the potential via expansion to the specified set of path expansions, when the intersection is larger than the threshold area.
9. The computer program of
10. The computer program of
a sixth set of instruction for decomposing, before specifying the set of path expansions, the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;
wherein at least one of the second and third topological items represents an interior space of a face.
11. The computer program of
12. The computer program of
13. The computer program of
a seventh set of instructions for specifying a plurality of nodes along boundaries of the routable elements; and
an eight set of instructions for defining edges between the nodes.
14. The computer program of
15. For an integrated circuit layout that has multiple layers, a method of generating a multi-layer topological path comprising:
a) identifying a set of path expansions from a first topological item to a second topological item on a first layer of the layout;
b) identifying a first region on the first layer for the second topological item, and a second region on the second layer for a third topological item that is reachable from the second topological item through a via expansion;
c) determining whether an intersection of the first and second regions is larger than a threshold area; and
d) adding the potential via expansion to the specified set of path expansions when the intersection is larger than the threshold area.
16. The method of
17. The method of
before specifying the set of path expansions, decomposing the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;
wherein at least one of the second and third topological items represents an interior space of a face.
18. The method of
19. The method of
specifying a plurality of nodes along boundaries of the routable elements; and
defining edges between the nodes.
20. A computer program stored on a computer readable medium, wherein the computer program generates, for an integrated circuit layout that has multiple layers, a multi-layer topological path, the computer program comprising sets of instructions for:
a) identifying a set of path expansions from a first topological item to a second topological item on a first layer of the layout;
b) identifying a first region on the first layer for the second topological item, and a second region on the second layer for a third topological item that is reachable from the second topological item through a via expansion;
c) determining whether an intersection of the first and second regions is larger than a threshold area; and
d) adding the potential via expansion to the specified set of path expansions when the intersection is larger than the threshold area.
21. The computer program of
22. The computer program of
23. The computer program of
24. The computer program of
specifying a plurality of nodes along boundaries of the routable elements; and
defining edges between the nodes.
Description This patent application claims the benefit of the earlier-field U.S. Provisional Patent Application entitled “Interconnect Method, Apparatus, and Architecture for Integrated Circuits and Integrated-Circuit Layouts”, having Ser. No. 60/295,735, and filed Jun. 2, 2001; and U.S. Provisional Patent Application entitled “Interconnect Method, Apparatus, and Architecture for Integrated Circuits and Integrated-Circuit Layouts”, having Ser. No. 60/298,146, and filed Jun. 12, 2001; and U.S. Provisional Patent Application entitled “Method and Apparatus for Routing a Set of Nets”, having Ser. No. 60/351,459, and filed Jan. 22, 2002. The invention is directed towards method and apparatus for generating multi-layer routes. An integrated circuit (“IC”) is a semiconductor device that includes many electronic components (e.g., transistors, resistors, diodes, etc.). These components are often interconnected to form multiple circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. The electronic and circuit components of IC's are jointly referred to below as “components.” An IC also includes multiple layers of wiring (“wiring layers”) that interconnect its electronic and circuit components. For instance, many IC's are currently fabricated with metal or polysilicon wiring layers (collectively referred to below as “metal layers”) that interconnect its electronic and circuit components. One common fabrication model uses five metal layers. In theory, the wiring on the metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal layer typically has a preferred wiring direction. IC designs often penalize non-preferred direction wiring on a layer. Many IC's use the Manhattan wiring model, which specifies layers of preferred-direction horizontal and vertical wiring. In this wiring model, the layers of preferred-direction wiring typically alternate. Also, in this wiring model, the majority of the wires can only make 90° turns. However, occasional diagonal jogs are sometimes allowed on the preferred horizontal and vertical layers. Design engineers design IC's by transforming circuit description of the IC's into geometric descriptions, called layouts. To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. EDA applications create layouts by using geometric shapes that represent different materials and devices on IC's. For instance, EDA tools commonly use rectangular lines to represent the wire segments that interconnect the IC components. These tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes. Also, in this document, the phrase “circuit module” refers to the geometric representation of an electronic or circuit IC component by an EDA application. EDA applications typically illustrate circuit modules with pins on their sides. These pins connect to the interconnect lines. A net is typically defined as a collection of pins that need to be electrically connected. A list of all or some of the nets in a layout is referred to as a netlist. In other words, a netlist specifies a group of nets, which, in turn, specify the required interconnections between a set of pins. The IC design process entails various operations. Some of the physical-design operations that EDA applications commonly perform to obtain the IC layouts are: (1) circuit partitioning, which partitions a circuit if the circuit is too large for a single chip; (2) floor planning, which finds the alignment and relative orientation of the circuit modules; (3) placement, which determines more precisely the positions of the circuit modules; (4) routing, which completes the interconnects between the circuit modules; and (5) verification, which checks the layout to ensure that it meets design and functional requirements. Routing is a key operation in the physical design cycle. It is generally divided into two phases: global routing and detail routing. For each net, global routing generates a “loose” route for the interconnect lines that are to connect the pins of the net. After global routes have been created, the detail routing creates specific individual routing paths for each net. While some commercial routers today might allow an occasional diagonal jog, these routers do not typically explore diagonal routing paths consistently when they are specifying the routing geometries of the interconnect lines. This, in turn, increases the total wirelength (i.e., total length of interconnect lines) needed to connect the nets in the layout. In addition, routers today are mostly gridded. The manufacturing processes for designing IC's specify a manufacturing grid that specifies manufacturable resolution. The boundary of all circuit elements is defined by the straight-line connections between adjacent manufacturing points. Gridded routers typically define arbitary grids of intersecting lines to specify the available locations for routing interconnects. These arbitrary grids are often much coarser than the manufacturing grids (e.g., they are typically line-to-via spacing). Consequently, they arbitrarily limit the locations of interconnect lines and impose arbitrary spacing between the items in the layout. These arbitrary limits increase the size and efficiency of a design. The routing grids also discourage using arbitrary widths or spacing for interconnect lines. Furthermore, existing routers primarily utilize preferred-direction wiring to route their designs. Many IC layouts are designed by penalizing the use of interconnect lines in each particular layer when the interconnect lines are not in the preferred wiring direction of the particular layer. Such preferred direction wiring leads to IC layouts and IC's that have most of their interconnect lines and wiring on each of their metal layers traverse in the same direction. Such IC layouts and IC's do not efficiently use the available spacing on the interconnect layers, and this adversely affects the size and efficiency of the layouts and the IC's. Some embodiments of the invention provide a method of generating a multi-layer topological path for a layout that has multiple layers. This method specifies a set of path expansions from a first topological item to a second topological item on a first layer of the layout. For a potential via expansion from the second topological item to a third topological item on a second layer of the layout, the method (1) identifies a first region of the first layer for the second topological item, (2) identifies a second region on the second layer for the third topological item, (3) determines whether an intersection of the first and second regions is sufficiently large to contain a via, and (4) if the intersection is sufficiently large, adds the potential via expansion to the specified set of path expansions. The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. FIG. 1 illustrates a wiring model of some embodiments of the invention. FIG. 2 presents a conceptual illustration of a detail-routing process used by some embodiments of the invention. FIG. 3 illustrates one manner of defining sub-regions for detail routing. FIGS. 4 and 5 illustrate two layers of 16 Gcells that have been combined to produce a sub-region. FIG. 6 illustrates the data structure that the detail routing process uses to represent a sub-region in some embodiments of the invention. FIG. 7 illustrates the modified data structure that the detail routing process uses to represent a subregion in some embodiments of the invention. FIG. 8 illustrates a data structure that defines a face. FIG. 9 illustrates a data structure that defines an edge. FIGS. 10-12 illustrate the data structure of nodes, edge items, and face items. FIG. 11 illustrates the data structure for an edge item. FIG. 12 illustrates the data structure for a face item. FIGS. 13 and 14 illustrate one example of topological routes. FIG. 15 illustrates a process that provides the overall flow of a topological engine in some embodiments of the invention. FIG. 16 illustrates a triangulation process that is used in some embodiment of the invention. FIG. 17 illustrates the layout of FIG. 4 after nodes have been defined at each sub-region corner, at each port or obstacle geometry point, and within each port geometry. FIG. 18 illustrates a triangulation technique. FIGS. 19 and 20 illustrate why maximizing the minimal angles of the decomposing triangles improves the likelihood that the generated topological routes can be geometrized. FIGS. 21 and 22 illustrate one manner for performing an edge-flipping operation. FIG. 23 illustrate one manner of constraining geometry and sub-region boundaries in the triangulated graph. FIG. 24 illustrates an example of how the layout of FIG. 4 might look after triangulation. FIGS. 25 and 26 illustrate a process that the triangulation process can call each time it wants to identify the capacity of each edge in the triangulated sub-region. FIG. 27 pictorially illustrates an example of a solving engine's IDA*-searching operation for a set of three nets. FIG. 28 illustrates a more detailed process used by the solving engine in some embodiments of the invention. FIG. 29 illustrates a process that the solving engine uses to generate topological routes for a net. FIGS. 30A and 30B illustrate a process for inserting Steiner-tree face items in face. FIG. 31 illustrates a process for generating paths between one or more sources and one or more targets for a selected pin-pair. FIGS. 32-36 illustrate the possible expansions from edge items, nodes, and face items. FIG. 37 illustrates three types of legality checking. FIGS. 38A and 38B illustrate how to compute the flow of an edge after a potential expansion. FIGS. 39A and 39B illustrate processes for making via checks. FIG. 40 illustrates a process for computing the cheapest-route cost for a net. FIG. 41 conceptually illustrates a process performed by this routing engine in some embodiments of the invention. FIG. 42 illustrates eight such sectors that are defined around the eight routing directions of the octilinear wiring model illustrated in FIG. FIG. 43 illustrates a process for measuring the sector congestion about a via. FIG. 44 illustrates four sets of adjacent Manhattan sectors, while FIG. 45 illustrates four sets of adjacent 45° sectors. FIG. 46 illustrates a unique-congestion graph edge that is between two nodes. FIG. 47 illustrate a simple example of a layout portion that has two obstacles about which two topological routes for two nets are defined by the topological router. FIGS. 48A-48D illustrate four sets of path defining edges for this example. FIGS. 49A and 49B illustrate two octagons that represent the octilinear wiring model of FIG. FIG. 49C identifies the eight possible directions that can be constrained by the four constraining angles, ±22.5° and ±67.5°, for the octilinear wiring model. FIG. 50 illustrates a merged path for the examples illustrated in FIGS. 48A-48D. FIG. 51 illustrates the geometric projection of a segment onto a horizontal direction. FIG. 52 illustrates a net-width view of the route illustrated in FIG. FIG. 53 presents a geometric-routing process performed by the geometric engine of some embodiments of the invention. FIGS. 54 and 55 provide two examples for identifying the spacing and width requirements on constraining directions. FIG. 56 illustrates an example of identifying a shortest partial path after constraining segments of the intersected path-defining edges. FIG. 57 provides an example of a portion of a merged route. FIG. 58 illustrates multiple via cuts and contact pairs that define a via between a narrow path on one layer and a wider path on another layer. FIGS. 59-62 illustrate various shapes of vias that are used in some embodiments of the invention, and FIGS. 63-65 illustrate various shapes of interconnect-lines that are used in some embodiments of the invention. FIG. 66 illustrates a half-octagon interconnect lines that matches well with different via shapes that can be used with the octagonal wiring model. FIG. 67 illustrates a half-hexagon interconnect lines that matches well with different via shapes that can be used with the hexagonal wiring model. FIG. 68 illustrates an example of an octagonal Steiner node formed by half-octagon lines, while FIG. 69 illustrates an example of a hexagonal Steiner node formed by half-hexagonal lines. FIGS. 70-82 present several examples that illustrate the via-checking process of FIG. FIG. 83 illustrates a computer system used in some embodiments. In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. Some embodiments of the invention utilize non-preferred-direction (“NPD”) wiring models for designing IC layouts. A NPD wiring model does not specify a single preferred routing direction for at least one of its interconnect layers. (In the discussion below, the terms interconnect layer is interchangeably used with the terms metal or wiring layer.) A NPD wiring model has at least one NPD interconnect layer that has more than one preferred routing direction. In other words, each NPD interconnect layer has at least two routing directions that are equally preferable with respect to one another, and that are as preferable or more preferable than the other routing directions on that layer. A router that uses a NPD wiring model does not penalize wiring in the two or more preferred directions of a NPD interconnect layer of its layout. In other words, such a router does not impose arbitrarily different costs for routing in the two or more preferred directions of a NPD interconnect layer of its layout. For instance, when a NPD interconnect layer allows horizontal and +45° direction wiring, some embodiments cost the interconnect lines in the horizontal and +45° directions based solely on their lengths and not on any other arbitrary cost designed to dissuade using one direction (e.g., the horizontal direction) over the other. By using NPD wiring models, some embodiments generated IC layouts with one or more metal layers that do not have a single preferred wiring direction. FIG. 1 illustrates a wiring model As used in this document, an interconnect line is “diagonal” if it forms an angle other than zero or ninety degrees with respect to the layout boundary. On the other hand, an interconnect line is “horizontal” or “vertical” if it forms an angle of 0° or 90° with respect to one of the sides of the layout. In the wiring model of FIG. 1, (1) the horizontal interconnect lines are parallel (i.e., are at 0°) to the x-axis, which is defined to be parallel to the width of the layout, (2) the vertical interconnect lines are parallel to the y-axis, which is defined to be parallel to the height and perpendicular (i.e., are at 90°) to the width of the layout, (3) the +45° diagonal interconnect lines are at +45° with respect to the width of the IC layout, and (4) the −45° diagonal interconnect lines are at −45° with respect to the width of the IC layout. Other embodiments of the invention use different NPD wiring models. For instance, some embodiments of the invention's NPD wiring model only include diagonal interconnect lines, other embodiments only use horizontal and vertical interconnect lines, and yet other embodiments use diagonal interconnect lines with either horizontal or vertical interconnect lines but not both. Also, some embodiments use non-45° diagonal wiring. For example, some embodiments use horizontal, vertical and ±120° diagonal interconnect lines. In addition, some embodiments have more than five layers, while other embodiments have less. Some embodiments also assign a preferred direction for some of the layers, while allowing other layers not to have a preferred wiring direction. For instance, some embodiments have preferred direction Manhattan wiring for the first three layers (e.g., horizontal preferred direction wiring for the first layer, vertical preferred direction wiring for the second layer, and horizontal preferred direction wiring for the third layer), and NPD wiring for the fourth and fifth layers. By generating IC layouts with one or more NPD interconnect layers, some embodiments fabricate IC's that have NPD wiring for one or more of the metal layers. For instance, the wiring model In some embodiments, the IC has at least one wiring layer that does not have a wiring direction with more that 50% of the wiring on that layer. In other embodiments, the IC has at least one wiring layer that does not have a wiring direction with more than 70% of the wiring on that layer, one such embodiment might only include horizontal and vertical direction wiring on such a wiring layer. A gridless routing process is described below for generating gridless layouts. This routing process is gridless as it does not require the interconnect lines to be positioned with respect to any grid that is coarser than the manufacturing grid. In other words, the only grid that the interconnect lines have to be aligned with is the manufacturing grid. The gridless routing process generates gridless layouts that can be used to fabricate IC's that have their metal lines aligned with the manufacturing grid instead of coarser non-manufacturing grids. The gridless routing process described below generates gridless NPD octilinear layouts. However, one of ordinary skill will realize that this routing process can be used to generate other gridless layouts. For instance, some embodiments generate gridded NPD layouts. Some embodiments generate gridless NPD layouts by using a detail routing technique that does not specify a preferred wiring direction for any of its interconnect layers. The detail-routing embodiments described below use the NPD wiring model In the embodiments described below, the detail routing is performed after a global-routing stage, which (1) partitions the routing region into global-routing cells (“Gcells”), and (2) defines, for each net, global-routing paths that connect the Gcells containing the net's pins. One hierarchical global routing approach recursively divides the routing region into smaller sub-regions, and defines routing paths at each hierarchical level, until reaching the lowest-recursive level's sub-regions, which are the Gcells. Another global-routing approach flatly divides the routing region into numerous Gcells, and then defines the routing paths between the Gcells. Under either approach, the global router can use either a NPD wiring model or a preferred-direction wiring model. FIG. 2 presents a conceptual illustration of a detail-routing process In the embodiments described below, a net has two or more pins, a pin can have one or more ports, and each port can have one or more geometries. In these embodiments, a net's routable elements are the port geometries, and a net is typically routed along one port of each of its pins. One of ordinary skill will realize, however, that other embodiments may define the routable elements of the nets differently. A topological route is a route that is defined in terms of its relation to other layout items, such as pins, obstacles, boundaries, and/or other topological routes of other nets. As such, a topological route provides a general plan for how to route a net, without providing a specific geometric path to do so. One topological route represents a set of diffeomorphic geometric routes (i.e., a set of geometric routes that can be morphed into one another through a continuous sequence of perturbations without changing the route's path relative to any other pin, path or obstacle). A geometric route is one explicit realization of a topological route. A geometric route is defined in terms of exact coordinates that define the route as it travels through the interconnect layers. Several manners for identifying topological routes for each net within the selected sub region will be described below. After At At As mentioned above, the detail-routing process Different embodiments select the Gcells differently. Some embodiments select contiguous non-overlapping groups of Gcells for each iteration of process Other embodiments select the sub-region to detail route at After selecting several Gcells for detail routing, the detail routing process For example, FIGS. 4 and 5 illustrate two layers of 16 Gcells that have been combined to produce a sub-region The detail routing process This data structure also includes the bounding box of the subregion. In addition, it includes an array of layer properties. This array specifies various design rules for each layer. For instance, it specifies for each layer the minimum wire size, the minimum spacing, and the minimum via size. This array also specifies the minimum cost per unit length for an interconnect on each layer. For instance, the cost per unit length might be expressed in terms of resistance per distance, which might be less for the higher layers as the wire width typically increases for the higher layers. Some embodiments store additional layer information in other data structures. For instance, some embodiments (1) allow the net widths to be different on different layers, and/or (2) allow the spacing between nets or between nets and unrelated geometries to be different on different layers. Such information is stored in a look-up table in some embodiments. The data structure also includes a netlist that specifies the nets in the sub-region. Each net specifies one or more pins, each pin refers to one or more ports, and each port refers to one or more geometries. A geometry that is not referred to by a port (i.e., that is not part of a pin) is an obstacle. One manner for generating topological routes will now be described. In some embodiments, these routes are generated by a topological routing engine that (1) receives the sub-region data structure defined at This engine is a multi-layer topological router that for each net in the sub-region, generates a topological route (i.e., a topological representation of a route) that connect the net's routable elements on one or more layers. In other words, this router selects a net and for the selected net, defines a topological route that connects the selected net's routable elements on one or more interconnect layers, before selecting another net for routing. To facilitate its multi-layer approach, this topological router uses vias that are defined topologically, as further described below. These vias are referred to below as topological vias. The topological engine also routes sets of nets together. Specifically, this engine selects a set of nets in the sub-region, and identifies the best possible combination of topological routes for the set's nets. As further described below, the topological engine used in some embodiments is an IDA* solving engine that deterministically traverses through the solution space to identify the best possible combination of topological routes for a set of nets. In addition, while routing a set of nets, the topological engine considers the routing cost of nets that have not yet been selected. This topological engine also employs NPD routing as it costs routing in all planar directions on a layer the same. In other words, it does not penalize routing in any planar direction on a layer. In addition, this engine costs wires and vias proportionately to their metric cost that they introduce in the design. The metric cost can be based on a number of properties of wires and vias. These properties include resistance, delay, manufacturing yield, etc. The topological engine also allows nets to have different widths on different layers. It also can impose different spacing constraints between each pair of net. The spacing constraint for a pair of nets can also be different on different layers. This topological engine can also base its topological routes on different wiring models, such as a wiring model that employs only Manhattan lines, one that uses Manhattan and ±45° lines, one that uses Manhattan and ±120° lines, etc. 1. Overview In the embodiments described below, the topological engine (1) initially decomposes each layer of the received sub-region to obtain a decomposed graph that has several nodes, edges, and faces, and then (2) uses the nodes, edges, and faces of the generated graphs to define topological routes in the received sub-region. a. Overview of the Decomposition Operation. As further described below, the decomposition operation is a triangulation operation in some embodiments. In other words, the faces resulting from the decomposition operation are triangles and therefore have three edges. Each edge is defined to be between two nodes. In the embodiments described below, the nodes of each layer's triangulated graph are defined at the obstacle-geometry vertices, pin-geometry vertices, and the four corners of the sub-region on each layer. At the end of the triangulation operation, the topological engine adds, to the sub-region definition, a graph data structure for each layer of the sub-region. This addition is pictorially illustrated in FIG. FIG. 8 illustrates a data structure FIG. 9 illustrates a data structure The edge data structure also specifies the capacity of the edge. It further specifies the wire flow across each edge. This flow equals the width of the nets crossing the edge plus the spacing between the crossing nets and between the nets and the edge nodes. This data structure also has a Boolean flag to indicate whether the edge is a constrained edge. This flag is used during the triangulation, as described below. In addition, the edge data structure b. Embedded Topological Routes After triangulation, the topological engine embeds multi-layer topological routes in the triangulated graphs. It uses the nodes, edges, and faces of these graphs to define the topological direction of these routes. Specifically, the topological engine defines a topological route as a linked list of topological items that represent various points along the route. These topological items include nodes, edge items, and face items. Nodes and face items can serve as via locations, Steiner points, or both. Nodes can also serve as end points of a topological route. FIGS. 10-12 illustrate the data structure of nodes, edge items, and face items. As shown in FIG. 10, a node data structure In the embodiments described below, a node can serve as the location for a via. Accordingly, the node data structure The node data structure further includes a list of edges connected to the node. For each edge, it includes an edge reference to the next or previous topological item (i.e., node or edge item) on the edge. It also has a reference to the geometry of the node, and a vertex number that identifies the point in the geometry corresponding to the node. The node structure further specifies the location of the node. FIG. 11 illustrates the data structure for an edge item. This data structure has a reference to its edge. In addition, like a node data structure, an edge item's data structure includes a net identifier that specifies the net of the edge-item's topological route. This structure also includes a pair of edge references that refer to the next and previous topological item (i.e., node or edge item) on its edge. The edge-item data structure also has a pair of planar-path references that refer to the planar topological items (i.e., items on the same layer as the edge item) that are adjacent to the edge item in its topological route. FIG. 12 illustrates the data structure for a face item. The face-item data structure In the embodiments described below, a face item can serve as the topological position of a via. Accordingly, the face item data structure The layer of the topological items can be identified as follows. A node's layer can be identified by referring to its geometry. A face's or edge's layer corresponds to the layer of its nodes. In addition, a face item's layer corresponds to the layer of its face, and an edge item's layer corresponds to the layer of its edge. FIGS. 13 and 14 illustrate one example of topological routes. FIG. 13 presents two topological routes The route FIG. 14 illustrates the data structure representation of these topological routes As shown in FIG. 14, the nodes and edge items are inserted on their edge's linked list in the order that they are placed on their respective edge. For instance, the edge list 2. Overall Flow of Topological Router FIG. 15 illustrates a process After the triangulation, the process groups (at Next, the process selects (at Other embodiments, however, might process the nets differently. For instance, some embodiments might order the nets based on an entropy value (e.g., might order the nets in a descending order of entropies), and select the group of nets based on this order. Some of these embodiments then use a two-tiered approach in selecting the group of nets at In the embodiments described below, the topological engine uses an IDA* solving engine that deterministically searches for the best routing solution for the selected group of nets. An IDA* searching technique involves searching the solution space in an iteratively-deepening manner, up to a particular depth limit. Accordingly, at Some embodiments generate the cheapest route for each unsolved net by ignoring the routes of the other unsolved nets. Accordingly, these embodiments generate the cheapest routes for each net in the first group of nets being solved in an empty subregion (i.e., a sub-region that does not contain the topological routes of any other nets in the group). However, the cheapest routes for the subsequent groups of nets are computed for a sub-region that contains the topological routes of the previously routed nets. At At The process then determines (at As further described below, the solving engine returns an incomplete non-empty solution when it can only find topological routes for some of the nets in the selected group. If the process determines (at On the other hand, if the process determines (at On the other hand, if the process determines (at After assigning face-item shapes, the topological-routing process At 3. Triangulation Different embodiments use different topological structures to define topological routes. The embodiments described below use triangulated graphs of the sub-region. Specifically, these embodiments use a constrained Delaunay triangulation (“CDT”) technique. Several such techniques are disclosed in C. L. Lawson, “Transforming triangulations”, DiscreteMath, 3:365-372, 1972; C. L. Lawson, “Software for C Surface Interpolation,” In J. R. Rice, editor, FIG. 16 illustrates a triangulation process The process next defines (at One of ordinary skill will realize that other embodiments might define graph nodes slightly differently. For instance, some embodiments might define a graph node for only some of the virtual pins. These embodiments select as triangulation nodes vpins that are near interior geometry nodes that are close to the boundary. Of the remaining vpins, these embodiments select every nth (e.g., 5 Next, the process creates (at FIG. 18 illustrates this triangulation technique. In this example, two triangles After defining a set of triangles at FIGS. 19 and 20 illustrate why maximizing the minimal angle of each triangle improves the likelihood that the generated topological routes can be geometrized. In these figures, nodes Some embodiments perform an edge-flipping operation by identifying, for each triangle, a circle that encompasses all of the triangle's vertices. If that circle encompasses the vertex of another triangle as well, and if the two triangles do not jointly form a non-convex polygon, then the common edge between the two triangles is flipped. Flipping an edge between two triangles means deleting the existing common edge between the two triangles and defining a new common edge between the two vertices of the triangles that were not previously connected. The edge flipping operation typically results in a new pair of triangles that has larger minimal angles than the original pair of triangles. When a pair of abutting triangles form a non-convex structure, the common edge between them is not flipped. FIGS. 21 and 22 illustrate one manner for performing the edge-flipping operation. FIG. 21 illustrates two triangles After performing the edge-flipping operation at Next, the process performs (at In some embodiments, the triangulation operation defines the capacity of each edge in the triangulated regions. The above-described triangulation operation defines each edge's capacity whenever it creates the edge at As shown in FIG. 25, the process After
where α is the angle between the capacity vector C and the legal routing direction D. Accordingly, the edge capacity is the magnitude of the projection vector. In the example illustrated in FIG. 26, edge The largest projection of the capacity vector can be identified (at Other embodiments might compute the edge capacities differently. For instance, some embodiments might define each edge (including an edge that does not connect to vpins) to be its own capacity vector. Some of these embodiments then specify each edge's capacity as the edge's largest projection onto one of the legal routing directions. 4. Solving Engine a. Jointly Routing Groups of Nets with an IDA* Search Engine As mentioned above, the topological routing engine calls (at The IDA* solving engine traverses the solution space in an iterative-deepening manner up to a particular depth limit. FIG. 27 pictorially illustrates an example of this engine's IDA*-searching operation for a set of three nets. As shown in this figure, the IDA* solving engine initially identifies several topological routes After identifying the solutions for the first net, the IDA* solving engine selects a topological-routing solution for the first net. At each level of iteration, the search selects the solutions according to a quality metric. In the embodiments described below, this quality metric is the length of the topological routes. Other embodiments might use different quality metrics. In the example illustrated in FIG. 27, the topological routes for each net get longer from left to right (i.e., the solutions get worse going from left to right). Accordingly, in the example illustrated in FIG. 27, the first selected solution for the first net is the best solution After identifying the solutions for the second net, the IDA* solving engine selects the best solution After examining all the solutions The solving engine then determines whether it has examined all the previously-defined solutions for the net at the previous level of the search. At this stage, this previous example is net However, the solving engine cannot embed any of these routes Accordingly, the solving engine examines the solution space that results from the selection of the next best solution This solution will be the optimal solution or very close to it so long as the depth limit is increased by small increments from its lowest possible value. For instance, when the depth limit is increment by 10%, the solution will be within 10% of the optimal solution. Some embodiments described below introduce two additional constraints in the operation of the solving engine. First, these embodiments limit the solving-engine's IDA* search to a maximum number of iterative attempts, referred to below as pushes. This is to decrease the run-time of the solving engine. Limiting the number of pushes might cause the solving engine to return a solution that is not the optimal, but this might be acceptable in some situations as a reasonable tradeoff for run-time speed. Second, the solving engine in these embodiments considers the impact of the routes selected for the nets in the selected group on the nets not yet selected. In other words, while solving the selected group of nets, the solving engine considers the routing cost of nets that have not yet been selected. In the embodiments described below, the solving engine generates a lower bound estimate on the cost of the unselected nets, and ensures that the depth limit is not exceeded by the sum of this estimate and the actual or predicted costs of the nets in the selected group. b. Solving FIG. 28 illustrates a more detailed process When the specified group of nets is not the first group of nets that the solving engine has solved (i.e., if the topological route has called the solving engine previously to solve a different group of nets), the sub-region includes the topological routes of the previously-solved nets. In addition, when the process After Some embodiments store the routes in an array of N data objects, where N corresponds to the number of nets that the solving engine is trying to solve. In other words, there is one data object for each of the N nets. Each data object can store the route solution pool of its net, and includes a pointer into this pool that specifies the solution currently being explored. This pointer traverses through the solution pool as the IDA* solving engine examines the solutions of its net. At Next, the process determines (at When the process determines (at If the process determines (at At On the other hand, if the Push_Count is not equal to the maximum number of pushes, the process determines (at If not, the process (at As mentioned above, the process On the other hand, if the process determines (at If the process determines (at If not, the process clears (at C. Route Generation FIG. 29 illustrates a process As shown in FIG. 29, the process The process then identifies (at Next, the process generates (at If so, at As mentioned above, the process can transition to If the Depth_Limit does not exceed the maximum depth limit, the process transitions to If the process determines (at On the other hand, if the process determines that it has examined all the pin-pairs, the process (at After After d. Path Generation FIG. 31 illustrates a process The process then identifies (at FIG. 33 illustrates that a node can expand (1) towards the opposing edges of two faces that abut the node, (2) towards the other nodes of these two faces, (3) towards face items of these two faces, and (4) towards one or more nodes and face items above or below it. A node can via up or down to more than one node or face item, when more than one triangulated graph is above or below the node. Some embodiments explore each potential via expansion possibility of a node. FIG. 34 illustrates that a face item can expand towards the three nodes and edges of its face. Some embodiments do not allow a planar expansion from a face item (i.e., an expansion to an item in the same face as the face item) when the face item was reached through a planar expansion. In other words, these embodiments only allow a via expansion from a face item, when the face item was reached through a planar expansion. Like via-path expansion from a node, a path can via up or down from a face item. Some embodiments do not allow a via expansion in a particular direction (e.g., down) from a face item, when the face item was reached in a direction opposite to the particular direction (e.g., up). Also, like a node, a face item can via up or down to more than one node or face item above or below it, since more than one face of the above/below triangulated graph can be above or below the face item. As with a node, some embodiments explore each potential via expansion possibility of a face item. Also, as illustrated in FIGS. 35 and 36, when the face item serves as the destination of a via from another layer, the face item has more expansion possibilities if topological routes intersect its face. For instance, in FIG. 35, one net runs through the destination face item's face, and the face item has eight expansion possibilities, with five of them being on one side of the router and the other three being on the other side of the route. In FIG. 36, two nets run through the destination face item's face, and the face item has ten expansion possibilities. When it is time to expand from a destination face item, some of the expansion possibilities might be quickly eliminated if there is no space for the via to be located in a region that gives rise to the expansion possibilities. For instance, in FIG. 36, the only viable via location might be in the region between the two crossing routes. In such a circumstance, the three and five expansion possibilities on the other sides of these route will not be explored. After identifying the expansions from the Current_Point at If the process determines (at At After At If the Current_Point is not a source node, the process transitions to e. Legality Check For some embodiments, FIG. 37 provides a table that illustrates the types of legality checks performed for different combination of expansions. The vertical axis lists the starting points of the expansion, and the horizontal axis lists the destination points of the expansion. As shown in FIG. 37, the are three types of legality checking. These are: planarity, via checking, and edge capacity. (1) Edge Capacity Check The edge capacity check is performed each time a path tries to intersect an edge. This legality check requires that the flow across the destination edge after the potential move not exceed this edge's capacity. FIG. 38A and 38B illustrate how to compute the flow of an edge after a potential expansion. Specifically, FIG. 38A illustrates the center-lines of routes for two nets that were previously inserted across an edge FIG. 38B illustrates how the edge (2) Via Legality Check As indicated in FIG. 37, the via check is performed for each possible expansion. Different embodiments of the invention perform the via-checking operation differently. FIGS. 39A and 39B illustrate two different processes for performing this checking operation. (i) Optimization Technique FIG. 39A illustrates a process In the embodiments described below, there is no expansion face when a node is the destination of a via expansion. The process However, some embodiments could examine each face that contains a path-expansion's destination item, as this approach has several advantages. For instance, such a check would allow the router to detect an illegal via-path expansion when the router imposes a larger minimum-spacing requirement for a destination node that serves as a via than for a destination node that does not. If the expansion is a via expansion to a node, there is no face to check at On the other hand, if the identified expansion is to a face item or, in a planar expansion, to a node or edge item in an expansion face with a face item, the process For a face item in a face involved with a path expansion, the constraints include constraining points and minimum required distance to each constraining point. If the face item is moveable, the face item's set of constraints also specifies a legal x,y region that can contain the face item. Some embodiments allow each face to have up to two face items. When a face item is within a face that contains another face item, the process FIGS. 70-82 present several examples that illustrate the type of constraints identified by the process FIG. 70 illustrates a potential face item F In the embodiments described below, the edge and node constraints of a face item are the minimum required distances from the face item to the edges and nodes of the face that contains the face item. Specifically, for the face item, the constraint with respect to each node represents the required width and spacing of the minimum set of topological items (if any) that separate the face item from the node. For the face item, the constraint with respect to each edge is the required width and spacing of the minimum set of topological items (if any) that topologically separate the face item from the edge. One manner of computing edge and node constraints is further described below. FIG. 71 illustrates the edge and node constraints for the potential face item F As shown in FIG. 71, the face item F The process The process Each time the process FIG. 73 illustrates an example identical to the example illustrated in FIG. 70, except that the face The process For the example illustrated in FIG. 73, the node and edge constraints for the face item F The face item F For the via formed by these three face items, the process Based on the identified legal region and node constraints for each face traversed by the via that F As mentioned above, the process As mentioned above, some embodiments allow a face to have at most two face items. These embodiments limit the number of face items to improve run-time efficiency. Other embodiments, however, might allow a face to have more than two face items. These embodiments would identify node, edge, and region constraints similarly to the examples described above. They would also analogously identify repulsion constraints between face items in a face except that, in a face with three or more face items, the required constraint between two face items would be the sum of the width of each route and/or face item between these two face items plus the required minimum spacing between the route(s) and face items. A face could also include a face item that is a Steiner point. FIG. 79 illustrates a face The process Accordingly, when a via starts or ends with a node, the process FIG. 81 illustrates an example of a via formed between a node N A face item might exist on a face that connects through a via to a face involved with an expansion. FIG. 82 illustrates an example of such a face item. This figure illustrates a potential expansion between face items F The face In some embodiments, the process In some embodiments, the process uses a stack to keep track of the minimum required distances as it traverses the edges. In traversing the edges, the process might encounter routes for three types of other nets. The first type does not connect to a face item within the face. The second type connects to a face item with a degree greater than one (i.e., connects to a face item that connects to more than one topological item on the face boundary). The third type connects to a face item with a degree one (i.e., connects to a face item that only connects to one topological item on the face boundary) The process adds to the stack the required width plus spacing distances of the encountered routes for the first- and second-type nets when it encounters these routes for the first time while traversing the identified face's edges. The process removes from the stack the distances of each such route when it encounters the route for the last time while traversing the identified face's edges. When the process encounters a route for a third-type net while traversing the identified face's edges, the process does not add any space and width distance to the stack. Additionally, when the process encounters either a second- or third-type route while traversing the edges, the process identifies and stores the required repulsion distance between the face item that it is currently examining and the face item that is connected to the encountered second- or third-type route. The process Identifying the constraint for a node that connects to a route is slightly more involved. When the process encounters such a node, it determines whether it is the last time that it will encounter the route connected to the node before completing its loop traversal about the identified faces edges. If so, this node constraint is (1) the value on the stack after the removal from the stack of the spacing and width distances of net route that connects to the node, plus (2) the minimum required distance between the last edge item encountered and the node. If not, this node constraint is (1) the value on the stack before the addition to the stack of the spacing and width distances of net route that connects to the node plus (2) the minimum required distance between the last edge item encountered and the node. Each time the process After identifying constraints at If the process determines (at If the process determines (at For each non-via face item in a face involved with the expansion, the process where p is a variable that represents a point in the set of constraining points for the face item, P is the final point in the set, d For a face item that forms a via with a node (i.e., a face item that has a fixed position for the process where p is a variable that represents a point in the set of constraining points for the face item, P is the final point in the set, d At For a set of face items that form a moveable via, the sub-function again has the form: In this equation, p is a variable that represents a point in the set of constraining points for all the face items, P is the final point in the set, and r When a face examined by the process where d When both face items are moveable, the x,y location for both face items can vary within regions defined for them. For the two face items F In Equation (4), a face item's x,y location is fixed when it forms a via with a node. For example, for the two face items F In Equation (4), a face item's x,y location is also fixed when the face item is on a face that (1) is not involved with a path expansion but (2) connects through a via formed by another face item to a face that is involved with an expansion. For instance, face item F At
In this function, (1)f The function formulated at After formulating the cost function at After performing the minimization operation, the process (ii) Non-Optimization Technique FIG. 39B illustrates a process If the process Next, the process computes (at (3) Planarity Check As indicated in FIG. 37, the planarity check is performed for four of the expansions. For the node to node expansion, the planarity check simply ensures that there is no route crossing the shared edge between two nodes. All other planarity checks are performed by traversing the linked list of edges from the source towards the destination node/edge, checking that no other net's route blocks a direct connection between the source and destination items of the path expansion. f. Cheapest Path Calculation FIG. 40 illustrates a process for computing the cheapest-route cost for a net. As shown in FIG. 40, the process The process then identifies (at After If the process determines (at On the other hand, if the process determines that it has examined all the pin-pairs, the process (at At In some embodiments, the routability checking is performed by a routability engine that initially reduces wiring congestion by moving vias, and then determines whether the identified topological routes are geometrically routable. FIG. 41 conceptually illustrates a process As shown in this figure, the routability process After identifying congestion graphs and determining the capacity and flow of edges in these graphs, the process Next, the process 1. Congestion Graphs. a. Defining Congestion Graphs. Different embodiments of the invention construct different congestion graphs to measure the congestion in the IC sub-region being routed. For instance, some embodiments construct a visibility graph for each sub-region layer, while other embodiments generate for each layer a graph that is an approximation of the visibility graph (an “approximated visibility graph”). Some embodiments construct a visibility graph for a layer by taking the triangulated graph for the layer and adding additional visibility edges. For instance, in some embodiments, the visibility graph includes a node for each corner of its sub-region layer and each point of a port or obstacle geometry, vpin, and vias. These embodiments then define an edge between every two nodes that have an unobstructed view of (i.e., an unobstructed path to) each other. For each node, these embodiments also define an edge for each unobstructed projection of the node onto each of its layer's bounding sides. Other embodiments construct an approximate visibility graph for each sub-region layer. Some embodiments construct such a graph for each layer by duplicating the triangulated graph of the layer and adding additional edges about the nodes of the duplicated triangulated graph. Specifically, for each particular node in the triangulated graph, these embodiments identify the faces adjacent to the particular node. For each identified face that is a boundary face (i.e., a face that has a portion of the layer's boundary as one of its edges), a new edge is defined for the projection onto the boundary of the face's node that is not on the boundary. On the other hand, for each identified face that is not a boundary face, these embodiments identify the other face (“opposing face”) that shares the edge that is opposite to the particular selected node. If the identified and opposing faces form a convex quadrangle, these embodiments then determine whether the identified edge between these two faces can be flipped. If so, a new flipped edge is defined (i.e., an edge is defined between the particular selected node and the opposing face's node that is not on the shared edge). This new-flipped edge results in two new faces that connect to the selected particular node. This process is repeated for all the identified and resulting faces to define additional edges that connect the particular node to other nodes “visible” to it. b. Compute Capacity and Flow for Each Congestion Graph Edge. A layer's visibility or approximate visibility graph takes the layer's triangulated graph and adds additional edges. In both cases, the capacity and flow of each edge that is part of a triangulated graph were previously computed during the topological routing process as described above. On the other hand, the routability engine has to compute the capacity of each congestion-graph edge that is unique to this graph (i.e., each edge that is not in the corresponding triangulated graph). The capacity of an edge that is unique to a visibility or approximate visibility graph can be computed by performing the operations described above by reference to FIG. The routability engine also has to compute the flow of each unique-congestion graph edge (i.e., each edge that is not in the corresponding triangulated graph but is only in the congestion graph). For both the visibility and approximate visibility graph, the flow of each unique congestion-graph edge can be computed based on the flow of the edges that surround and/or intersect the unique congestion-graph edge. When only two edges surround the unique congestion-graph edge (such as when the unique congestion-graph edge represents the projection of a boundary-face node onto a boundary), the flow of the unique congestion-graph edge can be derived from the flow of the two surrounding edges. On the other hand, the unique congestion-graph edge can be shared by two faces that form a quadrangle. The unique-congestion graph edge is one of the diagonal edges of such a quadrangle. The quadrangle can have another diagonal edge that intersects the unique congestion-graph edge. When the unique congestion-graph edge is shared by two faces, the process for performing this computation for a visibility graph is recursive. This is because one or more of the edges that surround or intersect a unique congestion-graph edge might themselves be unique congestion-graph edges. On the other hand, the flow of each unique non-boundary, congestion-graph edge in the approximate visibility graph can be computed non-recursively, since the flow of each unique congestion graph edge can be defined based on the previously-computed flows of its surrounding and intersecting edges. 2. Reduce Congestion. As mentioned above, the process To examine congestion about vias, the routability engine defines a congestion sector for each the legal routing direction. FIG. 42 illustrates eight such sectors that are defined around the eight routing directions of the octilinear wiring model illustrated in FIG. In other words, (1) sector one identifies the projection onto the 0° routing direction of the capacity vectors with directions between ±22.5, (2) sector FIG. 43 illustrates a process The process then selects (at At Next, the process determines (at The process then determines (at Each Max_Congestion is the largest Max_Overflow among three adjacent sectors. FIG. 44 illustrates four sets of adjacent Manhattan sectors, while FIG. 45 illustrates four sets of adjacent 45° sectors. Accordingly, each Max_Congestion value is defined along one of the octilinear directions. More specifically, FIG. 44 illustrates (1) a Max_Congestion FIG. 45 illustrates (1) a Max_Congestion To identify the particular Max_Congestion value for a particular set of sectors, two of the three Max_Overflow values have to be projected onto the particular octilinear direction corresponding to the particular Max_Congestion value. For instance, the Max_Congestion Once the process Based on the computed Max_Congestions, the routability engine determines whether it can move the via. Specifically, the routability engine makes this determination by examining corresponding pairs of Max_Congestion values. Each pair relates to two opposite directions on the Manhattan or 45° axis. For the Manhattan axis, one corresponding pair includes the Max_Congestion Some embodiments use the following criteria to determine whether a move is possible in a particular axis direction of the Manhattan or 45° axis. If the corresponding pair of Max_Congestions for a particular axis direction (e.g., for the positive and negative Manhattan x-directions) are both positive, the via is not moved in either direction specified by the pair (e.g., it is not moved in the positive or negative Manhattan x-directions). On the other hand, when one Max_Congestion of a corresponding Max_Congestion pair (e.g., the total for the positive Manhattan x-direction) is negative, while the other (e.g., the total for the negative Manhattan x-direction) is positive, the via can be moved in the direction with the negative Max_Congestion (e.g., in the positive Manhattan x-direction) until one of the Max_Congestions for the pair is 0. When the corresponding pair of Max_Congestions for a particular axis direction (e.g., for the positive and negative Manhattan x-directions) are both negative, the via can be moved in the direction with the more negative Max_Congestion until both Max_Congestions are equal. As mentioned above, some embodiments define the edge capacity and flow in terms of the edge length and net width, which, in turn, makes distance the unit for quantifying congestion. Accordingly, in these embodiments, the amount of a via move is directly specified by the congestion values. For instance, when the Max_Congestion of the +x-axis Manhattan direction is 25 while that of the -x-axis Manhattan direction is −75, the via can be moved in the -x-axis direction by 50 units. In some embodiments, each unit is to equal to the IC-manufacturing-grid unit. Based on the criteria recited above, the routability engine examines the potential for moving the via on each axis of the Manhattan and 45° coordinate systems. If the routability engine determines that the via movement is only possible within one of the coordinate systems, then the routability engine moves the via according to the potential x- and/or y-axis moves this coordinate system. On the other hand, if the routability engine determines that the via movement is possible within both coordinate systems, it identifies the best coordinate system for the movement. For each particular pair of corresponding directions in the Manhattan and 45° coordinate systems, some embodiments compute a balance factor that measures the difference in Max_Congestions of the particular pair after the potential move in the axis direction of the pairs. For each coordinate system, these embodiments then generate an overall balance factor that combines the two balance factors for the two axis directions of the coordinate system. Some embodiments generate the overall balance factor of a coordinate system by summing up the balance factors for the x- and y-axes directions. The routability engine then picks the via movement in the coordinate system with the better overall balance factor. After moving a via, the routability engine has to recompute the capacity and flow of edges that connect to the via on any layer of the sub-region. The operations for computing the capacity and flow of an edge are identical to those discussed above for the topological router. The process for reducing congestion by moving vias can be performed several times. Some embodiments perform several such iterations, because each iteration might move one or more vias, which, in turn, would affect the congestion of nearby edges, which, in turn, might allow or necessitate additional via movements. 3. Computing Congestion and Interacting with Topological Router After moving vias to reduce congestion, the routability process If the process identifies no congested edges, it ends. However, if it identifies congested edges, the process directs (at In different embodiments, the routability and topological engine interact in different ways to identify other topological routes. In some embodiments, the routability engine needs to identify the edges that are congested to the topological engine. In some of these embodiments, the congested edges are often the edges that are unique congestion-graph edges (i.e., are edges that are not in the topological router's triangulated graphs). Hence, in some embodiments, the routability engine needs to relay to the topological router the congestion problem without referring to unique congestion-graph edges that are not used by the topological router. In some embodiments, the routability engine conveys the congestion problem of a unique congestion-graph edge by identifying the triangulated-graph edges that connect the same endpoints as the unique congestion-graph edge. For instance, FIG. 46 illustrates a unique-congestion graph edge The topological router can then use the edge-identity information in several ways. For instance, it can reduce the flow of the identified edges and then identify topological routes for the nets that previously crossed the identified edges. Alternatively, for each particular triangulation-graph edge, the topological router keeps in some embodiments a record of the number of other edges that need to be analyzed with the particular edge during the edge capacity-checking operations of the route generation process. Accordingly, when the routability engine identifies a set of edges that need to be collectively analyzed in order to capture the congestion of a particular congestion-graph edge, the topological router stores the identified set (once for all edges in the set or once for each edge in the set); each time a path tries to cross one of the edges in the set, the path generation process not only checks the edge's individual capacity, but also compares the remaining capacity of all the edges with the specified capacity of the congestion-graph edge. If the topological router repeatedly fails to generate geometrically routable topological routes for a particular set of edges, the routability engine flags one or more nets as unroutable, directs the topological router to define routes the remaining nets crossing the set of edges, and then transitions to After the routability checking, the process In some embodiments, the geometric engine generates the design-rule-correct routes by referring to path-refining edges. These edges are specified about vpins, vias, ports, and obstacles in directions that constrain the embedding of geometric routes about obstacles and unrelated vpins, vias, and ports. In some embodiments, the geometric engine performs four operations to generate the design-rule-connect routes for topological routes on a layer. These operations are explained for the octilinear wiring model of FIG. First, for each of the four constrained directions, the geometric engine generates one set of path-defining edges about the geometric points in the layer. In other words, four sets of path-defining edges are defined along ±22.5° and ±67.5° directions. FIG. 47 illustrate a simple example of a portion of a layout that has two obstacles about which two topological routes for two nets Second, the geometric engine generates four “partial” route representations for each topological route. Each partial route is defined with respect to one set of path-defining edges. In addition, the geometric engine produces each partial design-rule-correct route for a net's topological route on a layer by (1) identifying the path-defining edges intersected by the topological route, (2) based on the design rules, identifying the segments of the intersected path-defining edges that are available for constructing the partial route, and (3) generating the shortest path between the endpoints of the topological route (on that layer) that traverses the identified segments. Some embodiments identify the constrained boundaries of path-defining segments that a net's route can intersect based on the location of the center-line of the net. Some embodiments also require that all the nodes in the path-defining-edge graph lie on the manufacturing grid. FIGS. 48A-48D specify with dots the segments of the path defining edges that have been constrained for net FIGS. 54 and 55 provide two more-detailed examples for identifying the spacing and width requirements on the constraining directions. FIG. 54 illustrates two nets In the example illustrated in FIG. 54, the x-coordinate of the left-most constrained endpoint
where,
and “ceil” signifies rounding up to the next manufacturing grid. This manner of defining the y-coordinate of the left-most constrained endpoint FIG. 55 illustrates nets
where,
This manner of defining the x-coordinate of the left-most constrained endpoint After identifying the path-defining edges intersected by the topological route, and identifying the constrained segments of the intersected path-defining edges that are available for constructing the partial route, the geometric engine generates the shortest path between the endpoints of the topological route that traverses the identified segments. FIGS. However, unlike the case for the topological router which defined the shortest distance within a polygon, the geometric engine identifies the shortest distance among a set of parallel path-defining edges. Whenever this engine is defining constraints on the path defining edges, it detects when a route bends 180° around an obstacle or unrelated geometry (i.e., bends around the obstacle or geometry and intersects a path-defining edge that is co-linear with a previous path-defining edge), and breaks the path into two structures around the bend in order to avoid inflection points. It then computes the shortest path for each structure, and later joins the resulting paths for these structures to define a partial path. FIG. 56 illustrates another example of identifying a shortest partial path after constraining segments of the intersected path-defining edges. This figure illustrates five 22.5° path-defining edges Third, the geometric engine examines the points of the four partial paths defined during the previous operation and removes points that should not be considered for the merged path. Fourth, the geometric engine merges the four partial routing solutions into a single design-rule-correct route. In some embodiments, the geometric engine performs the third and fourth operations by using polygons that represent the wiring model being used. For instance, FIGS. 49A and 49B illustrate two octagons that represent the octilinear wiring model of FIG. Each of these octagons has a specific vertex for connecting to a partial-path point that is defined along a specific constraining direction. FIG. 49C identifies the eight possible directions that can be constrained by the four constraining angles, ±22.5° and ±67.5°, for the octilinear wiring model. FIGS. 49A and 49B identify constrained directions that correspond to their octagon vertices. For instance, the negative octagon's vertex To identify an unnecessary partial-path point, the geometric engine places the negative octagon's vertex that corresponds to the point's constraining direction on the point. The geometric engine determines to take out the point, if either segment that connects to this point on the partial path falls within the negative octagon. In the examples of FIG. 48, all the partial-path points of the −22.5° and −67.5° angles can be eliminated by using this approach. Similar approaches are used to merge the partial paths. Specifically, to identify the first point of the merged paths, the positive octagon is placed on the first points of each partial path that remains after the point-removal operation. The positive octagon is placed on each point at its vertex that corresponds to the constraining direction used to identify the point. The point that is selected is the first point of the solution whose first path (i.e., the path from the starting point to the first point) does not intersect the positive octagon or lies on the octagons border. To select each successive point except the last, one positive octagon is placed on the last selected point and another is placed on the next point in the selected point's partial path. If the segment connecting these two points does not fall within either positive octagon, then the next point in the partial path is selected as the next point in the merged path. On the other hand, if the segment connecting these two points falls within either octagon, then next point in the selected point's partial path is not selected Rather, the next point in the merged path is identified to be the next remaining point of the solution set whose constraining direction is clockwise or counterclockwise adjacent to the constraining direction of the last selected point. The solution of the adjacent clockwise direction is selected when the constraining node of the last selected point was on the right of the oriented path segment to the last selected point. On the other hand, the solution of the adjacent counter-clockwise direction is selected when the last point's constraining node was on the left of the oriented path segment to the last selected point. When all the partial solutions are empty except one, the last point or points are selected from the remaining non-empty partial solution. FIG. 50 illustrates the merged path After generating a merged design-rule-correct route, the geometric engine can then generate and embed a geometric route based on the merged route. The geometric engine directly embeds all segments of the merged path that are in one of the octilinear directions illustrated in FIG. FIG. 51 illustrates the projection of a segment In the example illustrated in FIG. 51, the partial solution for segment The geometric engine then sorts the constraints in a direction perpendicular to either octilinear direction resulting from the projection. At this stage, the geometric engine has defined a sorted structure of points that it needs to analyze. One manner for generating geometric routes will now be described by reference to the example of FIG. In this example illustrated in FIG. 51, the constraints are sorted in the Y-axis direction (in the direction perpendicular to the x-axis direction). Also, this sorting leads the geometric engine to store a list of sorted points, starting with node The geometric engine stores the node The next point on the sorted order is point The engine then selects the next sorted point, which is point FIG. 50 illustrates the center-point line for the geometric route of the merged route of net FIG. 53 presents a geometric-routing process performed by the geometric engine of some embodiments of the invention. As shown in this figure, the process After assigning locations to each edge item on the selected layer, the process At After selecting a wiring model, the process Like a triangulated-graph edge, a path-defining edge has a data structure that includes a linked list of items on the edge, where each item on the list points to the next and previous items in the list. This list starts and ends with the endpoints of the edge. As mentioned below, edge items are added between the edge's endpoints to represent routes as routes are inserted in the edge. After specifying the path-defining edges in the constraining angle selected at A path's linked list starts and ends with the endpoints of the path, and in between can include edge items on one or more path-defining edges. Hence, after After creating the new route descriptions at After identifying the path-defining-edge segments that are available for constructing the partial path of the selected path, the process The process then determines (at When the process The process then determines (at Multi-layer routes use vias to traverse from one interconnect layer to another. Each via between two layers has three components, which are (1) the via contact on one layer, (2) the via contact on the other layer, and (3) at the overlap of the via contacts, a cut that represent the cavity for placing interconnect materials to connect the via contacts. At times, multiple via cuts and contact pairs forms one conceptual via. For instance, as shown in FIG. 58, multiple via cuts and contact pairs FIGS. 59-63 illustrate various shapes of vias that are used in some embodiments of the invention. These shapes can also be used as the shapes of non-via face items. FIG. 59 illustrates the shapes of two corresponding via contacts (ie., two via contacts on different layers that are interconnect to form a via). As shown in this figure, some embodiments use a square shape for one of the contacts FIG. 60 illustrates an alternative shape for a via contact. As shown in this figure, a via contact All of the described via shapes can be used with any wiring model, but work particularly well when they are used with a wiring model that allows Manhattan and ±45° interconnect lines. When a hexagonal wiring model is used (e.g., a wiring model that allows horizontal and ±60° lines, or a wiring model that allows vertical and ±30° lines), some embodiments use hexagonally-shaped via contacts. FIG. 61 illustrates one such hexagonal contact FIG. 62 illustrates another via shape that is used in some embodiments. This figure presents a circular via In some embodiments, the interconnect-line endpoints have non-rectilinear shapes. Each route is defined by one or more interconnect lines, and each interconnect line can be straight or it can have one or more bends. Accordingly, a route can have multiple interconnect-line endpoints, such as Steiner points, interconnect-line terminations on vias, and interconnect-line terminations on the net's routable elements (e.g., on the net port geometries). In some embodiments, interconnect lines can terminate in half-octagons or half hexagons. FIG. 63 illustrates an interconnect-line In some embodiments, the above-described router represents each route as a collection of points that define the traversal path of the route (e.g., represents each route as a collection of points that define the traversal of the center-line path), and leave the defining of the interconnect-line shapes to another stage of the EDA process (e.g., the wire shapes can be generated when writing the routing data into a GDS file, when displaying the routes, or before extraction). One of ordinary skill will realize, however, that in other embodiments the router uses the interconnect-line shapes. Interconnect lines that terminate in half-octagons, half-hexagons, or half-circles can be used with any wiring model. However, interconnect lines that terminate in half octagons (such as interconnect line For instance, half-octagon interconnect lines (i.e., interconnect lines that terminate in half-octagons) provide a good general structure that matches well the different via shapes that might be used with the octagonal wiring model. FIG. 66 illustrates this matching. Specifically, this figure illustrates the overlap between a half-octagon interconnect line and (1) a square via, (2) a diamond via, and (3) an octagonal via. Similarly, half-hexagon interconnect lines (ie., interconnect lines that terminate in half-hexagons) provide a good general structure that matches well the different via shapes that might be used with the hexagonal wiring model. FIG. 67 illustrates this matching. Specifically, this figure illustrates the overlap between a half-hexagon interconnect line and (1) a square via, and (2) a hexagonal via. In addition, half-octagon interconnect lines form octagonal Steiner nodes when they are used with an octagonal wiring model, while half-hexagon interconnect lines form hexagonal Steiner nodes when they are used with a hexagonal wiring model. FIG. 68 illustrates an example of an octagonal Steiner node Half-circle interconnect lines accurately model endpoints of conductive lines on IC's, which typically are not rectilinear but rather arc somewhat semi-circular. Also, half-octagon and half-hexagon interconnect lines more closely model actual conductive lines on the IC's that traditional rectilinear interconnect-line ends. Similarly, circular, octagonal and hexagonal via contacts model the circular vias in the IC's more closely than square via contacts used by most EDA tools today. FIG. 83 presents a computer system with which one embodiment of the present invention is implemented. Computer system The bus From these various memory units, the processor Like the permanent storage device The bus The output devices Finally, as shown in FIG. 83, bus Any or all of the components of computer system While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims. Patent Citations
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