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Publication numberUS6832268 B2
Publication typeGrant
Application numberUS 10/324,863
Publication dateDec 14, 2004
Filing dateDec 19, 2002
Priority dateDec 19, 2002
Fee statusPaid
Also published asUS7386643, US20040122995, US20050060502
Publication number10324863, 324863, US 6832268 B2, US 6832268B2, US-B2-6832268, US6832268 B2, US6832268B2
InventorsSin S. Tan, Stanley S. Kulick, Rajesh S. Pamujula
Original AssigneeIntel Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions
US 6832268 B2
Abstract
A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.
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Claims(22)
What is claimed is:
1. A forward progress module, comprising:
an address conflict checking module to compare a first memory address from a first coherent input/output (I/O) transaction with at least one memory address corresponding to at least one processor-issued transaction to determine if an address conflict exists; and
a processor module to complete a first processor-issued transaction of the at least one processor-issued transactions that has the address conflict and to reject the first coherent I/O transaction, wherein the processor module waits for the first coherent I/O transaction to reenter the processor module after the forward progress module transmits the first coherent I/O transaction to an external I/O device, rejects remaining processor-issued transactions of the at least one processor-issued transaction other than the first processor-issued transaction that have the address conflict with the first memory address, completes the first coherent I/O transaction utilizing the processor module, and releases the remaining processor-issued transactions of the at least one processor-issued transaction that have the address conflict that were held in the forward progress module, once the first coherent I/O transaction is complete.
2. The forward progress module of claim 1, wherein the forward progress module is located in a controller device.
3. The forward progress module of claim 1, wherein the forward progress module is located in a switching device.
4. The forward progress module of claim 1, wherein the forward progress module is located in an input/output (I/O) device.
5. The forward progress module of claim 1, further including a processor transaction buffer to store the at least one processor-issued transaction.
6. The forward progress module of claim 5, wherein the processor transaction buffer stores multiple processor-issued transactions of the remaining processor-issued transaction that request the first memory address.
7. The forward progress module of claim 1, further including a second buffer module to store the first coherent I/O transaction.
8. The forward progress module of claim 7, wherein the second buffer module transmits the first coherent I/O transaction, after it is rejected, to an external I/O device, receives the first coherent I/O transaction from the external I/O device after a period of time, and transmits the first coherent I/O transaction to the processor module.
9. A multi-node computing system, comprising:
at least one processor to generate at least one processor-issued transaction;
at least one input/output (I/O) device to generate a first coherent I/O transaction; and
at least one forwarding device to receive the at least one processor-issued transaction, to receive the first coherent I/O transaction, and to resolve address conflicts, including
an address conflict checking module to compare a first memory address from the first coherent I/O transaction with at least one memory address corresponding to the at least one processor-issued transaction to determine if an address conflict exists; and
a processor module to complete a first processor-issued transaction of the at least one processor-issued transaction that has the address conflict and to reject the first coherent I/O transaction, wherein the processor module waits for the first coherent I/O transaction to reenter the processor module after the forward progress module transmits the first coherent I/O transaction to an external I/O device, rejects remaining processor-issued transactions of the at least one processor-issued transaction other than the first processor-issued transaction that have the address conflict with the first memory address, completes the first coherent I/O transaction utilizing the processor module, and releases the remaining processor-issued transactions of the at least one processor-issued transaction that has the address conflict that were held in the forward progress module, once the first coherent I/O transaction is complete.
10. The multi-node computing device of claim 9, wherein the at least one forwarding device is located in a scalability controller.
11. The multi-node computing device of claim 9, wherein the at least one forwarding device is located in a switching device.
12. The multi-node computing device of claim 9, wherein the at least one forwarding device is located in an input/output (I/O) device.
13. A method to forward transactions, comprising:
comparing a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists;
completing a first processor-issued transaction of the at least one processor-issued transaction utilizing a processor in a forwarding device if the address conflict exists by allowing the first processor-issued transaction access to a memory in the forwarding device;
rejecting the first coherent I/O transaction;
holding, in the forwarding device, remaining processor transactions of the at least one processor-issued transaction that have the address conflict with the first address of the first coherent I/O transaction;
transmitting the first coherent I/O transaction to an external I/O device while the processor in the forwarding device is completing the first processor-issued transaction, and
waiting for the first coherent I/O transaction to return from the external I/O device.
14. The method of claim 13, further including completing the remaining processor transactions with the address conflict once the first coherent I/O transaction has been completed utilizing the processor of the forwarding device.
15. The method of claim 13, wherein an I/O transaction buffer stores the first coherent I/O transaction, transmits the first coherent I/O transaction to the external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and transmits the first coherent I/O transaction to a processor module.
16. The method of claim 13, further including completing any processor-issued transaction without an address conflict with the first memory address of the coherent I/O transaction.
17. The method of claim 13, further including completing the first coherent I/O transaction in the forwarding device before releasing the remaining processor transactions being held in the forwarding device where the remaining processor transactions have the address conflict with the first coherent I/O transaction.
18. A program code storage device, comprising:
a machine-readable storage medium; and
machine-readable program code, stored on the machine-readable storage medium, the machine readable program code having instructions to:
compare a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists;
complete a first processor-issued transaction of the at least one processor-issued transaction utilizing a processor in a forwarding device if the address conflict exists by allowing the first processor-issued transaction to access a memory in the fowarding device; reject the first coherent I/O transaction;
hold, in the forwarding device, remaining processor transactions of the at least one processor-issued transaction that have the address conflict with the first address of the first coherent I/O transaction;
transmit the first coherent I/O transaction to an external I/O device while the processor in the forwarding device is completing the first processor-issued transaction, and
wait for the first coherent I/O transaction to return from the external I/O device.
19. The program code storage device of claim 18, including instructions to complete the first coherent I/O transaction.
20. The program code storage device of claim 19, wherein an I/O transaction buffer stores the first coherent I/O transaction, transmits the first coherent I/O transaction to the external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and transmits the first coherent I/O transaction to the processor module.
21. The program code storage device of claim 18, further including completing. any processor-issued transaction without an address conflict with the first memory address of the coherent I/O transaction.
22. A method to forward transactions, comprising:
comparing a first address from a first coherent input/output (I/O) transaction with an address from a plurality of processor-issued transactions in a forwarding device to determine if an address conflict exists;
completing a first processor-issued transaction of the plurality of processor-issued transaction utilizing a processor in the forwarding device if the address conflict exists by allowing the first processor-issued transaction to access a memory in the forwarding device
rejecting the first coherent I/O transaction;
holding, in the forwarding device, only a second processor transaction of the plurality of processor-issued transactions that have the address conflict with the first address of the first coherent I/O transaction in the processor transaction buffer;
transmitting remaining processor-issued transactions to a processor bus;
transmitting the first coherent I/O transaction to an external I/O device while the processor in the forwarding device is completing the first processor-issued transaction;
waiting for the first coherent I/O transaction to return from the external I/O device; and
completing the first coherent I/O transaction in the forwarding device before releasing the second processor transaction being held in the forwarding device.
Description
BACKGROUND

1. Technical Field

Embodiments of this invention relate generally to preventing starvation problems for incoming coherent Input/Output (I/O) transactions, and more specifically, to preventing starvation for incoming coherent I/O transactions against coherent processor-issued transactions when both transactions are attempting to access the same memory address.

2. Discussion of the Related Art

Coherent transactions may attempt to access a physical memory space. Coherent transactions access the physical memory space by requesting a read or write command to a specific memory address. A subset of coherent transactions, such as processor-issued transactions may be incoming that request the use of a specific memory address. Additionally, input/output (I/O) device issued coherent transactions may request the use of a specific memory address. For simplicity, the I/O device issued coherent transactions may be referred to as coherent I/O issued transactions. If the processor issued transactions request the same specific memory address as the coherent I/O issued transactions, a conflict arises. When the conflict arises, the coherent I/O issued transaction with the memory address conflict will not progress to its destination because of the address conflict. This conflict may occur while other non-conflicted coherent I/O transactions and all other processor-issued transactions progress to their destination.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a multi-node computing device according to an embodiment of the present invention;

FIG. 2 illustrates a forward progress module in a forwarding device according to an embodiment of the present invention; and

FIG. 3 illustrates a flowchart of a forward progress module to guarantee forward progress for coherent I/O transactions according to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 illustrates a multi-node computing device according to an embodiment of the present invention. A multi-node computing device may include at least one processor 100 102 104, at least one forwarding device 150, and at least one input/output (I/O) device 108. The multi-node computing device may also include a switching device (not shown). For simplicity only one forwarding device 150 is discussed. The forwarding device 150 may include a forwarding device memory 112 and a forwarding device processor 110. The at least one processor 100 102 104 may be coupled to one of the forwarding device 150 via a processor bus 114. In the embodiment where the at least one processor 100 102 104 is coupled to the at least one forwarding device 150 via a processor bus 114, the forwarding device 150 may be located in a scalability device (not shown). In embodiments of the invention, the at least one scalability device may also be referred as a North Bridge. In an alternative embodiment of the present invention, the at least one forwarding device 150 may be located in between the at least one scalability device 106 and the at least one I/O device 108, i.e., in the switching device. In this embodiment, the at least one forwarding device 150 may be connected to the at least one I/O device 108 through a second bus 116. Alternatively, the forwarding device 150 may be located in the I/O device 108. In Intel™ multi-node computing systems, for example, the scalability device may be a scalable node controller, the switching device may be a scalability port switch, and the I/O device may be a server input/output hub (SIOH).

The forwarding device 150 may receive a plurality of processor-issued transactions and a first coherent input/output (I/O) transaction. The at least one forwarding device 150 may compare a first memory address that the first coherent I/O transaction is trying to access against at least one memory address that the at least one processor-issued transaction is attempting to access. If the at least one forwarding device 150 determines that a memory address conflict exists between the first coherent I/O transaction and one of the at least one processor-issued transactions, the at least one forwarding device 150 may complete the first processor-issued transaction that has the memory address conflict with the first coherent I/O transaction. The forwarding device 150 may complete the one processor-issued transaction by instructing the forwarding device processor 110 to process the one processor-issued transaction and allow the first processor-issued transaction to access the address of the plurality of memory addresses; in the forwarding device memory 112.

The forwarding device 150 may reject the first coherent I/O transaction and transmit the first coherent I/O transaction to the second bus 116. The forwarding device 150 may hold remaining processor-issued transactions attempting to access the same address, i.e., the first address in the forwarding device memory 112 that the first coherent I/O transaction was attempting to address. After the first coherent I/O transaction returns from the second bus 116, the at least one forwarding device 150 may complete the first coherent I/O transaction by instructing the forwarding device processor 110 to allow the first coherent I/O transaction to access the first memory address in the forwarding device memory 112. After the first coherent I/O transaction is completed, the at least one forwarding device 150 may release and/or complete the remaining processor-issued transactions having the memory address conflict with the first coherent I/O transaction.

FIG. 2 illustrates a forward progress module in a forwarding device according to an embodiment of the present invention. The forward progress module 200 may include a processor transaction buffer 210, an address conflict checking module 212, an I/O transaction buffer 214, a processor module 216, a forwarding device processor 110, and a forwarding device memory 112. In an alternative embodiment, the forward progress module 220 may include a processor transaction buffer 210, an address checking module 212, and an I/O transaction buffer 214. In this embodiment, the processor module 216, the forwarding device processor 110, and the forwarding device memory 112 may be located external to the forward progress module 200. In one embodiment of the present invention, the forward progress module 200 may be located in a scalability controller device, such as an Intel™ Scalability Node Controller. In another embodiment of the present invention, the forward progress module 200 may be located in a switching device, such as an Intel™ Scalability Port Switch. Alternatively, the forward progress module 200 may be located in an I/O device 108, such as an Intel™ Server Input/Output Hub.

In an embodiment of the present invention, the processor transaction buffer 210 in the forward progress module 200 may receive at least one processor-issued transaction from at least one processor (not shown). In an embodiment of the invention, at least one processor-issued transaction may be received by a forward progress module 200. The at least one processor-issued transactions may be requesting access to at least one memory address, with each of the at least one processor-issued transaction requesting access to one of the at least one memory addresses. The I/O transaction buffer 214 may also receive a coherent I/O transaction from a plurality of I/O devices (not shown). The coherent I/O transaction may be requesting access to a first memory address.

The address conflict checking module 212 in the forward progress module 200 may compare the first memory address of the first coherent I/O transaction with the at least one memory addresses corresponding to the at least one processor-issued transaction. The address conflict checking module 212 may identify if an address conflict exists between the first memory address of the first coherent I/O transaction and at least one memory address of the at least one processor-issued transaction.

If the address conflict exists between the first memory address and the at least one memory address corresponding to the at least one processor-issued transaction, a first processor-issued transaction, which has the address conflict with the first memory address of the first coherent I/O transaction, may be completed by the processor module 216. The processor module 216 may complete the first processor-issued transaction by instructing the processor 110 to allow the first processor-issued transaction to access the corresponding memory address in the forwarding device memory 112. The first processor-issued transaction may be the first processor-issued transaction with the address conflict that entered the processor transaction buffer 210, e.g., a first-in, first-out structure. In another embodiment of the present invention, the first processor-issued transaction may be the processor-issued transaction with the address conflict that has the highest priority in terms of being executed. In another embodiment, the first processor-issued transaction may be the last processor-issued transaction with the address conflict that entered the processor transaction buffer 210, e.g., a first-in, first-out structure.

If there is an address conflict between the first memory address of the first coherent I/O transaction and at least one memory address corresponding to the at least one processor-issued transaction, the first coherent I/O transaction may be rejected and transmitted to the I/O device (not shown) via the I/O transaction buffer 214 and a second bus (not shown). In embodiments of the invention, any processor-issued transaction resident in the processor transaction buffer 210 may be processed and completed in a normal fashion if the address conflict does not exist with the first memory address of the first coherent I/O transaction. Additionally, a second address in a second coherent I/O transaction may be compared to at least one memory address corresponding to the at least one processor-issued transactions in the processor transaction buffer 210; and if no memory address conflict is present with the at least one processor-issued transactions, the second coherent I/O transaction may be completed by the processor module 216.

In embodiments of the present invention, more than one of the at least one processor issued transactions stored in the processor transaction buffer 210 may have the address conflict with the first memory address of the first coherent I/O transaction. If the address conflict exists between the first memory address of the first coherent I/O transaction and at least one memory address corresponding to the at least one processor-issued transactions, the forward progress module 200 may hold remaining processor-issued transactions, but not the first processor-issued transaction, of the at least one processor-issued transactions that request the first memory address in the processor transaction buffer 210. The forward progress module 200 may hold the remaining processor-issued transactions that request the first memory address to allow the first coherent I/O transaction to be completed at a future time.

In embodiments where more than one of the at least one processor-issued transactions have the address conflict with the first memory address, the forward progress module 200 may 1) send one of the processor-issued transactions, e.g., the first processor-issued transaction, to the processor module 216 for completion, 2) may reject the remaining processor issued transactions of the at least one processor-issued transactions, and may transmit the remaining processor-issued transactions, but not the first processor-issued transaction, of the at least one processor-issued transactions with the address conflict to the processor bus (not shown). The remaining processor-issued transactions may be resent to the forward progress module 200 of forwarding device 150 by the processor bus.

In one embodiment of the present invention, the processor transaction buffer 210 may only allow a single processor-issued transaction of the remaining processor-issued transaction that request the first address to be resident in the processor transaction buffer 210 at a specified period of time. In an alternative embodiment of the present invention, the forward progress module 200 may send the first processor-issued transaction to the processing module 216 for completion and may store the remaining processor-issued transactions of the at least one processor-issued transaction with the address conflict in the processor transaction buffer 210.

The forward progress module 200 of the scalability device 106 may wait for the first coherent I/O transaction to return from the second bus. In one embodiment of the present invention, the forwarding device 150 may wait for a specified period of time. In another embodiment of the present invention, the forwarding device 150 may wait until the first coherent I/O transaction returns, no matter how long the first coherent I/O transaction may take to return. In an embodiment of the present invention, the first coherent I/O transaction may return to the I/O transaction buffer 214. In this embodiment of the present invention, when the first coherent I/O transaction is the next transaction to be processed in the I/O transaction buffer 214, the forward progress module 200 of the forwarding device 106 may complete the first coherent I/O transaction. As discussed previously, completing the first coherent I/O transaction means that the processing module 216 instructs the forwarding device processor 110 to allow the first coherent I/O transaction to access the first memory address in the forwarding device memory 112. Once the first coherent I/O transaction is completed, the first coherent I/O transaction may be released from the I/O transaction buffer 214.

After the first coherent I/O transaction has been completed, any of the remaining processor-issued transactions being held by the forward progress module 200 of the forwarding device 150 may be released. In an embodiment of the present invention where the single processor-issued transaction is being held by the forward progress module 200 in the processor transaction buffer 210 and the remaining processor-issued transactions were sent to the processor bus, the forward progress module 200 may release the hold on the single processor-issued transaction and allow the processing module 216 to complete the single processor-issued transaction. Once the single processor-issued transaction is completed, the single processor-issued transaction may be released from the processor transaction buffer 210.

In embodiments of the invention where multiple remaining processor-issued transactions with the address conflict are being held by the forward progress module 200 in the processor transaction buffer 210, the forward progress module 200 may release the hold on the remaining processor-issued transaction of the at least one processor-issued transaction with the address conflict. The processing module 216 may complete the multiple remaining processor-issued transactions in any order. The multiple remaining processor-issued transactions may be completed in a first-in first-out (FIFO) manner, a last-in first out (LIFO) manner, or based on a priority assigned to them by the processor of the plurality of processors that initiated the processor-issued transaction. After the processing module 216 has completed the multiple processor-issued transactions, the other processor-issued transactions may be released from the processor transaction buffer 210

In embodiments of the invention where (1) multiple processor-issued transactions had an address conflict with the first memory address of the first coherent I/O transaction, (2) the first processor-issued transaction was completed, (3) a single processor-issued transaction of the remaining processor-issued transaction was held in the processor transaction buffer 210, and (4) the remaining processor-issued transactions were transmitted back to the processor bus (not shown), the forward progress module 200 may complete the single processor-issued transactions being held in the processor transaction buffer 210. Additionally, the forward progress module 200 may wait for the remaining processor-issued transactions to be transmitted back from the processor bus and may complete the remaining processor-issued transactions once they return form the processor bus. In this embodiment of the present invention, the other processor-issued transactions may be transmitted from the processor bus to the processor transaction buffer 210.

FIG. 3 illustrates a flowchart of a forward progress module to guarantee forward progress for coherent I/O transactions according to an embodiment of the present invention. The forward progress module compares 300 a first address from a first coherent I/O transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. If the address conflict exists, a first processor-issued transaction of the at least one processor-issued transactions is completed 302 and the coherent I/O transaction is rejected. The forward progress module holds 304 other processor-issued transactions in a processor transaction buffer if the new memory address of the other processor-issued transaction conflicts with the first memory address of the coherent I/O transaction. The forward progress module transmits 306 the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forward progress module releases 308 the hold on the other processor-issued transaction in the processor transaction buffer with the address conflict once the first coherent I/O transaction has been completed.

While the description above refers to particular embodiments of the present invention, it should be readily apparent to people of ordinary skill in the art that a number of modifications may be made without departing from the spirit thereof. The accompanying claims are intended to cover such modifications as would fall within the true spirit and scope of the invention. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description. All changes that come within the meaning of and range of equivalency of the claims are intended to be embraced therein.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7930459 *Apr 19, 2011Intel CorporationCoherent input output device
US8527708Jan 5, 2011Sep 3, 2013International Business Machines CorporationDetecting address conflicts in a cache memory system
US20080109624 *Nov 3, 2006May 8, 2008Gilbert Jeffrey DMultiprocessor system with private memory sections
US20090089468 *Sep 28, 2007Apr 2, 2009Nagabhushan ChitlurCoherent input output device
Classifications
U.S. Classification710/5, 710/33, 709/205, 710/58, 711/E12.035
International ClassificationG06F3/00, G06F12/08, G06F12/00
Cooperative ClassificationG06F12/0835
European ClassificationG06F12/08B4P4P
Legal Events
DateCodeEventDescription
Dec 19, 2002ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAN, SIN S.;KULICK, STANLEY S.;PAMUJULA, RAJESH S.;REEL/FRAME:013619/0814
Effective date: 20021216
Jun 13, 2008FPAYFee payment
Year of fee payment: 4
May 16, 2012FPAYFee payment
Year of fee payment: 8
Jul 4, 2013ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:030747/0001
Effective date: 20111122