|Publication number||US6848177 B2|
|Application number||US 10/112,961|
|Publication date||Feb 1, 2005|
|Filing date||Mar 28, 2002|
|Priority date||Mar 28, 2002|
|Also published as||US7112887, US20030210534, US20050090042|
|Publication number||10112961, 112961, US 6848177 B2, US 6848177B2, US-B2-6848177, US6848177 B2, US6848177B2|
|Inventors||Johanna M. Swan, Bala Natarajan, Chien Chiang, Greg Atwood, Valluri R. Rao|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (108), Non-Patent Citations (6), Referenced by (46), Classifications (20), Legal Events (5) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US 6848177 B2
An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.
1. A method of constructing an electronic assembly, comprising:
manufacturing a first integrated circuit on a first substrate, the first integrated circuit including a plurality of transistors formed in a semiconductor material of the first substrate and the first integrated circuit and the first substrate jointly forming a first die;
laser-drilling an opening in at least the semiconductor material of the first substrate;
forming a conductive member in the opening, the conductive member in the opening of the first substrate being electrically connected to at least one of the transistors of the first integrated circuit on the first substrate; and
stacking the first die on a second component having a circuit, the first integrated circuit being connected through the conductive member to the circuit of the second component.
2. The method of claim 1, wherein the opening is laser-drilled after at least a portion of the integrated circuit is manufactured.
3. The method of claim 2, wherein the transistors of the integrated circuit are formed prior to laser-drilling of the opening.
4. The method of claim 2, wherein the opening is formed through a volume of the first die without transistors of the integrated circuit and extends through the entire first die.
5. The method of claim 4, wherein the opening is laser-drilled through the entire first die.
6. The method of claim 1
, further comprising:
forming an oxide layer on surfaces of the opening.
7. The method of claim 6
, further comprising:
forming a metal layer on the oxide layer, the conductive member being plated on the metal layer.
8. The method of claim 7, wherein the metal layer is sputtered and the conductive member is plated on the metal layer.
9. The method of claim 7, wherein the metal layer and the conductive member are of different materials.
10. The method of claim 9, wherein the materials include tantalum nitride and copper, respectively.
11. The method of claim 6
, further comprising:
forming a contact on a contact terminal on the first integrated circuit, the contact interconnecting the contact terminal with the conductive member.
12. The method of claim 11, wherein the contact is screen-printed.
13. The method of claim 1, wherein the conductive member is located on a terminal of the second component.
14. The method of claim 1, wherein a plurality of said openings are formed, a respective conductive member is formed in each opening, and the circuits are connected through the conductive members.
15. The method of claim 1, wherein the second component has a second substrate and the circuit of the second component is a second integrated circuit formed on the second substrate.
16. The method of claim 15
, further comprising:
laser-drilling an opening in at least the second substrate; and
forming a conductive member in the opening in the second substrate.
17. The method of claim 1, wherein the opening is laser-drilled through a volume of the first substrate not designated for the first integrated circuit.
18. A method of constructing an electronic assembly, comprising:
laser-drilling an opening in at least a semiconductor material of a first substrate of a first die having a first integrated circuit formed on the first substrate, the first integrated circuit including a plurality of transistors formed in the semiconductor material of the first substrate;
forming a conductive member in the opening, the conductive member in the opening of the first substrate being electrically connected to at least one of the transistors of the first integrated circuit on the first substrate; and
stacking the first die on a second component having a circuit, at least one of the transistors of the first integrated circuit being connected through the conductive member to the circuit of the second component.
19. The method of claim 18, wherein the opening extends through the entire first die.
20. The method of claim 18, wherein the second component has a second substrate and the circuit of the second component is a second integrated circuit formed on the second substrate, the second circuit including a plurality of transistors.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electronic assembly of the kind having a plurality of integrated circuit dies stacked onto one another, and its manufacture.
2. Discussion of Related Art
In conventional computer assemblies, integrated circuits are “two-dimensionally” connected to one another. Two dies may, for example, be mounted to a common substrate having metal lines that interconnect the integrated circuits of the dies with one another. A “three-dimensional” interconnection scheme may in certain instances be more desirable. Handheld devices may, for example, require a more compact packaging arrangement. In other applications, the metal lines in substrates may inhibit performance. Other applications may also require a three-dimensional interconnection scheme to allow for the design of more sophisticated, three-dimensional logic.
Some techniques for forming contacts on a substrate side of a die are disclosed in U.S. Pat. No. 6,184,060. These techniques are in some respects undesirable, because they require etching of an opening in a die. Etching is relatively slow. Etching also requires many photolithographic steps. All of these factors contribute to limiting throughput.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described by way of example with reference to the accompanying drawings, wherein:
FIG. 1A is a cross-sectional side view through a wafer, illustrating a portion of a die having an integrated circuit formed thereon, and FIG. 1B is a view similar to FIG. 1A after an opening is formed in the wafer;
FIG. 2 is a view similar to FIG. 1B after an oxide layer is formed on a lower surface of the die and within the opening;
FIG. 3 is a view similar to FIG. 2 after a tantalum nitride layer is blanket-sputtered over the oxide layer and onto the metal pad;
FIG. 4 is a view similar to FIG. 3, after the tantalum nitride layer is patterned and a copper conductive member is plated on the tantalum nitride layer;
FIG. 5 is a view similar to FIG. 4 after screen-printing of a contact;
FIG. 6 is a side view of a partially fabricated electronic assembly according to an embodiment of the invention, wherein the die of FIG. 5, another die, and a package substrate are stacked on one another;
FIG. 7 is a view similar to FIG. 6 after heating and cooling of the electronic assembly; and
FIG. 8 is a cross-sectional plan view on 8—8 in FIG. 7.
DETAILED DESCRIPTION OF THE INVENTION
The following description relates to the construction of an electronic assembly by stacking two or more integrated circuit dies on top of one another. An opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a smaller number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.
Referring now to FIG. 1A, a portion of a fabricated wafer is shown, including a die 10 having a silicon substrate 12 and an integrated circuit 14 formed on the silicon substrate 12. The die 10 further includes a contact pad 16 and a passivation layer 18.
The silicon substrate 12 has a lower surface 20 and an upper surface 22. Individual transistors 24 and other electronic components are formed in and on the upper surface 22. The silicon substrate 12 is shown after having been thinned down in a grinding operation from between 425 and 750 microns to approximately 150 microns.
The integrated circuit 14 has alternating dielectric layers 32 and metallization layers 34 that are formed on top of the surface 22. The contact pad 16 and the passivation layer 18 are formed on top of the final interlayer dielectric layer 32. The passivation layer 18 has a periphery that seals with the contact pad 16 and through which an upper surface of the contact pad 16 is exposed.
The contact pad 16 is connected through portions of the metallization layers 34, plugs (not shown), and vias (not shown), to the transistors 24. Signals can thus be transmitted between the transistors 24 and the contact pad 16. The metallization layers 34 are not located in a cylindrical volume 38 below the contact pad 16. There is thus no communication between the contact pad 16 and the transistors 24 in the cylindrical volume 38.
As illustrated in FIG. 1B, an opening 44 is subsequently laser-drilled through the die 10. A triple-pumped Nd:YAG laser having a wavelength of 355 nm is preferably used to laser-drill the opening 44. A laser source of the laser is located above the passivation layer 18, and alignment marks on an upper surface of the die 10 is used to align the laser source with the contact pad 16. Laser light from the laser source then strikes an upper surface of the contact pad 16. The laser light ablates a central portion of the contact pad 16, followed by a central portion of the cylindrical volume 38, followed by a portion in the substrate 12. The opening 44 may be between 25 and 50 microns in diameter. In the case of a small opening such as a 25-micron opening, the opening is typically percussion-drilled. A larger opening such as a 50-micron opening may require circular movement of the laser light about a final center line of the final opening 44. Such circular motion is generally referred to in the art as “trapan” movement.
As shown in FIG. 2, an oxide layer 48 is deposited on the die 10. The oxide layer 48 is blanket-deposited so that it covers the lower surface 20 and side surfaces of the opening 44.
As illustrated in FIG. 3, a tantalum nitride layer 56 is subsequently blanket-deposited on the oxide layer 48. The tantalum nitride layer 56 forms on side surfaces of the opening 44 and on a lower surface of the oxide layer 48. The oxide layer 48 provides a surface onto which the tantalum nitride layer 56 can easily be sputtered, and also provides electrical insulation between the tantalum nitride layer 56 and the surrounding silicon. Techniques exist in the art for sputtering tantalum nitride on oxide within openings such as the opening 44.
FIG. 4 illustrates the structure of FIG. 3 after the tantalum nitride layer 56 is patterned and a copper conductive member 60 is formed. The tantalum nitride layer 56 is patterned by forming a mask over portions of the tantalum nitride layer 56 within the opening 44, and also over a circular portion thereof surrounding the opening 44 on a lower surface of the oxide layer 48. Other portions of the tantalum nitride layer 56 are removed, whereafter the mask is removed. The tantalum nitride layer 56 forms a circular contact pad 62 on a lower surface of the oxide layer 48.
The copper conductive member 60 is plated on the remaining tantalum nitride layer 56. The tantalum nitride layer 56 acts as a seed layer for forming the conductive member 60. Because the opening 44 extends all the way through the die 10, a plating solution can easily be introduced into the opening 44. The tantalum nitride layer 56 also acts as a barrier layer, preventing migration of copper from the conductive member 60 into the silicon of the substrate 12.
Plating is continued until the opening 44 is filled with a portion 64 of the conductive member 60 and until the conductive member 60 forms a bump 66 on the contact pad 62. The portion 64 forms a via extending all the way through the integrated circuit 14 and the substrate 12. The bump 66 has a lower surface 68 standing proud of the lower surface of the oxide layer 48. What should be noted is that the portion 64 is still electrically disconnected from the contact pad 16 and from the metallization layers 34.
As illustrated in FIG. 5, a contact 70 is subsequently screen-printed on the die 10. A lower surface of the contact 70 has a central region that is in contact with an upper end of the portion 64 of the conductive member 60. An annular outer region of the contact 70 is in contact with the contact pad 16. The contact pad 16 is thereby electrically connected through the contact 70 to the conductive member 60. A signal can now be transmitted between the bump 66 and the contact pad 16.
FIG. 6 illustrates a partially assembled electronic assembly 72, including the die 10. The die 10 includes a plurality of bumps 66 manufactured in a similar manner. The die 10 includes a plurality of the contact pads 16 of FIG. 5, and a respective contact 70 is plated on each one of the contact pads 16.
The electronic assembly 72 also includes another die 110 and a package substrate 200. The die 110 may be manufactured in exactly the same way as the die 10. It may also be possible that the dies 10 and 110 are exactly the same in all respects. The dies 10 and 110 may, for example, be identical memory dies. Alternatively, the dies 10 and 110 may differ from one another and may even be from different manufacturers. One die may, for example, be a processor, and the other die a memory die. What should be noted is that the die 110 also includes bumps 170 and 160 at the top and the bottom, respectively. The bumps at the top may not be necessary, and merely assist in alignment during subsequent reflow. The die 10 is stacked on the die 110, and a respective one of the bumps 66 is positioned on a respective one of the bumps 170. The package substrate 200 has a plurality of contact terminals 210 on an upper surface thereof. Each one of the bumps 160 is positioned on a respective one of the contact terminals 210.
FIG. 7 illustrates the electronic assembly 72 of FIG. 6 after being processed through a reflow furnace. The electronic assembly 72 is heated so that the bumps 66, 170, and 160 melt, and are subsequently cooled. The bumps 66 thereby attach to the bumps 170 to form interconnects 300. The interconnects 300 structurally attach the die 10 to the die 110. The interconnects 300 also electrically connect the integrated circuit of the die 10 with the integrated circuit of the die 110. Other bumps 160 attach the die 110 to the package substrate 200 and interconnect the integrated circuit of the die 110 with metallization layers in the package substrate 200.
As illustrated in FIG. 8, the interconnects 300 are in an array of rows and columns. A typical array may, for example, have ten rows and eight columns. Although only the interconnects 300 are shown in FIG. 8, it will be understood that an array of conductive members such as the conductive member 60 shown in FIG. 5 are formed in an array which corresponds to the array of the interconnects 300.
Laser-drilling of the opening 44 allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening 44 is laser-drilled from an upper surface of the upper die 10 all the way through the die 10, which allows for the use of alignment marks on an upper surface of the upper die 10.
An additional benefit of the electronic assembly 72 is that the die 10 provides the structural interconnection benefits of a flip-chip die, while providing the thermal benefits of a wire-bonded die. Because the integrated circuit 14 is at the top, it can be more easily cooled with a heat sink closer to the active circuitry than in a conventional flip-chip application. However, because the die 10 is structurally and electrically connected through an array of bumps 66, the structural and electrical benefits of a flip-chip application are achieved. A further advantage of having conductive members on vias in the silicon below the integrated circuit is that they are more thermally conductive than the silicon and assist in dissipation of heat.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.
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| || |
|U.S. Classification||29/852, 257/E21.597, 29/846, 257/E25.013, 257/E23.011|
|International Classification||H01L21/768, H01L25/065, H01L23/48|
|Cooperative Classification||H01L2225/06589, H01L2225/06513, H01L25/50, H01L21/76898, H01L25/0657, H01L2225/06541, H01L23/481, H01L2225/06517|
|European Classification||H01L25/50, H01L21/768T, H01L25/065S, H01L23/48J|
|Oct 24, 2012||SULP||Surcharge for late payment|
Year of fee payment: 7
|Oct 24, 2012||FPAY||Fee payment|
Year of fee payment: 8
|Sep 17, 2012||REMI||Maintenance fee reminder mailed|
|Jul 29, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Jul 8, 2002||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SWAN, JOHANNA M.;NATARAJAN, BALA;CHIANG, CHIEN;AND OTHERS;REEL/FRAME:013054/0215;SIGNING DATES FROM 20020605 TO 20020619
Owner name: INTEL CORPORATION 2200 MISSION COLLEGE BLVD.SANTA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SWAN, JOHANNA M. /AR;REEL/FRAME:013054/0215;SIGNING DATES FROM 20020605 TO 20020619