|Publication number||US6852549 B2|
|Application number||US 10/273,200|
|Publication date||Feb 8, 2005|
|Filing date||Oct 17, 2002|
|Priority date||May 28, 2002|
|Also published as||US20030224537|
|Publication number||10273200, 273200, US 6852549 B2, US 6852549B2, US-B2-6852549, US6852549 B2, US6852549B2|
|Inventors||San-Yuan Chen, Chia-Liang Sun, Albert Chin|
|Original Assignee||National Chiao Tung University|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Classifications (28), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a method of manufacturing a semiconductor, and more particularly to a transistor with a metal/ferroelectric thin film/insulator/semiconductor (MFIS) gate capacitor structure.
The present silicon memory devices can be sorted by the storage state of the data. One type of the silicon memory devices is the random access memory (RAM), such as DRAM and SRAM. This type of memory device with data reading/writing speed below several ten nanoseconds is generally called quick-access memory. However, the data saved therein will disappear while the power is shut down. Therefore, the storage state of the RAM is volatile. Another type is the read only memory (ROM), such as electrical erasable programmable read only memory (EEPROM) and flash memory. On the contrary, this type of memory device can save the data permanently but has longer reading/writing speed than the RAM. Because the data do not disappear while the power is shut down, the storage state of the RAM is nonvolatile.
Although the current memory devices all have high density (>64 Mbit), the important properties, non-volatility and quick speed, cannot be performed at the same time. Since the demand for ferroelectric random access memory (FRAM) consisting these two merits becomes urgent.
The FRAM has the same speed in reading/writing data with the conventional RAM, so it belongs to the quick-access memory. When writing data, the ferroelectric film is polarized permanently by a electrical pulse so that the data written in is saved forever even that the power is shut down. Therefore, the FRAM is a non-volatile memory device with quick and non-disappeared properties. Moreover, the design of ROM+RAM can be replaced by one FRAM and then the efficiency will be promoted greatly.
Principle of non-volatile ferroelectric memory device for application is using the polarization-electric field (P-E) hysteresis of the ferroelectric film. Because the ferroelectric film has remnant polarization while no external electric field exists, the data do not disappear when shutting down the power. In the practical application, the ferroelectric film capacitor replaces the storage capacitor of SiO2 to distinct the logic “0” and “1” by different remnant polarization (Pr). When the logic is “0”, adding a positive voltage has a difference between Pr and saturation polarization (Ps). While the logic is “1”, the difference is between −Pr and Ps. The current of logic “1” is larger than that of logic “0” so that it is able to be used for determining the data logic.
In the development of the FRAM, how to combine the manufacture process of ferroelectric and silicon integrated circuit is a key point. Especially when the high density memory is developed, the ferroelectric capacitor formed on the gate of the metal oxide semiconductor field-effect transistor (MOSFET) is imperative, so the research in this aspect is extensively noted. In 1950˜1960, scientists use the natural polarization of the ferroelectric ceramics to control (or change) the electric conduction coefficient on the surface of the semiconductor for producing the ferroelectric field-effect transistor memory. Recently, owing to the excellent characteristics of the ferroelectric film, and requirements of both high density G-bite DRAM and non-volatile memory devices so that the FRAM is noted and studied once again.
In view of foregoing reasons, the present invention provides the ultra-thin aluminum oxide to be the insulator for solving charge-injection problem and the material with bismuth layered perovskite structure to be the ferroelectric film due to its non-fatigue behavior and compatibility to the other high-temperature semiconductor process so that excellent memory characteristics can be reached in the MFIS stacked gate capacitor structure.
It is an object of the present invention to provide a production process for manufacturing a bismuth layered ferroelectric film on the ultra-thin aluminum oxide. The single ferroelectric field-effect transistor is produced by the process of the present invention having superior memory property which is due to the ferroelectricity of the ferroelectric film. By appropriately controlling the high-temperature process, the large memory window due to the ferroelectricity and low leakage current are observed in single ferroelectric transistor with a metal/ferroelectric/insulator/Si (MFIS) gate capacitor structure. The low leakage current density matches ULSI device requirement and further the high-temperature process is compatible with CMOS and other post-end semiconductor process.
It is another object of the present invention to provide a method for manufacturing a semiconductor applied to a ferroelectric memory device, including steps of providing an insulator, forming a bismuth ferroelectric film with bismuth layered perovskite structure on the insulator, wherein the bismuth is partially substituted by one of lanthanum and vanadium, treating the insulator and the bismuth ferroelectric thin film at a relatively high temperature, and plating a metal layer on the bismuth ferroelectric film.
Preferably, the insulator is aluminum oxide.
Preferably, the insulator further includes one selected from a group consisting of aluminates, silicides, zirconium oxides, bismuth oxides and a mixture thereof.
Preferably, the insulator is a gate dielectric layer having a relatively high dielectric constant.
Preferably, the insulator is formed by means of sputtering.
Preferably, the insulator is formed by means of metalorganic chemical vapor deposition (MOCVD).
Preferably, the insulator is formed by means of molecular beam epitaxy (MBE).
Preferably, the insulator is formed by means of jet vapor deposition (JVD).
Preferably, the insulator is formed by means of electron beam evaporation and following oxidation process.
Preferably, the bismuth ferroelectric film includes bismuth ion precursors, titanium ion precursors and one of lanthanum ion precursors and vanadium ion precursors.
Preferably, the bismuth ion precursors, titanium ion precursors and one selected from a group consisting of lanthanum ion precursors, vanadium ion precursors and the mixture thereof are at a molar ratio of (4−X):3:X(Bi3+:Ti4+:La3+/V3+), wherein 0<X<1.9.
Preferably, the bismuth layered ferroelectric film is formed by means of spin coating of a chemical solution.
Preferably, the chemical solution is one selected from a group consisting of bismuth acetate, lanthanum acetate, titanium n-butoxide and the mixture thereof dissolving in a mixing solvent of acetic acid and 2-methoxyethanol.
Preferably, the chemical solution includes an metallo-organic precursor and an organic solvent.
Preferably, the metallo-organic precursor is one selected from a group of bismuth, lanthanum and titanium with carbon chains, respectively.
Preferably, the organic solvent is used for dissolving said metallo-organic precursors.
Preferably, the organic solvent includes alcohols and carboxylic acids.
Preferably, the bismuth layered ferroelectric film is formed by means of sputtering.
Preferably, the bismuth layered ferroelectric film is formed by means of pulsed laser deposition (PLD).
Preferably, the bismuth layered ferroelectric film is formed by means of MOCVD.
Preferably, the relatively high temperature is ranged from 600 to 1000° C.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
FIG. 1(a) is a schematic diagram of bismuth titanate ceramic structure according to the prior art.
FIG. 1(b) is a schematic diagram of lanthanum substituted bismuth titanate ceramic structure according to the prior art.
In order to solve the charge injection problem, aluminum oxide layer is used to be the insulator. For testing the application of ferroelectric material in the present invention, the bismuth layer structured ferroelectric is considered and used as the ferroelectric material which chemical formula can be represented as (Bi2O2)2+(Am−1BmO3m+1)2+. The present invention takes Bi3.25La0.75Ti3O12 (m=3) for example, Bi3.25La0.75Ti3O12 (BLT) is used to be the material and produce the capacitor having BLT/Al2O3/Si MFIS structure.
Preparation of Buffer Layer
After dealing silicon substrate cleaned with RCA and treated by hydrofluoric acid vapor, then the metal aluminum is deposited on the surface of the silicon substrate in the electron beam evaporation system to form a metal film with several ten nanometer thereon. After thermal oxidation at 900° C., the aluminum film converts to the aluminum oxide film with thickness below 10 nm.
Preparation of Chemical Solution
Take BLT (Bi4−XLaXTi3O12) for example, dissolving bismuth acetate, lanthanum acetate and titanium n-butoxide in acetic acid and 2-methoxythanol mixture, the molar ratio of Bi3+:La3+:Ti4+ is (4−X):X:3, wherein 0<X<1.9. After the chemical solution is clear, the chemical solution must be stirred at least ten hours to carry out the hydrolysis condensation of the different metallo-organic precursors.
Preparation of Ferroelectric Film
The synthesized chemical solution is spin coated uniformly on the silicon substrate having the insulator thereon by means of rotary plating in 4000 rpm for 30 seconds. After each step of plating gel, the silicon substrate have to remove the organic solvent on hot plate at 400° C. Repeat the above-mentioned steps of coating and drying several times and then raise the temperature to the desired temperature in oxygen atmosphere. Keep the temperature one hour so as to finish the thermal treatment.
FIGS. 1(a) and 1(b) display the structures of bismuth titanate ceramics (Bi4Ti3O12) and lanthanum substituted bismuth titanate ceramics (Bi4−XLaXTi3O12), respectively. As shown in FIG. 1(a), bismuth titanate ceramics have bismuth layered perovskite structure ((Bi2O2)2+(Am−1BmO3m+1)2+). As shown in FIG. 1(b), according to the prior art, the A-sites in the bismuth layered perovskite structure are occupied by lanthanum. Furthermore, because the stability of the lanthanum substituted bismuth layered perovskite structure is improved and the antiphase boundary is formed easily, the BLT ferroelectric film is non-fatigue on the noble metal electrode.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
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|U.S. Classification||438/3, 438/238, 438/199, 257/E29.272, 438/239, 438/399, 438/396, 438/240, 257/E21.272, 257/E29.164, 257/E21.208|
|International Classification||C23C18/12, H01L21/314, H01L29/51, H01L21/28, H01L21/316, H01L29/78|
|Cooperative Classification||H01L21/31691, H01L21/28291, H01L29/78391, C23C18/1216, C23C18/1225, H01L29/516|
|European Classification||H01L29/78K, H01L29/51F, H01L21/316D, C23C18/12E, C23C18/12C2D|
|Oct 17, 2002||AS||Assignment|
Owner name: NATIONAL CHIAO TUNG UNIVERSITY, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, SAN-YUAN;SUN, CHIA-LIANG;CHIN, ALBERT;REEL/FRAME:013413/0632
Effective date: 20021014
|Aug 8, 2008||FPAY||Fee payment|
Year of fee payment: 4
|May 17, 2012||FPAY||Fee payment|
Year of fee payment: 8