|Publication number||US6856420 B1|
|Application number||US 09/631,036|
|Publication date||Feb 15, 2005|
|Filing date||Jul 31, 2000|
|Priority date||Jul 31, 2000|
|Publication number||09631036, 631036, US 6856420 B1, US 6856420B1, US-B1-6856420, US6856420 B1, US6856420B1|
|Inventors||Frederick W. Pew, Marvin D. Nelson|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (3), Referenced by (9), Classifications (15), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
It is well known that many printers include a CPU and a memory management unit (MMU) which are both located on the same integrated circuit (IC). The MMU operates to translate virtual addresses (generated by processes being executed by the CPU) into physical addresses. By using virtual memory, a contiguous range of virtual addresses can be mapped to several non-contiguous areas of physical memory. The phrase “virtual address space” is the range of virtual addresses that is provided by the MMU. Typically, the virtual address space is divided into “virtual pages” which are of a pre-determined size.
Printers often provide for “direct memory access (DMA)” transfers to or from the printer's internal memory. In this context, DMA transfers refer to the process of transferring data (e.g., page description commands describing a document) to or from the printer's internal memory without intervention from the printer's central processor unit (CPU). Instead, the DMA transfers are (typically) implemented by a special purpose controller (referred to as a “DMA” controller) that resides within the printer.
During a DMA transfer, the DMA controller operates as a “bus master”. A bus master refers to a device capable of asserting control over a bus. As part of this function, the DMA controller causes addresses to be placed on the bus to address the printer's internal memory.
Some printers that make use of virtual memory include a DMA controller that only works with physical addresses. This can present a problem, as the printer's internal memory may become fragmented due to contiguous virtual memory addresses being mapped to non-contiguous areas in the physical memory.
One solution to this problem is to constrain each DMA transfer to within a single virtual page. Unfortunately, this solution reduces the amount of data that can be transferred during any one DMA transfer. As a result, multiple DMA transfers may be required to transfer a given amount of data. This is especially disadvantageous for printers (as opposed to other general purpose computers) since printers often perform DMA transfers of relatively large amounts of data which often exceeds the size of a typical virtual page.
Some general purpose computers include DMA controllers that work with virtual memory. An example of such a computer is given in Computer Architecture: a Quantitative Approach, page 527, by David A. Patterson and John L. Hennessy, 2nd ad., ISBN 1-55860-372-7. Typically, this type of DMA controller is provided with an associated set of registers. The registers are used to store a small number of virtual to physical address mappings. Prior to a DMA transfer, the computer's CPU stores the mappings in the register. The mappings are then used by the DMA controller, during a DMA transfer, to translate virtual addresses into physical addresses. Unfortunately, this implementation adds complexity and overhead which is associated with the registers and the operation of the CPU to update these registers prior to each DMA transfer. Implementing this solution in a printer, therefore, results in adding overhead, complexity and therefore cost to the printer.
Briefly, and in general terms, a printer according to a preferred embodiment of the invention includes a first address bus, a second address bus and an address translation unit (ATU). The ATU is coupled to the first and second address buses and is operable to translate virtual addresses received from at least two bus masters connected to the first bus into physical memory addresses and to transmit these physical addresses over the second bus to a memory. One of the bus masters may be a CPU, the other bus master may be a DMA controller.
In another embodiment, a printer is provided that includes a DMA controller operable to generate virtual addresses, a CPU operable to generate virtual addresses and a memory. The printer further includes an address translation unit operable to receive the virtual addresses from both the DMA controller and the CPU and to translate the virtual addresses into physical addresses. The ATU then transmits the physical addresses to the memory.
The present invention may also be implemented as a method of generating physical addresses in a printer. The printer including a CPU, a DMA controller and a memory. The method preferably includes providing an address translation unit (ATU), the CPU transmitting a first plurality of virtual addresses to the ATU, and the DMA controller transmitting a second plurality of virtual addresses to the ATU. The method may further include the ATU generating physical addresses from the virtual addresses received from the CPU and then transmitting these physical addresses to the memory. In addition, the method may further include the ATU generating physical addresses received from the DMA controller and then transmitting these physical addresses to the memory.
The present invention may also be implemented as a computer. The computer includes a DMA controller, a CPU, an ATU and a memory. The address translation unit is operable to receive virtual addresses from both the DMA controller and the CPU, to translate the virtual addresses into physical addresses and to transmit the physical addresses to the memory.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
In addition, and in accordance with the invention, the printer 10 includes an “address translation unit” (ATU) 24. The ATU 24 operates to translate virtual addresses into physical (i.e., actual) memory addresses. As will be discussed in greater detail below, the ATU 14 allows the CPU 12, the first DMA controller 26 and the second DMA controller 27 to all operate in a virtual address space.
As shown, the bus system 22 includes a “virtual” memory bus 30, a “physical” memory bus 32 and a single data bus 34. Each of these two memory buses include respective control lines 38, 42 and address lines 36, 40. As will be described in greater detail below, the virtual memory bus 30 is used as a communication path for virtual addresses. These virtual addresses may be transmitted from the CPU 12, the first DMA controller 26 or the second DMA controller 27 and are received by the ATU 24. The physical memory bus 32 is used as a communication path for physical addresses which are transmitted from the ATU 24.
The CPU 12, the I/O port 14 and the print engine interface 15 are all connected to the virtual memory bus 30. The RAM 18 and the ROM 20 are both connected to the physical memory bus 32. The ATU 24 is connected to both the virtual memory bus 30 and the physical memory bus 32. In addition, the CPU 12, the I/O port 14, the print engine interface 15, the RAM 18 and the ROM 20 are each connected to the data bus 34. The print engine interface 15 is connected to the print engine 16 by a video bus 44. The video bus 44 may be a serial type connection.
The I/O port 14 is used to facilitate DMA transfers of data transmitted from an external host to the RAM 18. This data may represent page description language (PDL) commands that describe a document to be printed. As will be described in greater detail below, the DMA controller 26 operates to direct these DMA transfers.
The CPU 12 is used to execute programs stored in the ROM 20. These programs provide the printer 10 with various control and image processing facilities. For example, one or more of these programs may direct the CPU 12 to process the PDL commands received over the I/O port 14 in order to generate video data. The CPU 12 may also operate to store the video data in the video buffer 28.
The print engine interface 15 is used to coordinate, control and buffer the DMA transfer of video data from the video buffer 28 to the print engine 16 during the printing of a document. Importantly, during this operation, the second DMA controller 27 directs the DMA transfer of the video data over the data bus 34. Additionally, the print engine interface 15 transmits the video data over the video bus 44 to the print engine 16.
It is noted that the first DMA controller 26, the second DMA controller 27 and the CPU 12 can operate as a bus master over the virtual memory bus 30 in order to write or read data from the RAM 18.
Importantly, the function of the ATU 24 is to allow the CPU 12, the first DMA controller 26 and the second OMA controller 27 to operate in a virtual address space. To accomplish this, the ATU 24 operates to map virtual addresses transmitted over the virtual memory bus 30 into physical addresses. Importantly, the virtual addresses may be transmitted from the CPU 12, the first DMA controller 26 or the second DMA controller 27.
After the physical address is generated, the ATU 24 places the physical address, along with appropriate control signals, on the physical memory bus 32. The ATU 24 may also provide various other memory control functions such as memory chip selection and address multiplexing.
In the present embodiment, the ATU 24 includes a translation table 38. The translation table 38 is a single data structure that includes mappings of virtual to physical addresses. Importantly, the translation table 38 provides mappings for the entire virtual address space available in the printer 10. The translation table 38 is maintained by a single firmware program 36 which is shown stored in the ROM 20 and is executed by the CPU 12.
As shown in
Referring now to
From the foregoing it will be appreciated that a printer constructed according to the invention offers numerous advantages. First, both the CPU and the printer's DMA controllers operate in a virtual address space and both have access to the entire virtual address space. This significantly simplifies the operation of these components. Second, the task of mapping the virtual addresses (generated by these components) is now centralized and the mappings are maintained in a single data structure (i.e., the translation table). This significantly simplifies the book keeping task associated with ensuring correct physical addresses are generated. Third, by allowing the DMA controllers to operate with virtual addresses, more efficient use of the RAM can be achieved as DMA transfers can be mapped into non-contiguous areas of the RAM.
It is further noted that the present invention may also be embodied in the form of a program storage medium with computer readable program code embodied therein that represents the ATU firmware. In the context of this document, “program storage medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus or device. The program storage medium can be, for example (the following is a non-exhaustive list), a magnetic, optical, or semiconductor based storage device.
Although a specific embodiments of the invention has been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. For example, the invention has been shown to have particular applicability to a printer. The invention, however, may be used to improve other types of computing systems. Therefore, the invention is limited only by the claims and equivalents thereof.
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|US7854518||Jun 16, 2006||Dec 21, 2010||Hewlett-Packard Development Company, L.P.||Mesh for rendering an image frame|
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|U.S. Classification||358/1.16, 711/206, 358/1.17, 711/203, 710/9, 710/110, 711/209|
|International Classification||G06F12/10, G06K15/02, G06K1/00, G06F15/00, G06F3/12, B41J5/30|
|Nov 9, 2000||AS||Assignment|
|Sep 30, 2003||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY L.P.,TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:014061/0492
Effective date: 20030926
|Aug 15, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Oct 1, 2012||REMI||Maintenance fee reminder mailed|
|Feb 15, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Apr 9, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130215