|Publication number||US6857029 B2|
|Application number||US 10/137,084|
|Publication date||Feb 15, 2005|
|Filing date||Apr 30, 2002|
|Priority date||Apr 30, 2002|
|Also published as||US20030204650|
|Publication number||10137084, 137084, US 6857029 B2, US 6857029B2, US-B2-6857029, US6857029 B2, US6857029B2|
|Inventors||Jaya Prakash Subramaniam Ganasan, Adger Erik Harvin, III, Richard Gerard Hofmann, Perry Willmann Remaklus, Jr.|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Non-Patent Citations (1), Referenced by (10), Classifications (9), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to system on chip (SOC) designs and specifically to monitoring bus performance on such designs.
Circuit designs are typically system level designs on a system on chip (SOC). In system level designs board-level bus analysis is usually accomplished through the use of connectors and cables which attach to the system bus, allowing devices (such as logic analyzers, digital oscilliscopes, etc.) to sample bus transactions over a given time period. As system-level board designs have migrated to system on chip (SOC) designs, there should exist a similar mechanism to perform at speed on-chip bus performance analysis.
There are two conventional approaches to accomplishing a similar task:
However, for this mechanism to attach to all of the necessary internal signals and allow full flexibility in the types of bus monitoring that can be performed, the design could become quite large. As SOC designs are starting to utilize more die area, fitting such an oversized design block into the SOC layout becomes quite a challenge for placement and wiring, especially where contiguous whitespace is virtually nonexistent. Another problem would be that a design of such a large fixed-size mechanism does not lend itself well to implementations in larger SOC designs where bus traffic from a few additional devices may require monitoring. This limits the mechanism's scalability, possibly requiring a redesign of the performance-monitoring mechanism specifically for designs where functionality may have increased.
Accordingly, what is needed is a system and method for monitoring bus activity in an SOC that is scalable and does not add significantly to the die size or cost with the SOC. The present invention addresses such a need.
A bus performance monitoring mechanism system on chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave devices, a plurality of generic signals and a plurality of control signals. The monitoring mechanism includes a plurality of control registers coupled to the muxing logic to allow for the selection of master, slave, generic and pipeline stage events to be counted. Finally, the monitoring mechanism includes synchronizing logic coupled to the plurality of registers for providing and receiving synchronizing signals to and from the monitors coupled thereto to allow for scalability.
The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a “lego-like” fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique. For these designs where multiple monitor instances may be required, this enhances wireability by allowing the SOC designer to scatter the monitor instance locations virtually anywhere within the smaller areas of unused chip space, and simply wire the synchronization signals among the monitor instances to allow for synchronous operation.
FIG. 3 and
The present invention relates generally to system on chip (SOC) designs and specifically to monitoring bus performance on such designs. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
An on-chip bus performance mechanism in accordance with the present invention is scalable for accommodating larger SOC designs. A bus performance monitoring mechanism in accordance with the present invention tracks the occurrence and/or duration of events associated with on-chip bus transactions. Events are tracked on a per master and/or per slave basis, and can be selectably isolated in accordance with user definable qualifications. The measurements which can be performed include: bus signal occurrence measurements, data-bus tenure, and address pipeline measurements. These measurements provide a means for systems designers to assess the performance of the SOC and also provide a mechanism for performing both hardware and software debugging for chip-level problem analysis.
A bus performance monitoring mechanism in accordance with the present invention has the following features.
Interrupt logic 110 also receives signals from cycle counter 108. The PLB signals are provided to a pipeline tracker 120 which in turn provides signals to a plurality of generic counters 116. Generic inputs are also provided to the plurality of generic counters 116. The plurality of generic counters 116 also provide input to the sync logic 102 as well as to the interrupt logic 110. The plurality of duration counters 118 also receive a signal from the muxing logic 106.
The bus performance monitoring mechanism 100 performs in the following functions. Muxing logic 106 simultaneously connects up to a plurality (i.e., eight) of PLB masters, a plurality (i.e., eight) of PLB slaves, and a plurality (i.e., four) of generic signals. Control registers 104 allow for the selection of master, slave, generic and pipeline-stage events to be counted.
The pipeline tracker 120 simultaneously tracks events from up to four PLB masters, up to four PLB slaves and either four pipeline-stage events or four external generic events. Configuration bits are within the control registers 104 for selecting priority matching, address matching, transfer-size matching, and/or read/write matching, allowing finer granularity when tracking certain PLB master events. Configuration bits are also within the control registers 104 for selecting Master ID matching also allow finer granularity when tracking certain PLB slave events. There are also separate duration counters 118 for tracking the minimum duration value, maximum duration value, total duration value, and the event occurrence totals of PLB-slave-related-transactions. The two sets of duration counters 118 allow concurrent tracking of up to two duration-events associated with any of the plurality of slaves.
The pipeline-depth tracker 120 provides for independent monitoring of hits-per-pipeline depth level of both read and write data buses. The pipeline tracker supports PLB implementations having a read-pipeline depth no greater than four, and a write-pipeline depth no greater than two. Finally, variable power consumption modes are handled by the mux logic 106 to allow the mechanism to be placed into different levels of inactivity.
The architecture of a full embodiment of this design is small enough to allow multiple monitor instances to coexist in a single system-on-chip (SOC) layout. Each embodiment allows for simultaneous monitoring of events from up to 8 PLB masters, 8 PLB slaves, and 4 extra non-PLB signals. Each could be wired to monitor the signals (and events) from the same PLB masters and slaves, or wired to receive signals (events) from a different set of PLB masters and slaves. This allows greater flexibility for SOC designs to monitor larger sets of events across larger designs. Examples are illustrated in the following diagrams, where, for example, Mn and S1n represent CoreConnect PLB Master and PLB slave devices, respectively.
The small scalable design structure also allows ease in placement and wiring within SOCs where contiguous spatial area is limited. Each monitor instance could be placed where a minimal space is available, possibly across chip from other monitor instances. An SOC design utilizing a “crossbar” type of PLB bus configuration is a good example where the scalability feature can be shown.
Synchronization and Triggering Description
In SOC designs requiring multiple monitor instances of the scalable on-chip performance monitoring synchronization mechanism to be implemented, there could exist a means of either allowing each monitor instance to function either independently or synchronously with one another. With each monitor instance having a sync-in and a sync-out signal port, the monitor instances can be easily connected allowing sychronization. Examples of chip-level sync wiring among monitor instances are described below.
Within the monitoring architecture as described in this disclosure there exists a feature for “staggered-sample-triggering”. This feature allows a primary monitor instance to activate its sync_out signals, after it has completed its currently selected measurement(s). Should multiple monitor instances be required within an SOC layout, this feature allows subsequent (secondary) monitor instances to be programmed to start functioning only after its primary monitor instance has completed performing its measurement (as defined in its controlling registers). This feature is similar to that of a logic analyzer apparatus in that special triggering schemes can be performed to measure the “hard-to-find” bus-related transactions.
The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a “lego-like” fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
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|U.S. Classification||710/15, 710/110, 710/18, 702/186, 710/107, 702/182|
|Jun 19, 2002||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GANASAN, JAYA PRAKASH SUBRAMANIAM;HARVIN, ADGER ERIK;HOFMANN, RICHARD GERARD;AND OTHERS;REEL/FRAME:012812/0141
Effective date: 20020522
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