|Publication number||US6885529 B2|
|Application number||US 09/942,785|
|Publication date||Apr 26, 2005|
|Filing date||Aug 31, 2001|
|Priority date||May 29, 2001|
|Also published as||US20020181177|
|Publication number||09942785, 942785, US 6885529 B2, US 6885529B2, US-B2-6885529, US6885529 B2, US6885529B2|
|Inventors||Ming-Dou Ker, Hun-Hsien Chang, Wen-Tai Wang|
|Original Assignee||Taiwan Semiconductor Manufacturing Co., Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (30), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates in general to a charged-device-model (CDM) electrostatic discharge (ESD) protection device, and especially to a CDM ESD protection device using deep N-well structure.
2. Description of the Related Art
ESD protection circuits are generally known to protect integrated circuits (IC) from machine model (MM) or human body model (HBM) electrostatic discharge events. In an HBM or MM mode electrostatic discharge event, electrostatic charges enter the IC through some of the IC pins and exit through others. To protect IC from such ESD events, an ESD protection circuit is often disposed adjacent to the output or input pad of the IC circuit to discharge the ESD stress. As the conventional ESD protection circuit shows in
Apart from the HMB and MM ESD events described, another ESD type referred to is charged-device model (CDM). In a CDM ESD event, electrostatic charges are stored in a floating IC substrate and are discharged via the momentarily grounded pins. Unlike HBD or MM ESD events, the ESD charges of a CMD ESD event are stored in the IC substrate, not relying on an external source. For instance, electrostatic charges accumulate in the IC via friction generated during IC conveyance. When one or more pins of the IC are momentarily grounded to a grounded platform, the electrostatic charges are discharged through the grounded pins.
The schematic diagrams of IC with the positive and the negative charges in a floating substrate are respectively shown in
CDM ESD stress often breaks through the gate oxide layers of input buffers. The substrate is filled with a substantial amount of electrostatic charges which transiently cause overstress and breakdown of the gate oxide of the input buffers. IESD in
A conventional method solves the problems caused by CDM ESD events by adding a small gate-grounded NMOS bedside the gate of the input buffer. The ground line VSS connected to the small gate-grounded NMOS is also the ground line of the input buffer as shown in
The other conventional method to solve the CDM ESD problem is to dispose the input buffer beside the pad so that the gate oxide of input buffer is protected by the HMB/MM ESD protection circuit near the pad. However, this will increase the layout complexity of the circuit around the pad.
In U.S. Pat. No. 5,901,022, an inductor is added between the input pad and the HBM/MM ESD protection circuit to clamp the CDM ESD stress across the gate oxide of the input buffer.
In U.S. Pat. No. 5,729,419, a CDM ESD protection circuit is proposed for the output buffer to clamp the voltage across the gate oxide of the output buffer.
An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type; the second conductivity type is the reversed polarity of the first conductivity type; and the isolating region has isolated the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage.
The first and the second conductivity types can be either N type or P type.
The ESD clamp device can be a two-stage HBM ESD protection circuit. The functional component can be an MOS component of either an input buffer or a output driver. The isolating region having the second conductivity type comprises a second well surrounding the first well and a deep well under the first well.
The first well and the substrate are isolated by the deep well of the reversed conductivity type.
The electrostatic charges accumulated in the first well are much lower than those accumulated in the substrate. During an ESD event, the substantial amount of electrostatic charges isolated by the isolating well are discharged through the ESD clamp circuit to the pad, not through the functional component. The electrostatic charges in the first well are too few to damage the functional component. Therefore, the functional component is less susceptible to damages caused by CDM ESD.
The present invention provides another CDM ESD protection circuit for an input buffer of an IC. The ESD protection circuit comprises: an ESD clamp device and an MOS component.
The ESD clamp device is coupled to a pad and a substrate having the first conductivity type. Under normal power operation, the ESD clamp device is closed. The MOS component is a second conductivity type, formed in a first well on the substrate and having a gate coupled to the pad. An isolating region having the second conductivity type is formed between the first well and the substrate to separate the two; and the second conductivity type is the reversed polarity of the first conductive type. Under normal power operation, the MOS component transmits a signal from the pad into the IC.
The present invention further provides a CDM ESD protection circuit for an output port of an IC. The ESD protection circuit comprises: an ESD clamp device and an MOS component. The ESD clamp device is coupled to a pad and a substrate having the first conductivity type. Under normal power operation, the ESD clamp device is closed. The MOS component is a second conductivity type, and is formed in a first well on the substrate and coupled to the pad. An isolating region having the second conductivity type is formed between the first well and the substrate to separate the first well and the substrate; the second conductivity type is the reversed polarity of the first conductive type; under normal power operation, the MOS component transmits a signal from the IC to the pad.
The present invention yet provides a CDM ESD protection circuit, suitable for an I/O port of a mixed-voltage IC. The CDM ESD protection circuit comprises: an ESD clamp device, first NMOS (N-type metal-on-semiconductor) component, and an output driver. The ESD clamp device is coupled between a pad and a p-type substrate. Under normal power operation, the ESD clamp device is closed. The first NMOS component is formed on a first isolated well. An isolating region is formed to separate the first isolated well and the substrate; the first NMOS component has a gate coupled to a high power line, a first source/drain coupled the pad, and a second source/drain coupled to an input buffer. The output driver comprises a second and a third NMOS components respectively formed in a second isolated well on the P-type substrate and connected in series. An N-type first isolating region is formed between the second isolated well and the P-type substrate; a gate of the second NMOS component is coupled to the high power line, a drain of the second NMOS component is coupled to the pad, a source of the second NMOS component is coupled to a drain of the third NMOS component; a source of the third NMOS component is coupled to an I/O low power line, and a gate of the third NMOS component is coupled to a pre-output driver.
The advantage of the present invention is that by using an isolating region, most of the significant electrostatic charges stored in the substrate are discharged through the ESD clamp circuit, rather than through the functioning component, to the pad. Additionally, the electrostatic charges in the first well is too few to damage the gate oxide of the functioning component.
As technology of deep sub-micron CMOS advances, IC products often have high-integration circuit blocks, such as embedded dynamic random-access-memory (DRAM)or mixed-mode circuits (analog circuit blocks). In order to maintain the circuit performance of the embedded DRAM or mixed-mode (analogue) circuits, or to reduce noise coupling through common p-type substrate, a deep N-well structure is often added into the CMOS processes to meet the required circuit specifications. Especially, the memory cells of the embedded DRAM are placed in a stand-alone p-well region which is isolated from the common p-type substrate by a deep N-well structure. The common p-type substrate is generally biased at 0V (ground) for most of the applications. With the addition of the deep N-well structure, the stand-alone p-well region can be biased with a negative voltage level to reduce the leakage current of the switch MOS in the memory cell. In the mixed-mode circuit, the high-resolution circuit performance of the analog circuits is easily disturbed by noises generated from the digital logic blocks. With the additional deep N-well structure in the CMOS technology, the NMOS devices of analog circuits are placed at the isolated p-well region, which is isolated from the noisy common p-substrate. Therefore, the deep N-well structure has been generally included into the sub-micron CMOS process to support the IC design for high-integration applications.
The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:
With the additional deep N-well structure as described in the prior art, an ESD protection design for overcoming the CDM ESD events is proposed in this invention. An ESD protection design using a deep N-well for overcoming CDM ESD events is proposed in the present invention. A cross-section of the NMOS component placed in an isolated p-well region with the deep N-well structure and the symbol thereof is shown in FIG. 7. The symbol shown in the right-hand side of the
With the deep N-well design in
Similarly, in the output circuit in
Cross-sections of Mn6 and Mn7 are shown in FIG. 10. Mn7 is formed in a P-well 80 connected to the common P-substrate 82. Mn6 is placed in a stand-along P-well 84 surrounded by a normal N-well 86 at the side and a deep N-well 88 at the bottom to be isolated from the common P-substrate 82. If the CDM charges stored in the P-substrate 82 are discharged via Mn6 component, the discharge path is: the P-substrate 82, the deep N-well 88, the stand-along P-well 84 and Mn6 component. The P-N junction between the P-substrate 82 and the deep N-well 88 or between the deep N-well and the stand-along P-well 84 has a great breakdown voltage of 20˜40V in the general deep sub-micron CMOS technologies. If the CDM charges stored in the P-substrate 82 are discharged from Mn7, the discharge path is: the P-substrate 82, the p-well 80 and Mn7 component. The breakdown voltage of the P-N junction between the P-well 80 and the N+ diffusion drain 90 is only about 8˜15V in the general deep sub-micron CMOS technologies. Therefore, the CDM charges stored in the P-substrate 82 are discharged from the ESD clamp component Mn7 rather than the functional component Mn6. The CDM charges and the discharge path thereof (by bold line) are shown in FIG. 11. Although the stand-along P-well 84 has some CDM charges 62, the amount of the CDM charges 62 in the stand-along P-well 84 of Mn6 is much smaller than those stored in the common P-substrate 82. The stand-along P-well 84 has a junction depth of about ˜2 μm, but the P-substrate 82 has a thickness of 500˜600 μm. The stand-along P-well 84 has a much smaller silicon area compared to the whole P-substrate 82 of the chip. Therefore, the CDM charges in the P-substrate 82 have a much greater amount than those in the stand-along P-well 84. By using the deep N-well structure, the CDM charges are mostly stored in the P-substrate 82, which is discharged through the ESD clamp component Mn7 to the pad 64 as shown in FIG. 11.
The CDM ESD discharge current path of the input ESD protection device in
The proposed CDM ESD protection design with deep N-well structure can also be applied to a mixed-voltage circuit. A typical 3V/5V-tolirant I/O circuit is shown in
To improve the CDM ESD level in a more complex design, such as the mixed-voltage I/O circuit, the deep N-well structures are added to the functional components to block their P-well regions away from the common P-substrate. The application of this invention on the 3V/5V-tolerant I/O circuit is shown in
The proposed CDM ESD protection method is illustrated in
Finally, while the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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|U.S. Classification||361/56, 361/111|
|International Classification||H02H3/22, H02H9/00, H01L27/02, H01L23/60|
|Aug 13, 2001||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LIMITED, T
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KER, MING-DOU;CHANG, HUN-HSIEN;WANG, WEN-TAI;REEL/FRAME:012142/0368;SIGNING DATES FROM 20010723 TO 20010731
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