|Publication number||US6888218 B2|
|Application number||US 09/974,023|
|Publication date||May 3, 2005|
|Filing date||Oct 10, 2001|
|Priority date||Oct 2, 1998|
|Also published as||EP1123565A1, EP1123565B1, US20020048927, WO2000021133A1|
|Publication number||09974023, 974023, US 6888218 B2, US 6888218B2, US-B2-6888218, US6888218 B2, US6888218B2|
|Inventors||Dennis R. Kling, Christopher D. Cotton, Bruce W. Chignola|
|Original Assignee||The Raytheon Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (7), Classifications (14), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. patent application Ser. No. 09/410,328 filed on Oct. 1, 1999 now abandoned, which claims the benefit of Provisional application Ser. No. 60/102,871, filed Oct. 2, 1998. The contents of the aforementioned application is hereby incorporated by reference.
The invention relates to systems and methods for interconnecting circuit devices, and more particularly, to systems and methods for providing multi-chip module (MCM) devices having reduced transmission noise on the power and ground planes.
High performance mixed signal A/D circuits require improved power distribution and decoupling as compared with conventional circuit devices. In addition, the inductive and capacitive parasitic losses present in conventional single chip packaging and surface mount technology dictate that many new high performance circuit designs be implemented using multi-chip module (MCM) packaging technologies.
A multi-chip module (MCM) is a single electronic package containing more than one IC. An MCM combines high performance ICs with a custom-designed common substrate structure which provides mechanical support for the chips and multiple layers of conductors to interconnect them. This arrangement takes better advantage of the performance of the ICs than does interconnecting individually packaged ICs because the interconnect length is much shorter. The defining characteristic of MCMs is the complex substrate structure that contains the circuit pattern that interconnects the ICs and which is fabricated using multi-layer ceramics, polymers, silicon, metals, glass ceramics, laminates, or other suitable materials.
Multi-Chip Modules (MCMs) offer a way to pack more integrated circuits into a given module surface area. In addition to reducing size, this technology permits increased speed because it shrinks interconnect distances. A typical MCM has bare ICs mounted on a high-density interconnect (HDI) substrate encapsulated within an environmentally-protected package.
Types of MCMs include: MCM-L (laminated PC board), MCM-C (co-fired ceramic), MCM-D (deposited thin film), and MCM-Si (silicon substrate). MCM-C technology is based on ceramic dielectrics, noble metals and thick film processing. MCM-L technology is based on organic dielectrics, plated copper metallization and laminate preceding. MCM-D technology is based on deposited dielectrics, copper or aluminum metallization and thin film processing. More formal definitions for these primary types of MCMs have been established by the Institute for Interconnecting and Packaging Electronic Circuits (IPC). In particular, MCM-L are understood as modules which are constructed of plastic laminate-based dielectrics and copper conductors utilizing advanced forms of printed wiring board (PWB) technologies to form the interconnects and vias. They are commonly called “laminate MCMs”. MCM-C modules are understood as modules which are constructed on confided ceramic or glass-ceramic substrates using thick film (screen printing) technologies to form the conductor patterns using fireable metals. The term “cofired” implies that the conductors and ceramic are heated at the same time. These are also called thick film MCMs. MCM-D modules are understood as modules which are formed by the deposition of thin film metals and dielectrics, which may be polymers or inorganic dielectrics. These are commonly called thin film MCMs.
From the above definitions, it can be understood that MCM-Cs are descended from classical hybrid technology, and MCM-Ls are essentially sophisticated printed circuit boards. On the other hand, MCM-Ds are the result of manufacturing technologies that draw heavily from the semiconductor industry.
The application of MCM technologies for developing high performance, mixed signal circuits aids in addressing the interconnection challenges that arise when developing these devices. The high switching speeds, high bandwidth, and high dynamic range of these circuits require that the power/ground distribution systems provide very low impedance decoupling with very low noise and ripple. The AC and DC loss characteristics of the substrate signal interconnect structure must be low and must provide sufficient signal, power, and ground layers to accommodate both analog and digital power and ground planes. In high speed circuits where substantial current switching is occurring, the decoupling performance is directly affected by the series inductance between the capacitor elements and the power and ground planes. Voltage spikes caused by L*di/dt effects will result in voltage differences in the power and ground planes. Low inductance surface mounted capacitors have been developed, however, electrical simulation results of standard MCM structures with surface mounted low inductance chip capacitors indicate that these structures still behave as LC transmission lines allowing the propagation of waves across the ground plane. Voltage differences of greater than 30 mV were obtained in simulations.
Present commercially available MCM interconnect solutions are comprised of the three basic MCM technologies, MCM-C, MCM-L, and MCM-D. Generally, these technologies rely on surface mounted capacitor chip components to provide decoupling capacitance for the IC devices. Although, this technique can work well, the current switching demands of high speed circuits can still pull sufficient current through the power lines to cause voltage spiking and ground bounce.
A better solution is to distribute the decoupling capacitance by placing the power and ground layers next to each other separated by a thin dielectric layer. This makes the decoupling capacitance integral to the substrate structure and provides the lowest series inductance.
However, in most cases this integral distributed decoupling capacitance is too small to be sufficiently effective due to the relatively low dielectric constants of the dielectric materials being used and the relatively large spacing between the power and ground layers. One specific MCM-D technology, manufactured by nChip Inc. utilizes multi-layer thin film processing with aluminum metallization and SiO2 dielectric fabricated on a silicon substrate. This technology is described in U.S. Pat. No. 5,134,539. However, this MCM-D technology is typically limited to 4 metal layers consisting of 1 power plane, 1 ground plane, and 2 signal layers, and therefore, fails to provide a sufficient number of layers to create an interconnect layer that allows separation of the analog and digital sections for mixed signal application. Additionally, the aluminum metallization applied by this process is more resistive than equivalent copper metallization, and therefore results in RC losses in the signal traces.
Therefore, a need remains in the art as none of the existing interconnect structures provide the features required or desired for high performance mixed signal A/D circuits.
It is an object of the invention to provide improved interconnect systems for high performance circuit devices, including high performance mixed signal A/D circuit devices.
To this end, the invention provides systems and methods for interconnecting circuit devices, wherein decoupling capacitors are disposed on a substrate and an interconnect layer having a pattern of circuit connections is formed by a deposition process over the capacitors, thereby embedding the decoupling capacitors within the interconnect layer. Circuit devices can be mounted to the surface of the deposited interconnect layer at locations that minimize, or substantially minimize, the interconnect length between the chip device and the decoupling capacitors for that circuit device.
More particularly, the systems and methods described herein, in one aspect, include methods for forming an interconnecting substrate comprising providing a support base, disposing on the support base a decoupling capacitor and employing a deposition process to form an interconnect layer over the decoupling capacitor, whereby an interconnecting substrate is formed having an embedded decoupling capacitor. In certain practices, the methods can include the step of forming electrical connections on a surface of the interconnect layer and extending into the interconnect layer, thereby allowing devices to be mounted on the surface of the interconnect layer. The devices can be mounted to the surface of the interconnect layer by wire bond mounting, flip chip mounting or any other suitable technique.
In a particular practice, the act of employing a deposition process to form an interconnect layer can include an act of forming an interconnect layer having a plurality of power and ground planes as well as forming an interconnect layer having a plurality of signal planes. The deposition process can optionally include a process that provides a low loss copper metallization structure having a plurality of metal layers, and separate layers can be provided for analog circuits and digital circuits.
In a further practice, the interconnect layer can be formed over a support base that carries a plurality of decoupling capacitors, wherein the decoupling capacitors are distributed across the support base at locations that are selected to align with circuit devices that are to be disposed on the surface of the interconnect layer. The decoupling capacitors can have a common ground plane and, optionally, can act to provide decoupling capacitance for a plurality of different power planes, at least some of which can be at different voltage levels. In a further practice, resistors, such as terminating resistors, as well as other devices can be disposed on the support base and embedded along with the decoupling capacitors in the interconnect layer that can be deposited over these elements.
In a further aspect, the invention can be understood as multi-chip module devices that comprise a support base, having disposed thereon a decoupling capacitor and an interconnect layer having a pattern of circuit connections contained therein and having the decoupling capacitors embedded within the interconnect layer. A plurality of circuit devices can be mounted to a surface of the interconnect layer and connected electrically with the pattern of circuit connections formed within the interconnect layer. Optionally, resistor elements, such as terminating resistors, can be carried on the surface of the support base and embedded, along with the decoupling capacitors, into the interconnect layer. Other elements and devices can also be embedded within the interconnect layer.
In one particular embodiment, the MCM device can include an interconnect layer that includes a plurality of metal layers which can form the circuit pattern for interconnecting the devices, or at least a portion of the circuit pattern that interconnects the devices. The substrate base can be formed of silicon, polycrystalline silicon, or any other suitable material. The decoupling capacitors can comprise a silicon oxide dielectric, a polyimide dielectric, aluminum oxide, organic material dielectrics, or any other suitable dielectric materials. The dielectric material is disposed between conductive plates, that can be made of aluminum, copper, tungsten, or any other suitable plating. The decoupling capacitors can provide a distributed decoupling capacitance for decoupling power lines carrying power to the circuit devices. The circuit devices can be wire bonded, flip chip mounted, or mounted using any suitable technique onto the surface of the interconnect layer.
Other practices and embodiments of the systems and methods described herein can be modified from the following descriptions.
The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof, with reference to the accompanying drawings wherein;
To provide an overall understanding of the invention, certain illustrative embodiments will now be described. However, it will be understood by one of ordinary skill in the art that the systems described herein can be adapted and modified to provide interconnecting structures and processes for other applications and that other additions and modifications can be made to the invention without departing from the scope hereof.
The systems and methods described herein provide, inter alia, interconnecting devices that can support high performance mixed signal A/D circuits, and in particular can provide the power distribution and decoupling required for the proper operation of such high performance mixed signal A/D circuit devices.
The support base 12 depicted in
The decoupling capacitors 14 depicted in
The depicted interconnect layer 16 can be formed over the decoupling capacitors 14 by a deposition process that forms the power planes, ground planes and interconnect layers on top of circuit components being connected together. One such deposition process is the type provided by EPIC Technologies, Inc. and which is capable of providing a low loss MCM copper metallization structure having six metal layers therein. The process for forming such an interconnect layer 16 follows from principles known in the art of circuit fabrication, including those set forth in U.S. Pat. No. 5,841,193, assigned to EPIC Technologies of Woburn, Mass. However, it will be understood by those of ordinary skill in the art that any other technique suitable for providing an interconnect layer on top of the decoupling capacitors 14 can be practiced. Moreover, it will be understood that the type of process employed for forming the interconnect layer can vary depending on the application, such as the number of layers needed, whether multiple separate power planes are required, and other such criteria.
For both capacitors 36 and 44, the top surface comprises a plurality of pads each of which can be employed for forming an electrical connection with the interconnect layer 16 that can be formed over these decoupling capacitors. Turning to
By way of example, the decoupling capacitor 30 can provide a relatively high capacitance decoupling structure, in the range of 1 to 1000 nf/cm2, and more particularly, in the range of about 50 nF/cm2, formed between the power and ground layers. Thus the circuit devices 20 can be connected over the short interconnect paths to a decoupling capacitance capable of reducing voltage spikes, cross-talk and signal noise.
Turning back to
The above described embodiments have been described as having MCM modules. However, it will be understood that the systems and methods described herein are not to be limited to systems and methods that include MCM packaging technologies, and that many IC packaging technologies can be practiced with the systems and methods described herein. For example, the systems and methods described herein can be practiced with any packaging technology that supports packaging efficiency, chip population, and I/O density can be employed herewith, and in particular, any packaging technology that provides a dense conductor matrix for the interconnection of bare IC chips, can be employed, including packaging technologies that support High Density Interconnect (HDI) modules.
Those skilled in the art will know or be able to ascertain using no more than routine experimentation, many equivalents to the embodiments and practices described herein. Accordingly, it will be understood that the invention is not to be limited to the embodiments disclosed herein, but is to be understood from the following claims, which are to be interpreted as broadly as allowed under the law.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4890192 *||Apr 9, 1987||Dec 26, 1989||Microelectronics And Computer Technology Corporation||Thin film capacitor|
|US5274270 *||Jan 22, 1993||Dec 28, 1993||Nchip, Inc.||Multichip module having SiO2 insulating layer|
|US5841193 *||May 20, 1996||Nov 24, 1998||Epic Technologies, Inc.||Single chip modules, repairable multichip modules, and methods of fabrication thereof|
|US5973910 *||Dec 13, 1995||Oct 26, 1999||Intel Corporation||Decoupling capacitor in an integrated circuit|
|JPH06295981A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7247932 *||May 19, 2000||Jul 24, 2007||Megica Corporation||Chip package with capacitor|
|US7919804||Dec 1, 2006||Apr 5, 2011||Oracle America, Inc.||Power distribution for high-speed integrated circuits|
|US8148806||Nov 12, 2008||Apr 3, 2012||Megica Corporation||Multiple chips bonded to packaging structure with low noise and multiple selectable functions|
|US8581395 *||Jun 14, 2012||Nov 12, 2013||Renesas Electronics Corporation||Hybrid integrated circuit device and electronic device|
|US20070102806 *||Dec 1, 2006||May 10, 2007||Sun Microsystems, Inc.||Power distribution for high-speed integrated circuits|
|US20090296310 *||Dec 3, 2009||Azuma Chikara||Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors|
|US20120248630 *||Jun 14, 2012||Oct 4, 2012||Renesas Electronics Corporation||Hybrid integrated circuit device, and method for fabricating the same, and electronic device|
|U.S. Classification||257/532, 257/E23.173, 257/533|
|International Classification||H01L23/538, H05K1/02, H05K1/18|
|Cooperative Classification||H01L2924/0002, H01L2924/3011, H01L23/5383, H05K1/0231, H05K1/185, H01L2924/09701|
|European Classification||H05K1/18C6, H01L23/538D|
|Oct 17, 2008||FPAY||Fee payment|
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|Sep 28, 2012||FPAY||Fee payment|
Year of fee payment: 8