|Publication number||US6888420 B2|
|Application number||US 10/407,056|
|Publication date||May 3, 2005|
|Filing date||Apr 3, 2003|
|Priority date||Nov 14, 2002|
|Also published as||US20040095205, WO2004047216A2, WO2004047216A3|
|Publication number||10407056, 407056, US 6888420 B2, US 6888420B2, US-B2-6888420, US6888420 B2, US6888420B2|
|Inventors||James H. Schaffner, Robert Y. Loo|
|Original Assignee||Hrl Laboratories, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Referenced by (23), Classifications (9), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The application claims the benefit of U.S. Provisional Application No. 60/426,672 filed on Nov. 14, 2002, the contents of which are incorporated herein by reference in their entirety.
The present invention relates to an apparatus for switching multiple electrical inputs to multiple electrical outputs. More particularly, the present invention relates to a broadband RF micro electromechanical system (MEMS) switch matrix that can be scaled to a matrix size of M×N, where M comprises the number of RF input ports and N comprises the number of RF output ports.
2. Description of Related Art
The routing of RF signals may be accomplished by using a switching matrix. A switching matrix may be configured to map M signal input ports into N signal output ports. Switching matrices are found in many signal routing situations such as communications base-stations, switched beam antennas, or telecommunications transfer switches.
Various methods and devices are known in the art for providing switch matrices that allow M inputs to be switched to N outputs. U.S. Pat. No. 4,399,439, issued Aug. 16, 1983 to L. C. Upadhyayula, describes an M by N switch matrix comprising M single pole input switches, each input switch having N throws, connected to N single pole output switches, each output switch having M throws. A total of M times N interconnects are required to connect the input switches to the output switches. Upadhyayula further discloses that the input and output switches may be fabricated from GaAs MESFET transistors to provide for switches useful at microwave frequencies. However, those skilled in the art would understand that scaling the Upadhyayula apparatus to a larger number of inputs and/or outputs would increase the size and complexity of the individual input and output switches and the size and complexity of the apparatus overall.
M by N switch matrices may be provided by multiple crossbar switches. U.S. Pat. No. 5,696,470, issued Dec. 9, 1997 to R. M. Gupta et al. discloses techniques for using multiple crossbar switches to accomplish 2×2 and 4×4 matrices. Gupta et al. further describe a solid-state electronic switching module capable of operating at microwave frequencies for providing for switching of signals at those frequencies. However, one skilled in the art would appreciate that scaling the devices disclosed by Gupta et al. to larger matrices would require increasing levels of integration or the provision of several discrete devices, which also increases the overall size and complexity of the switching matrix. Another crossbar switch capable of operating at microwave frequencies is disclosed in U.S. Pat. No. 5,309,006, issued May 3, 1994 to Willems et al. Switch matrices using the Willems et al. device would suffer from the same limitations discussed above for the Gupta et al. device.
Another well-known technique used for providing M×N switch matrices is through the use of a crosspoint switch matrix.
Crosspoint switch matrices have been fabricated using semiconductor devices. U.S. Pat. No. 5,446,424, issued Aug. 29, 1995 to J. A. Pierro, discloses a crosspoint switching matrix employing multilayer stripline and pin diode switching elements. Pierro discloses a multiple layer structure in which one layer contains row transmission lines and a separate layer contains column transmission lines. Pin diode arrays are placed in apertures within the structure to provide crosspoint switching among and between the row and column transmission lines. One skilled in the art will appreciate that the fabrication of the device according to Pierro may be quite complex, due to the need to fabricate the multiple layers and to insert the pin diode arrays at each crosspoint. Also, scaling the device according Pierro to a large number of signal inputs and/or outputs may also be difficult, due to the need to fabricate all of the row or column transmission lines within a single layer.
Therefore, there exists a need in the art for an apparatus and method that provides for switching multiple electrical inputs to multiple electrical outputs in a low cost and scalable fashion. Further, the apparatus and method should provide low insertion loss for the radio frequency signals to be switched and to provide high isolation between separate radio frequency signals over a broad bandwidth.
Accordingly, the present invention provides an RF switching matrix that is preferably constructed using elemental tiles comprising RF MEMS switches. The use of elemental tiles allows the switch to be scalable to any size matrix, M×N, constrained only by insertion loss parameters. The low insertion loss and high isolation inherent in the RF MEMS switches enable larger switching matrices to be constructed than if other semiconductor switching devices, such as PIN diodes or FET switches, were used.
The elemental tile preferably comprises two input ports and two output ports. RF signals are preferably routed between the input ports and the output ports with RF MEMS switches and microstrip transmission line circuit components.
Embodiments of the present invention may also use an integrated RF motherboard layer on which the elemental switch tiles may be assembled. Embodiments of the present invention may also use an integrated motherboard DC layer that allows the RF MEMS switches in the elemental tiles to be actuated individually without interfering with the RF signals switched within the switch matrix.
Embodiments of the present invention provide bandwidth, scalability and cost advantages over switch matrix technology known in the art. The preferred use of RF MEMS switches in embodiments of the present invention as the switching devices provide the switch matrix with broad bandwidth. RF MEMS switches provide excellent insertion loss, less than 0.25 dB up to 40 GHz, and high isolation, 25-30 dB at 40 GHz. Therefore, signal insertion loss is minimized as multiple switches are traversed in the matrix. Semiconductor switch matrices based on diodes or transistors may be limited in bandwidth due to higher losses in the semiconductor material and frequency selective parasitic impedance. Scalability is provided by the preferred use of monolithic switch tile elements. The switch tile elements allow any size switch matrix to be easily constructed. Many prior art switch matrices are entirely monolithic, which requires that the entire layout of the M×N switch to be determined prior to fabrication. Cost advantages are achieved with embodiments of the present invention by fabricating the switch matrices on low cost substrate material. Further, the broad bandwidth of the preferred RF MEMS switches allow the switch tile elements to be used in a variety of applications at different frequency bands. Thus, the tiles can be designed for high yield fabrication.
A first embodiment of the present invention provides a switch element tile comprising a substrate and three switches disposed on that substrate. The first switch on the substrate operates to electrically connect a row input to a row output, the second switch operates to electrically connect a column input to a column output, and the third switch operates to electrically connect the row input to the column output. The switches preferably comprise MEMS switches, although other switching devices known in the art, such as field effect transistors or PIN diodes, may be used. Microstrip lines on the substrate may be used to conduct electrical energy between the inputs, the outputs and the switches.
A second embodiment of the present invention provides a switch matrix for switching any one of multiple signal inputs to any one of multiple signal outputs. The switch matrix comprises: an array of switch element tiles, each switch element tile having one or more switch element inputs and one or more switch element outputs, each switch element tile of the array being disposed to couple at least one switch element output of each switch element tile to a switch element input of an adjacent switch element tile or to one signal output of the multiple signal outputs; a radio frequency (RF) substrate layer on which the array of switch element tiles are disposed, the RF substrate layer coupling each one of the multiple signal inputs to a corresponding switch element input, the RF substrate layer coupling each one of the multiple signal outputs to a corresponding switch element output, and the RF substrate layer coupling the at least one switch element output of each switch element tile to the switch element input of said adjacent switch element tile; and a bias line substrate layer on which the RF substrate layer is disposed, the bias line substrate layer having a plurality of switch element control inputs, the bias line substrate layer directing the switch element control inputs to the switch element tiles. The switch element tiles preferably comprise the switch element tiles described immediately above.
A third embodiment of the present invention provides a method for connecting various ones of M inputs to various ones of N outputs. The method preferably comprises the steps of providing a plurality of crosspoint switch tiles, each crosspoint switch tile having a row input, a column input, a row output, and a column output and each crosspoint switch tile being switchably operable to couple said row input to said row output or said column output and to couple said column input to said row output or said column output; disposing the plurality of crosspoint switch tiles on an upper side of an radio frequency (RF) substrate, the upper side of said RF substrate having a plurality of microstrip lines; arranging the plurality of crosspoint switch tiles on the RF substrate in rows and columns, wherein the row input of each crosspoint switch tile in each row is electrically coupled to the row output of an adjacent crosspoint switch tile in the same row or to one input of the M inputs with at least one microstrip line of the plurality of microstrip lines and the column output of each crosspoint switch tile in each column is coupled to the column input of an adjacent crosspoint switch tile or to one output of the N outputs with at least one microstrip line of said plurality of microstrip lines; receiving crosspoint switch signals at a bias line substrate disposed on a lower side of the RF substrate; and routing the crosspoint switch signals to the plurality of crosspoint switch tiles with control lines disposed on the bias line substrate and bias vias disposed within the RF substrate.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Preferred embodiments of the present invention provide a broadband switch matrix that may be scaled to a matrix size of M×N, where M is the number of input ports and N is the number of output ports. Embodiments of the present invention follow the same general architecture depicted in
A preferred embodiment of the present invention is shown in FIG. 3.
Switch Element Tile
A preferred embodiment of the switch element tile 19 is shown in FIG. 4. The switch element tile 19 preferably comprises three RF MEMS switches 24, 25, 26 switching across gaps in microstrip transmission lines 27. The RF MEMS switches 24, 25, 26 are preferably the electro-statically actuated metal contacting switches described in U.S. Pat. No. 6,046,659, issued Apr. 4, 2000 to Loo et al. and incorporated herein by reference, although other MEMS switches known in the art may be used. The switch element tile 19 is preferably fabricated on a semi-insulating GaAs substrate 28 in a manner described in U.S. Pat. No. 6,046,659, although other substrates and manners of fabrication may be used. The microstrip transmission lines 27 are preferably fabricated on the same side of the substrate 28 on which the RF MEMS switches 24, 25, 26 are disposed. The side of the substrate 28 opposite the RF MEMS switches 24, 25, 26 and the microstrip transmission lines 27 may be metallized to provide additional RF shielding capabilities. However, such metallization may lead to problems with parasitic capacitance. Hence, modeling of the effect of metallizing the opposite side of the substrate 28 should be performed to determine if the problems with parasitic capacitance and other signal altering effects outweigh the benefits of the additional shielding.
As shown in
In the embodiment depicted in
An airbridge 191 is used to route a signal from the column RF signal input port 23 to the column RF signal output port 22 at the point where the signal must cross the microstrip line 27 that connects the row RF signal input port 20 to the row RF signal output port 21. An enlarged view of the airbridge 191 is shown in FIG. 5.
Returning now to
Preferably, the switch element tile 19 is fabricated for flip-chip attachment to a motherboard. Solder bumps 120 may be disposed at the signal ports 20, 21, 22, 23 and/or the actuation bias pads 31, 32, 33, 34, 35, 36 to facilitate flip-chip attachment. The use of flip-chip connections for microwave circuits and methods of manufacturing solder bumps are described in U.S. Pat. No. 5,629,241, issued May 13, 1997 to Matloubian et al., and U.S. Pat. No. 5,757,074, issued May 26, 1998 to Matloubian et al., both incorporated herein by reference. The solder bumps 120 preferably have heights that are at least an order of magnitude greater than the heights of the switches 24, 25, 26 when they are in the open position, so that flip-chip assembly of the switch element tile 19 onto a motherboard will not interfere with the operation of the switches 24, 25, 26.
The switch element tile 19 described above discusses the use of RF MEMS switches to provide switch devices for routing the electrical signals within the tile 19. However, alternative embodiments of the switch tile may use solid state devices for providing the requisite switching. For example, field effect transistors (FETs) or PIN diodes may be used in place of the RF MEMS switches 24, 25, 26 shown in FIG. 4. Use of solid state devices for the switch devices should not impact the design or fabrication of the RF substrate layer 37, described below, but the bias line substrate layer 38, also described below, may change due to the use of different switch control voltages or currents.
The switch element tile 19 depicted in
RF Substrate Layer
As shown in
A close-up view of the RF substrate layer 37 is shown in FIG. 7. On the top surface of this layer 37 are microstrip lines 40 and upper solder pads 41. The upper solder pads 41 are connected to plated via holes 42, which extend all the way through the layer 37 and terminate on lower solder pads 43 on the lower surface of the layer 37. Preferably, the lower surface of the RF substrate layer 37 is mostly metallized, except in the vicinity of the lower solder pads 43 on the lower surface, where the metal has been removed to provide electrical isolation from the via holes 42. Since the lower solder pads 43 on the lower surface of the RF substrate layer 37 are localized, they should have minimal performance impact on the microstrip lines 40 disposed on the upper surface of the RF substrate layer 37.
The microstrip lines 40 are fabricated according to techniques well-known in the art. Therefore, the microstrip transmission lines 40 may comprise materials typically used for microstrip transmission lines in MMICs, such as gold alloys. Further, the widths and thicknesses of the microstrip lines 40 are also fabricated according to techniques well-known in the art for achieving certain performance characteristics. For example, the widths of the microstrip transmission lines 40 may depend upon the dielectric and thickness of the material comprising the RF substrate layer 37. Generally, a lower dielectric of the material used for the RF substrate layer 37 means that a wider microstrip transmission line 40 must be fabricated. However, the thicknesses, widths, and materials used for the microstrip transmission lines 40 will be selected based on the overall performance characteristics required.
A close-up semi-transparent view of the RF substrate layer 37 is shown in FIG. 8. The microstrip lines 40 and the upper solder pads 41 are fabricated on the layer 37 in such a way that they align with the switch element tiles 19. The switch element tiles 19 are assembled onto the RF substrate layer 37 so that the microstrip lines 40 connect one tile 19 to the next, as shown in the top view in
An alternative embodiment of the RF substrate layer 37 comprises additional microstrip lines to provide the airbridge used to route a signal from the column RF signal input port 23 to the column RF signal output port 22 of the switch element tile 19. Instead of disposing the airbridge directly on the switch element tile 19, as discussed above, the microstrip lines connecting to the column RF signal input and output ports 22, 23 are terminated with solder balls or some other means to provide an electrical connection to the RF substrate layer 37. Microstrip lines are disposed on the RF substrate layer 37 to provide an electrical connection between the column RF signal input port 23 and the column RF signal output port 22 while electrically isolating these ports from the transmission line between the row input and output ports 20, 21.
Bias Line Substrate Layer
As shown in
As shown in
The RF substrate layer 37 and the bias line substrate layer 38 may be fabricated using multiple layer circuit board techniques well-known in the art. The necessary elements in the RF substrate layer 37 and the bias line substrate layer 38, such as bias lines, microstrip lines, solder pads, vias, etc., are then fabricated using these well-known multiple layer techniques. Further, using such techniques, the RF substrate layer 37 and the bias line substrate layer 38 may both each actually comprise several layers to provide the necessary board layout and performance characteristics. Also, materials used in the RF substrate layer 37 and the bias line substrate layer 38 are selected to provide the necessary electrical isolation and structural characteristics. The combination of the RF substrate layer 37 and the bias line substrate layer 38 fabricated using multiple layer circuit board techniques may be considered as a motherboard for the switch element tiles 19.
As previously discussed, flip-chip techniques may be used to assemble the switch element tile 19 on the RF substrate layer 37. Such techniques would generally utilize registration marks provided on the RF substrate layer 37 to properly align the switch element tiles 19 to the RF substrate layer 37. Hence, the RF substrate layer 37 is preferably fabricated with such registration marks. The assembly of the switch element tiles 19 to the RF substrate layer 37 may then be accomplished using fabrication techniques similar to those used for ball grid array (BGA) chips. Such techniques are well-known in the art.
Switch Matrix Structure and Operation
As shown in
A model of the 4×4 RF MEMS switch depicted in
From the foregoing description, it will be apparent that the present invention has a number of advantages, some of which have been described above, and others of which are inherent in the embodiments of the invention described above. Also, it will be understood that modifications can be made to the method described above without departing from the teachings of subject matter described herein. As such, the invention is not to be limited to the described embodiments except as required by the appended claims.
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|U.S. Classification||333/101, 333/103|
|International Classification||H01H59/00, H01P1/12, H01H67/22|
|Cooperative Classification||H01P1/127, H01H59/0009, H01H67/22|
|Apr 3, 2003||AS||Assignment|
Owner name: HRL LABORATORIES, LLC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHAFFNER, JAMES H.;LOO, ROBERT Y.;REEL/FRAME:013940/0567;SIGNING DATES FROM 20030321 TO 20030325
|Aug 14, 2008||FPAY||Fee payment|
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|Oct 16, 2012||FPAY||Fee payment|
Year of fee payment: 8