|Publication number||US6891212 B2|
|Application number||US 10/697,191|
|Publication date||May 10, 2005|
|Filing date||Oct 30, 2003|
|Priority date||Dec 20, 2001|
|Also published as||CN1427416A, CN100447892C, EP1321943A2, EP1321943A3, US6750491, US20030117840, US20040089889|
|Publication number||10697191, 697191, US 6891212 B2, US 6891212B2, US-B2-6891212, US6891212 B2, US6891212B2|
|Inventors||Manish Sharma, Thomas C. Anthony, Lung Tran|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (6), Classifications (12), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a divisional of copending application Ser. No. 10/029,694 filed on Dec. 20, 2001, which is hereby incorporated by reference herein.
Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that is being considered for short-term and long-term data storage. MRAM has lower power consumption than short-term memory such as DRAM, SRAM and Flash memory. MRAM can perform read and write operations much faster (by orders of magnitude) than conventional long-term storage devices such as hard drives. In addition, MRAM is more compact and consumes less power than hard drives. MRAM is also being considered for embedded applications such as extremely fast processors and network appliances.
A typical MRAM device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
The memory cells may be based on tunneling magneto-resistive (TMR) devices such as spin dependent tunneling (SDT) junctions. A typical SDT junction includes a pinned layer, a sense layer and an insulating tunnel barrier sandwiched between the pinned and sense layers. The pinned layer has a magnetization orientation that is fixed so as not to rotate in the presence of an applied magnetic field in a range of interest. The sense layer has a magnetization that can be oriented in either of two directions: the same direction as the pinned layer magnetization or the opposite direction of the pinned layer magnetization. If the magnetizations of the pinned and sense layers are in the same direction, the orientation of the SDT junction is said to be “parallel.” If the magnetizations of the pinned and sense layers are in opposite directions, the orientation of the SDT junction is said to be “anti-parallel.” These two stable orientations, parallel and anti-parallel, may correspond to logic values of ‘0’ and ‘1 .’
The magnetization orientation of the pinned layer may be fixed by an underlying antiferromagnetic (AF) pinning layer. The AF pinning layer provides a large exchange field, which holds the magnetization of the pinned layer in one direction. Underlying the AF layer are usually first and second seed layers. The first seed layer allows the second seed layer to be grown with a (111) crystal structure orientation. The second seed layer establishes a (111) crystal structure orientation for the AF pinning layer.
According to one aspect of the present invention, a magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
Reference is made to
If the magnetization vectors (M1 and M2) of the data and reference layers 12 and 14 are pointing in the same direction, the orientation of the magnetic tunnel junction 10 is said to be “parallel” (see
The insulating tunnel barrier 16 allows quantum mechanical tunneling to occur between the data and reference layers 12 and 14. This tunneling phenomenon is electron spin dependent, causing the resistance of the magnetic tunnel junction 10 to be a function of the relative orientations of the magnetization vectors (M1 and M2) of the data and reference layers 12 and 14. For instance, resistance of the magnetic tunnel junction 10 is a first value (R) if the magnetization orientation of the magnetic tunnel junction 10 is parallel and a second value (R+?R) if the magnetization orientation is anti-parallel. The insulating tunnel barrier 16 may be made of aluminum oxide (Al2O3), silicon dioxide (SiO2), tantalum oxide (Ta2O5), silicon nitride (SiN4), aluminum nitride (AlNx), or magnesium oxide (MgO). Other dielectrics and certain semiconductor materials may be used for the insulating tunnel barrier 16. Thickness of the insulating tunnel barrier 16 may range from about 0.5 nanometers to about three nanometers.
Additional reference is now made to
Coercivities of the data and reference layers 12 and 14 may be made different by using different bit shapes, geometries, compositions, thickness, etc. for the two layers 12 and 14. Potential ferromagnetic layer materials include nickel iron (NiFe), nickel iron cobalt (NiFeCo), cobalt iron (CoFe), other magnetically soft alloys of NiFe and Co, doped amorphous ferromagnetic alloys, and PERMALLOY™ alloy. For example, the data layer 12 may be made of a material such as NiFeCo or CoFe, and the reference layer 14 may be made of a material such as NiFe.
Referring once again to
The direction of the reference layer magnetization vector (M2) is set by a structure 20 including a second electrical conductor 22 that is partially clad with a ferromagnetic material such as NiFe. The second conductor 22, made of an electrically conductive, magnetically non-conductive material such as copper, aluminum or metal alloy, may extend in a direction that is orthogonal to the direction of the first conductor 18.
The ferromagnetic cladding 24 completely covers three sides of the second conductor 22. The depiction of the cladding thickness is exaggerated: the thickness may be about 1 nm to 50 nm (with a typical value of 5 nm). The unclad side of the second conductor 22 is in direct contact with the reference layer 14.
Portions of the cladding 24 are in direct contact with the reference layer 14, thus placing the reference layer 14 in magnetic communication with the cladding 24. As a result, the reference layer 14 and the cladding 22 form a closed flux path (indicated by dashed lines).
Reference is now made to
After the current (IR) is removed, the reference layer magnetization vector (M2) retains its orientation. The orientation is retained because of the closed flux path formed by the reference layer 14 and the cladding 24.
Consider a magnetic tunnel junction 10 having a nominal resistance (R) of 1 Mohm, and a tunneling magneto-resistance of 30%. If the data layer magnetization vector (M1) is pointing to the left, and the magnetic field causes the reference layer magnetization vector (M2) to point to the right (
Data may be written to the magnetic tunnel junction 10 by setting the direction of the data layer magnetization vector (M1). During a write operation, write currents are supplied to the first and second conductors 18 and 22. The current supplied to the first conductor 18 creates a magnetic field about the first conductor 18, and the current supplied to the second conductor 22 creates a magnetic field about the second conductor 22. The two magnetic fields, when combined, exceed the coercivity (HC1) of the data layer 12 and, therefore, cause the magnetization vector (M1) of the data layer 12 to be set in a desired orientation (the orientation depends upon the directions of the currents supplied to the first and second conductors 18 and 22). The data layer magnetization vector (M1) will be set to either the orientation that corresponds to a logic ‘1’ or the orientation that corresponds to a logic ‘0’. Because the coercivity (HC2) of the reference layer 14 is less than that of the data layer 12, the combined magnetic fields cause magnetization (M2) of the reference layer 14 to assume that same orientation as the magnetization (M1) as the data layer 12.
Data is read from the magnetic tunnel junction 10 by sensing the resistance state (either R or R+?R) of the magnetic tunnel junction 10.
The read current is removed (block 314), but the reference layer 14 retains its magnetization orientation. A voltage is applied across the first and second conductors 18 and 22, and hence across the magnetic tunnel junction 10 (block 316). The voltage causes a sense current to flow through the magnetic tunnel junction 10.
The resistance of the magnetic tunnel junction 10 is measured by sensing the current flowing though the magnetic tunnel junction 10 (block 318). The sensed current is inversely proportional to the resistance of the magnetic tunnel junction 10. Thus Is=V/R or Is=V/(R+?R), where V is the applied voltage, Is is the sensed current, R is the nominal resistance of the device 10, and ?R is the change in resistance caused by going from a parallel magnetization orientation to an anti-parallel magnetization orientation.
Now that the direction of the reference layer magnetization vector (M2) and the magnetization orientation of the magnetic tunnel junction 10 are known, the direction of the data layer magnetization can be determined (block 320). The direction of the data layer magnetization indicates whether a logic ‘1’ or a logic ‘0’ is stored in the magnetic tunnel junction 10.
The direction of the resistance state transition (that is, going from Rp to Rap, or Rap to Rp) is determined (block 424). The direction of transition indicates the magnetization orientation of the data layer 12 and, therefore, the logic value stored in the magnetic memory device 10.
This second read method is self-referencing. Therefore, this dynamic approach is insensitive to resistance variations across different devices.
The second method is not limited to a positive polarity that corresponds to a logic ‘0’ and a negative polarity that corresponds to a logic ‘1’. For example, a positive polarity could just as easily correspond to a logic ‘1’, the first and second pulses could have negative and positive polarities, respectively, etc.
A simple sense amplifier 510 for detecting the resistance transition is shown in
Another simple sense amplifier 550 for detecting the resistance transition is shown in
Reference is now made to
Traces functioning as word lines 614 extend along the x-direction in a plane on one side of the array 612. The word lines 614 are in contact with the data layers of the magnetic tunnel junctions 10. Traces functioning as bit lines 616 extend along the y-direction in a plane on an adjacent side of the array 612. The bit lines 616 are partially clad with ferromagnetic material. There may be one word line 614 for each row of the array 612 and one bit line 616 for each column of the array 612. Each magnetic memory tunnel junction 10 is located at a cross point of a word line 614 and a bit line 616.
Each bit line 616 is fully clad on three sides. An unclad side of each bit line is in contact with a column of reference layers. As a result, each clad bit line 616 closes the magnetic flux path for a column of reference layers.
The MRAM device 610 also includes first and second row decoders 618 a and 618 b, first and second column decoders 620 a and 620 b, and a read/write circuit 622. The decoders 618 a, 618 b, 620 a and 620 b select word and bit lines 614 and 616 during read and write operations. A selected magnetic tunnel junction 10 lies at the cross point of a selected word and bit line 614 and 616.
The read/write circuit 622 includes current sources 624 for applying write currents to selected word and bit lines 614 and 616 during write operations. The read/write circuit 622 includes a sense amplifier 626, ground connections 628, and a voltage source 630 for applying voltages during read operations.
The magnetic tunnel junctions 10 are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the magnetic tunnel junction 10 at that cross point in parallel with resistances of magnetic tunnel junctions 10 in the other rows and columns. Thus the array 612 of magnetic tunnel junctions 10 may be characterized as a cross point resistor network.
Because the magnetic tunnel junctions 10 are connected as a cross point resistor network, parasitic or sneak path currents can interfere with the read operations on selected magnetic tunnel junctions 10. Blocking devices such as diodes or transistors may be connected to the magnetic tunnel junctions 10. These blocking devices can block the parasitic currents.
The read/write circuit 622 may use either read method described above. If blocking devices are not used, however, the read method may be modified as follows.
The parasitic currents may be dealt with by using an “equipotential” method disclosed in assignee's U.S. Pat. No. 6,259,644. If configured to use the equipotential method, the read/write circuit 622 may provide the same potential to unselected bit lines 616 as the selected bit line 616, or it may provide the same potential to unselected word lines 614 as the selected bit line 616.
Reference is now made to
A stack of magnetic material is deposited. The stack includes material for the data layers 14, material for the insulating tunnel barriers 16, and material for the reference layers 12. The material for the reference layers 14 forms a closed flux path with the ferromagnetic cladding.
The stack is patterned into bits (FIGS. 13 and 14). Spaces between the bits are filled with dielectric material, and word lines are formed. Each word line is formed over a row of data layers 12.
Alternative embodiments of a magnetic memory device according to the present invention are illustrated in
The structure 820 may be provided with a larger cross-section than the magnetic tunnel junction 10 to compensate for manufacturing tolerances. During manufacture, the reference layer 14 should be centered over the ferromagnetic cladding portions defining the magnetic gap 826. In practice, however, misalignments can occur. Even if misalignments occur, the reference layer 14 should still be positioned over the ferromagnetic cladding 824 to close the flux path.
Although the present invention was described in connection with a magnetic tunnel junction, it is not so limited. The present invention may be applied to other types of magneto-resistive devices that have similar operational characteristics. For instance, the present invention may be applied to giant magneto-resistive (GMR) devices. A GMR device has the same basic configuration as a TMR device, except that data and reference layers are separated by a conductive non-magnetic metallic layer instead of an insulating tunnel barrier. Exemplary spacer layer metals include gold, silver and copper. The relative orientations of the data and reference magnetization vectors affect in-plane resistance of a GMR device.
The present invention is not limited to GMR and TMR devices. For instance, the present invention may be applied to top and bottom spin valves.
Although several specific embodiments of the present invention have been described and illustrated, the present invention is not limited to the specific forms or arrangements of parts so described and illustrated. Instead, the present invention is construed according to the claims the follow.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|US7391641||Nov 23, 2005||Jun 24, 2008||Samsung Electronics Co., Ltd.||Multi-layered magnetic memory structures|
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|US20060227599 *||Jan 30, 2006||Oct 12, 2006||Won-Cheol Jeong||Magnetic memory device and method of fabricating the same|
|US20070115718 *||Nov 23, 2005||May 24, 2007||Manish Sharma||Multi-layered magnetic memory structures|
|U.S. Classification||257/295, 365/173, 365/213, 365/171, 365/232|
|International Classification||G11C11/16, H01L27/105, H01L43/08, G11C11/15, H01L21/8246|
|Aug 22, 2007||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:019733/0030
Effective date: 20070518
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