|Publication number||US6891229 B2|
|Application number||US 10/426,296|
|Publication date||May 10, 2005|
|Filing date||Apr 30, 2003|
|Priority date||Apr 30, 2003|
|Also published as||US20040217437|
|Publication number||10426296, 426296, US 6891229 B2, US 6891229B2, US-B2-6891229, US6891229 B2, US6891229B2|
|Inventors||Andrea Franke, Jonathan Cobb, John M. Grant, Al T. Koh, Yeong-Jyh T. Lii, Bich-Yen Nguyen, Anna M. Phillips|
|Original Assignee||Freescale Semiconductor, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (6), Classifications (6), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The subject invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to a technique for the formation of isolation regions between active areas in a semiconductor substrate, wherein the area available for the formation of active devices is optimized and the threading of crystalline defects to the substrate surface is diminished.
2. Related Art
The design and fabrication of semiconductor devices routinely require that isolation regions be provided in order to physically and electrically decouple active areas that are formed in a semiconductor substrate. Specifically, isolation is necessary to prevent conduction in the form of leakage current between devices. In the context of CMOS technology, it is regularly necessary to isolate areas of the substrate that contain N-channel transistors from areas that contain P-channel transistors. That is, isolation areas are interposed between, for example, an N-channel MOS transistor that is formed in a P-type well and an adjacent P-channel MOS transistor that is formed in an N-type well or substrate. Similarly, isolation is required between adjacent MOS transistors of the same conductivity type. For any semiconductor technology, the metrics applicable to isolation techniques include: circuit density, process complexity, yield, planarity and severity of parasitic effects.
A standard, and somewhat primitive, approach to the provision of isolation between active devices in a semiconductor substrate relies on the local oxidation of silicon (LOCOS) to isolate active areas.
As is well known, the LOCOS process results in a “bird's beak” isolation profile that is characterized by a surface bump and a narrowing tail into the active area. The length of the bird's beak reduces the effective width of the active area and also contributes to the narrow-channel effect. The narrow-channel effect is known to skilled artisans as a subtle consequence of the LOCOS process, resulting from the encroachment by the field oxide into the active area. Specifically, diffusion of dopants from the implanted field oxide areas into the edges of the active region (illustrated by the dashed lines in
Accordingly, alternative approaches have been developed in response to the shortcomings of LOCOS. One such alternative, trench isolation, is predicated on etching away part of the substrate and refilling the etched area (trench) with an insulator, almost invariably deposited oxide. It has been found that the profile of the isolation trenches influences a number of device performance parameters, including the level of leakage current that occurs at the junction between devices. For example, an isolation trench having substantially vertical sidewalls is susceptible to the formation of keyhole voids during subsequent filling of the trench with an oxide insulator. Keyholes (voids) adversely affect reliability and are not acceptable in the fabrication of semiconductor devices.
As an alternative to vertical trenching, tapered trenches have been implemented to extenuate the effects of keyholes during the formation of isolation regions. Tapered isolation trenches, such as the isolation trench depicted in
As depicted in
It has been determined that tapering of the isolation trench from wider at the surface to narrower at the bottom exacerbates the vulnerability of active devices to leakage between adjacent transistors. Tapering in this manner results in a reduction in the distance between adjacent transistors and is therefore attended by a greater susceptibility to leakage. Furthermore, when device dimensions are scaled, the dimensions of the isolation trenches are scaled proportionately. Both the width and the depth of the isolation trench must be reduced concomitantly in order to maintain the aspect ratio of the trench. Scaling therefore minimizes the distance between adjacent devices and further aggravates leakage effects. Tapered trenches also tend to compromise the packing density of devices on a wafer.
Reduction of the trench depth has also been entertained as a technique to obviate the effects of keyholes. That is, it has been found that keyholes can be avoided in the formation of isolation regions by reducing the aspect ratio of the isolation trench. However, reducing the isolation trench depth also diminishes the distance between adjacent transistors. As suggested above, in the event that more aggressive design rules are imposed, the trench depth must be scaled proportionally to maintain substantially the same aspect ratio in an effort to limit the generation of keyholes.
The above-identified difficulties associated with existing vertical trench isolation structures are, in large part, remediated by the isolation technique disclosed in U.S. Pat. No. 6,362,071, Method for Forming a Semiconductor Device With an Opening in a Dielectric Layer, that patent assigned to the assignee of this patent application. As may be seen in
A salient characteristic of the isolation structure depicted in
In one embodiment, the inverted trench profile of
Although the salutary nature of the above-described inverted trench isolation technique cannot be gainsaid, a number of difficulties inhere therein. The dry plasma etching step that is required to form the inverted trench sidewalls presents a process control challenge. This is due in part to the nature of conventional dry plasma etches, which are customarily designed to produce anisotropic etch profiles, rather than the sloped profile dictated by the inverted trench. In addition, the inverted trench fabrication process that is described above has in practice been found to produce trenches that vary in width across the semiconductor wafer, causing the width of the associated active areas to vary accordingly. Finally, the linearly varying slope of the trench sidewalls has been correlated to threading of crystalline defects to the wafer surface. Although threading defects are in all instances undesirable, the minimization of threading dislocation density is particularly critical to SiGe epitaxial devices, in which an uppermost strained Si layer is formed to increase the mobility of holes in P-channel devices and the mobility of electrons in N-channel devices.
Accordingly, there remains a persisting need for improvement in isolation techniques available for semiconductor device fabrication. The desiderata attributable to a more nearly optional isolation structure include: maximization of active device density, ease of fabrication, provision of adequate isolation, resistance to the creation and propagation of crystalline defects, and uniformity across the semiconductor wafer.
The subject invention for Inverted Isolation Formed With Spacers may be better understood by, and its many features, advantages and capabilities made apparent to, those skilled in the art with reference to the Drawings that are briefly described immediately below and attached hereto, in the several Figures of which identical reference numerals (if any) refer to identical or similar elements and wherein:
FIG. 4 through
Skilled artisans appreciate that elements in Drawings are illustrated for simplicity and clarity and have not (unless so stated in the Description) necessarily been drawn to scale. For example, the dimensions of some elements in the Drawings may be exaggerated relative to other elements to promote and improve understanding of embodiments of the invention.
For a thorough understanding of the subject invention, a semiconductor device and fabrication process that provide Inverted Isolation Formed With Spacers, reference is made to the following Detailed Description, which includes the appended claims, in connection with the above-described Drawings.
In a manner that will be made eminently clear below, the subject invention inheres, in one form, is an improved technique for establishing isolation areas between active devices in a semiconductor substrate. Composite isolation posts are erected at predetermined positions on a semiconductor substrate. The isolation posts result from the successive formation of at least two layers of insulating material on the semiconductor substrate, followed by photolithographic patterning. In one embodiment, the first insulating layer is silicon dioxide and the second insulating layer is silicon nitride. Sidewall spacers are disposed adjacent to the vertical walls of each of the posts so that isolation structures are formed that include inverted trenches with convex walls. The trenches are inverted in the sense that the trenches are wider at the substrate surface than at increasing depths into the substrate. Active areas between the sidewalls are filled with semiconductor material, followed by a CMP step. The technique is noteworthy in that it results in increased active area on the substrate, so as to at once enhance circuit packing density while limiting leakage current. The fabrication process is predicated on an easily controllable etch step. The convex nature of the sidewalls reduces threading dislocation density, which is known to be crucial in SiGe epitaxy to fabricate strained Si, high-mobility devices.
An appreciation of the subject invention, in its various aspects and attributes, may be conveniently acquired in the context of the fabrication process in which the subject inverted trenches are formed. To that end, attention is now directed to
At this point it is appropriate to note that the dimensions of isolation posts 50, 51, etc. need not be identical in all respects. Although, in general, the respective heights of posts 50 and 51 must conform in order to maintain the planarity of the substrate surface, the horizontal cross-sections of posts 50 and 51 may be different, as may be appropriate to the device design. Therefore, regardless of the impression conveyed by
As a mechanism to enhance the performance of active devices, a strained cap 101 may be imposed over active areas 80 of the semiconductor device. See FIG. 10. Strained cap 101 is a layer of semiconductor material that is dissimilar to the material that constitutes respective underlying active area 80. It is known that when a thin semiconductive layer is epitaxially pseudomorphologically grown on an underlying semiconductor material to which the epitaxial layer is not lattice matched, the epitaxial layer strains to match the underlying layer. So, for example, if active area 80 is formed from SiGe, as suggested above, or from Ge, then Si constitutes an appropriate material for cap layer 101. In this instance, the lattice constant of active area (be it SiGe or Ge) is greater than the lattice constant of the strained Si cap layer 101. As a result, cap layer 101 will exert a compressive force on underlying active area 80. The compressive stress so exerted is known to cause the mobility of holes in active area 80 to increase by about 60 to 80%.
Conversely, if active area 80 is formed from Si, then a material with a greater lattice constant, such as Ge or SiGe, may be used as cap layer 101. In this instance, cap layer 101 will exert a tensile force on the underlying Si active area 80. Within reasonable limits of lattice mismatch, tensile strain imposed in this manner may be operative to increase the mobility of electrons in N-channel devices by about 80% and to increase the mobility of holes in P-channel devices by about 20%. By way of comparison, no reasonable amount of lattice mismatch appears effective to induce a compressive stress that will result in an appreciable increase in election mobility. Consequently, compressive capping is largely confined to P-channel devices, but is known to be useful as a mechanism to balance the respective majority carrier mobilities of pMOS and nMOS devices in CMOS technology. However, as a general proposition, and notwithstanding the above, capping may be used to effect either a tensile strain or compressive stress on either N-type or P-type devices.
Furthermore, the combinations of materials that may be used is not particularly limited, provided that the lattice constants are dissimilar. The cap layer may have a lattice constant that is either greater than or less than the lattice constant of the underlying area. If greater than, tensile strain is exerted on the underlying layer; if less than, compressive stress is exerted on the underlying area. The maximum thickness to which the cap layer 101 may be grown before the strain is released depends on the degree of lattice mismatch and the mechanical properties of the layers. For a lattice mismatch of a few percent, this thickness is of the order of hundreds of angstroms.
As a further embellishment to the device design described heretofore, protection against threading dislocations may be had by appropriately grading the alloying concentration of active area 80. Specifically, if it assumed, for example, that substrate 40 is Si and that active area 80 is SiGe, then the formation of threading dislocations may be retarded by grading the concentration of Ge in area 80. The Ge concentration is controlled so that the concentration of Ge at the interface between substrate 40 and active area 80 is low, and increases within active area 80 as the distance from substrate 40 increases. For example, the Ge concentration may vary from approximately zero at substrate 40 to a predetermined concentration near cap layer 101. In one embodiment, the concentration of Ge may be limited in accordance with the judicious discretion of the designer, for example, to 25% near cap layer 101. Grading the concentration of Ge allows lattice mismatch between substrate 40 and active area 80 to be minimized. That is, establishing minimal Ge concentration at the interface allows substrate 40 to be substantially lattice matched to active area 80. Because lattice mismatch is a source of threading dislocations that originate at the interface, the minimization of lattice mismatch results in the corresponding suppression of threading dislocations.
From the above Description it should be apparent that the subject technique, including the described device structure and fabrication process, affords numerous features, advantages and capabilities. To wit: the inverted trench structure, as realized through sidewall spacers, maintains a desired level of circuit density while providing the necessary degree of isolation between active devices. The structure is amenable to conveniently controllable and reproducible processing steps. Furthermore, the isolation structure accommodates prospective device scaling and the imposition of increasingly aggressive design rules. In addition, the convex spacer profile is particularly well conceived in that it retards the propagation of crystalline threading defects to the wafer surface. That is, with respect to vertical isolation trenches, to conventional tapered trenches (
In the Description above, the invention has been set forth in the context of specific numerous embodiments, in a manner that is intended to be illustrative and to convey a thorough comprehension of the invention. However, one of ordinary skill in the art pertaining to the design and fabrication of semiconductor devices will appreciate that various modifications and changes may be imparted to the specifically described embodiments without departure from the scope of the invention. For example, unless specifically so stated, the invention is not to be construed as limited to the specific materials or dimensions (such as thickness, etc.) or process parameters identified herein. Similarly, those skilled in the art understand that conductivity or impurity types (P-type, N-type) may, in general, be revised, provided that requisite consistency is preserved. Consequently, the invention is to be understood as embracing all subject matter included within the literal scope of the appended claims, as well as equivalents thereof. Accordingly, the Description and the Figures are properly construed are illustrative of the invention, rather than delimiting, and all modifications to or departures from them are consequently comprehended by the scope of the subject invention.
Similarly, benefits, advantages, capabilities and solutions to operational or other technical challenges have been enumerated with respect to the specific embodiments of the invention, as provided herein. However, the benefits, advantages, capabilities and solutions, and any elements(s) or limitation(s) that give rise to any such benefit, advantage, capability and solution, or that enable or cause the same to become more pronounced, are not to be considered or construed as a critical, required, or essential element or limitation of any or all of the claims, either expressly or by implication or estoppel. Furthermore, as used herein, the terms “comprises,” “comprising,” or any variation thereof, are intended to apply nonexclusively, so that a process, method, article or apparatus that comprises a recited enumeration of elements includes not only recited elements but also other elements not explicitly recited or enumerated but inherent to such process, method, article, or apparatus.
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|U.S. Classification||257/354, 257/E21.545, 257/506|
|Aug 28, 2003||AS||Assignment|
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