|Publication number||US6898112 B2|
|Application number||US 10/322,979|
|Publication date||May 24, 2005|
|Filing date||Dec 18, 2002|
|Priority date||Dec 18, 2002|
|Also published as||CN1726400A, CN100507591C, DE60313660D1, DE60313660T2, EP1579231A1, EP1579231B1, US7235408, US20040120184, US20050153063, WO2004061467A1|
|Publication number||10322979, 322979, US 6898112 B2, US 6898112B2, US-B2-6898112, US6898112 B2, US6898112B2|
|Inventors||Jason Allen Janesky, Bradley N. Engel, Nicholas D. Rizzo, Jon M. Slaughter|
|Original Assignee||Freescale Semiconductor, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (4), Classifications (27), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to a co-pending application entitled “A Method Of Writing To A Scalable Magnetoresistance Random Access To Memory Element” U.S. Ser. No. 09/978859 filed on Oct. 16, 2001, assigned to the assignee of the instant application.
This Invention was made with Government support under Agreement No. MDA972-96-3-0016 awarded by DARPA. The Government has certain rights in the invention.
This invention relates to semiconductor magnetoeletronic devices, and in particular, the present invention relates to semiconductor structures useful in devices that store a magnetic state.
The class of devices that is magnetoelectronic devices is a broad class that includes motors, disk drives, and certain semiconductor memory devices, such as magnetoresistive random access memories (MRAMs), and integrated circuits that include MRAM and logic functions other than MRAM, such as radio and processing circuits. Memory devices of all types are an extremely important component in electronic systems. The three most prevalent semiconductor memory technologies are SRAM (static random access memory), DRAM (dynamic random access memory), and FLASH (a form of non-volatile random access memory), which are essentially non-magnetoelectronic. Each of these memory devices uses an electronic charge to store information and each has its own advantages. SRAM has fast read and write speeds, but it is volatile and requires large cell area. DRAM has high density, but it is also volatile and requires a refresh of the storage capacitor every few milliseconds. This requirement increases the complexity of the control electronics.
FLASH is the major nonvolatile memory device in use today. FLASH uses charge trapped in a floating oxide layer to store information. Drawbacks to FLASH include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 104-10 6 cycles before memory failure. In addition, to maintain reasonable data retention, the thickness of the gate oxide has to stay above the threshold that allows electron tunneling, thus restricting FLASH's scaling trends.
To overcome these shortcomings, new magnetic memory devices are being evaluated. One such device is the MRAM, which stores bits as magnetic states. MRAM has the potential to have speed performance similar to DRAM. To be commercially viable, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.
A significant amount of power is consumed during a write operation of an MRAM cell in an MRAM device having an array of cells. The write operation consists of passing currents through conductive lines external but in close proximity to the MRAM magnetic element. The magnetic fields generated by these currents are sufficient to switch the magnetic state of the free layer of the magnetic element. In addition, as the bit dimension shrinks, the switching field increases for a given shape and film thickness, requiring more current to switch. As will be discussed in more detail below, data is stored in the magnetization state of the free layer of the magnetic element. Therefore a significant challenge to commercializing MRAM devices is to construct MRAM cells that switch the magnetic state using the lowest possible magnetic field, resulting in the lowest possible write currents, while maintaining the integrity of the data within the entire array of elements
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
MRAM device 10 is a magnetoresistive tunneling junction memory cell, or magnetoresistive tunneling junction device (MTJD) that comprises material layers sandwiched between writing conductors that are a word line 20 and a digit line 30. Word line 20 and digit line 30 include conductive material through which a current can be passed to induce a magnetic field within the MRAM device 10. In this illustration, word line 20 is positioned on top of MRAM device 10 and digit line 30 is positioned on the bottom of MRAM device 10 and is directed at a 90° angle to word line 20 (See FIG. 3). It will be appreciated that conductors such as word line 20 and digit line 30 need not be in physical contact with the other layers of the MRAM device 10 for efficient reading and writing operation, the conductors just need to be sufficiently near the regions to which the magnetic field is to be applied such that the magnetic field is effective.
MRAM device 10 includes a bit magnetic region 15, a reference magnetic region 17, and an electrically insulating material that forms a layer that acts as a tunneling barrier 16, as well as those portions of the word line 20 and digit line 30 that carry currents that affect the operation of the MRAM device 10. The bit magnetic region 15 and reference magnetic region 17 may each comprise more than one layer, some of which can have a magnetic moment (all magnetic moments are represented herein as vectors) associated therewith. For example, some conventional MRAMs have a bit magnetic region 15 that is a single ferromagnetic layer or a multilayered unbalanced synthetic antiferromagnetic region. Bit magnetic region 15 for the present invention is a nearly balanced multilayer synthetic antiferromagnetic as described below. The bit magnetic region 15 and reference magnetic region 17 are positioned adjacent to the tunneling barrier 16, on opposite sides thereof. A resistance of the MTJD is determined by the relative polarization directions of a bit magnetic moment and a reference magnetic moment directly in contact with the tunnel barrier. The magnetic moment is a physical property of ferromagnetic materials. The magnetic material and the relative angle of polarization of region 15 or 17 directly adjacent to the tunnel barrier determine the high or low state. In the embodiments described herein, the bit magnetic region is a free ferromagnetic region, meaning that the bit magnetic moment is free to rotate in the presence of an applied magnetic field. The bit magnetic moment has two stable polarities (states) in the absence of any applied magnetic fields along a magnetic axis, known herein as the “bit easy axis”, determined at the time of deposition of the magnetic material and fabrication of the magnetic regions 15 of the MRAM array 3. An axis orthogonal to the bit easy axis is known as the “hard axis”.
Ferromagnetic layers 45, 55 have magnetic moments 58 and 53 (see FIG. 3), respectively, that have respective vector values M1 and M2. Further, ferromagnetic layers 45, 55 include at least one of elements Ni, Fe, Co, Mn or combinations thereof. Antiparallel coupling layer 65 includes a material that induces antiferromagnetic exchange coupling (also called herein an antiferromagnetic exchange material) between the ferromagnetic layers 45, 55 or a material that prevents exchange coupling (also called herein a spacing material) between the ferromagnetic layers 45, 55, or both. The antiferromagnetic exchange material comprises one of the elements Ru, Os, Re, Cr, Rh, Cu, Nb, Mo, W, Ir, V, or combinations thereof, and is not by itself an antiferromagnetic material; rather it is a coupling layer that is key to creating the antiferromagnetic-like properties of the SAF layer. The spacing material is an insulator, of which one example is Al2O3, or a conductor, of which some examples are Ta and Al. The antiparallel coupling layer 65 can comprise two or more layers, each of which may be antiferromagnetic exchange or spacing layers. The magnetic moments 58, 53 are usually oriented anti-parallel due to the coupling of the antiparallel coupling layer 65. The coupling can be induced as when an antiferromagnetic exchange material is used as the antiparallel coupling layer 65, or antiparallel coupling can also be generated by the magnetostatic fields of the ferromagnetic layers in the MRAM device 72. Therefore, the antiparallel coupling layer 65 need not necessarily provide any additional coupling beyond substantially eliminating the ferromagnetic coupling between the two ferromagnetic layers 45, 55 and could therefore be a spacing material, for example, an insulator such as A10 or a conductor such as Ta or Al. For the purposes of explaining the Savtchenko writing technique, there is also defined a net magnetic moment 40 that is the vector resultant of the magnetic moments 58 and 53. Also, it will be understood that bit magnetic region 15 can include synthetic antiferromagnetic layer material structures other than tri-layer structures and the use of tri-layer structures in this embodiment is for illustrative purposes only. For example, one such synthetic antiferromagnetic layer material structure could include a five-layer stack of a ferromagnetic layer/antiparallel coupling layer/ferromagnetic layer/antiparallel coupling layer/ferromagnetic layer structure. The number of ferromagnetic layers is identified as N. To simplify the description, it is assumed hereinafter that N is equal to two so that MRAM device 72 includes one tri-layer structure in bit magnetic region 15 with magnetic moments 53 and 58, as well as a net magnetic moment 40. Also, only the magnetic moments of bit magnetic region 15 are illustrated.
The magnetic moments 58, 53 in the two ferromagnetic layers 45, 55 in the MRAM device 72 can have different thicknesses or material to provide a net magnetic moment 40 given by ΔM=(M2−M1). In this case of Savtchenko writing technology, this tri-layer structure will be nearly balanced; that is, ΔM is less than 15 percent of the average of M2 and M1 (otherwise simply stated as “the imbalance is less than 15 percent”) and is preferably as near to zero as can be economically fabricated in production lots. The magnetic moments of the tri-layer structure of the bit magnetic region 15 are free to rotate with an applied magnetic field. In zero field the bit magnetic moment 58, which is the magnetic moment that is adjacent to the tunneling barrier 16, will be stable in one of two polarized directions along the easy axis.
A measurement current through the MRAM device 72 that is used to read the polarity of the bit magnetic moment 58 depends on the tunneling magnetoresistance, which is governed by the orientation and magnitudes of the bit magnetic moment 58 and a reference magnetic moment of the reference magnetic region 17. When these two magnetic moments are parallel, then the MRAM device resistance is low and a voltage bias will induce a larger measurement current through the MRAM device 72. This state is defined as a “1”. When these two magnetic moments are anti-parallel, then the MRAM device resistance is high and an applied voltage bias will induce a smaller measurement current through the device. This state is defined as a “0”. It will be understood that these definitions are arbitrary and could be reversed, but are used in this example for illustrative purposes. Thus, in magnetoresistive memory, data storage is accomplished by applying magnetic fields that cause the magnetic moments in region 15 to be orientated either one of parallel and anti-parallel directions along the bit easy axis 59 relative to region 17, and reading the written state relies upon resistance measurements that depend on the polarity of the bit magnetic moment relative to the reference magnetic moment (This same operation is true for all of the MRAM devices described herein)
The method of writing to the MRAM device 72 relies on the phenomenon of “spin-flop” for a nearly balanced SAF tri-layer structure, which is well known to one of ordinary skill in the art. Here, the term “nearly balanced” is defined such that the M1 and M2 are within 15% of one another, and includes the case in which M1 and M2 are essentially equal. The “spin-flop” phenomenon lowers the total magnetic energy in an applied field by rotating the magnetic moments of the ferromagnetic layers so that they are nominally orthogonal to the applied field direction but still predominantly anti-parallel to one another. The rotation, or “flop”, combined with a small deflection of each ferromagnetic magnetic moment in the direction of the applied field accounts for the decrease in total magnetic energy.
MRAM device 72 preferably has tri-layer structure that has a non-circular shape characterized by a length/width ratio in a range of 1 to 5. It will be understood that the bit magnetic region 15 of MRAM device 72 can have other shapes, such as square, elliptical, rectangular, or diamond, but it is illustrated as being circular for simplicity.
Further, during fabrication of MRAM array 5, each succeeding layer (i.e. 30, 55, 65, etc.) is deposited or otherwise formed in sequence and each MRAM device 72 may be defined by selective deposition, photolithography processing, etching, etc. in any of the techniques known in the semiconductor industry. During deposition of at least the ferromagnetic layers 45 and 55, a magnetic field is provided to set the bit easy axis. The provided magnetic field creates a preferred anisotropy axis for magnetic moments 53 and 58. The bit easy axis 59 is chosen to be at a 45° angle between word line 20 and digit line 30. It will be appreciated however that angles other than 45° could be used.
To illustrate how the writing methods for the MRAM array 5 work, it is assumed that a preferred anisotropy axis for magnetic moments 53 and 58 is directed at a 45° angle relative to the negative x-and negative y-directions and at a 450 angle relative to the positive x-and positive y-directions. As an example,
There are three magnetic field regions of operation illustrated in FIG. 4. In a magnetic field region 92 there is no switching. For MRAM operation in a magnetic field region 95, a direct writing method is in effect. When using the direct writing method, there is no need to determine the initial state of the MRAM device because the state is only switched if the state being written is different from the state that is stored. The selection of the written state is determined by the direction of current in both word line 20 and digit line 30. For example, if a ‘1’ is to be written, then the direction of current in both lines will be positive. If a ‘1’ is already stored in the element and a ‘1’ is being written, then the final state of the MRAM device will continue to be a ‘1’. Further, if a ‘0’ is stored and a ‘1’ is being written with positive currents, then the final state of the MRAM device will be a ‘1’. Similar results are obtained when writing a ‘0’ by using negative currents in both the word and digit lines. Hence, either state can be programmed to the desired ‘1 or ‘0’ with the appropriate polarity of current pulses, regardless of its initial state. Throughout this disclosure, operation in magnetic field region 95 will be defined-as “direct write mode”.
For MRAM operation in a magnetic field region 97, a toggle writing method is in effect. When using the toggle writing method, there is a need to determine the initial state of the MRAM device before writing because the state is switched every time the MRAM device is written to, regardless of the direction of the currents as long as the same polarity current pulses are chosen for both word line 20 and digit line 30. For example, if a ‘1’ is initially stored then the state of the device will be switched to a ‘0’ after one positive current pulse sequence is flowed through the word and digit lines. Repeating the positive current pulse sequence on the stored ‘0’ state returns it to a ‘1’. Thus, to be able to write the memory element into the desired state, the initial state of MRAM device 72 must first be read and compared to the state to be written. The reading and comparing may require additional logic circuitry, including a buffer for storing information and a comparator for comparing memory states. MRAM device 72 is then written to only if the stored state and the state to be written are different. One of the advantages of this method is that the power consumed is lowered because only the differing bits are switched. An additional advantage of using the toggle writing method is that only uni-polar voltages are required and, consequently, smaller transistors can be used to drive the MRAM device. Throughout this disclosure, operation in magnetic field region 97 will be defined as “toggle write mode”.
Both writing methods involve supplying currents in word line 20 and digit line 30 such that magnetic moments 53 and 58 can be oriented in one of two preferred directions as discussed previously. To fully elucidate the two switching modes, specific examples describing the time evolution of magnetic moments 53, 58, and 40 are now given.
At a time t1, a positive word current 60 is turned on, which induces HW 80 to be directed in the positive y-direction. The effect of positive HW 80 is to cause the nearly balanced anti-aligned MRAM tri-layer to “flop” and become oriented approximately 90° to the applied field direction. The finite antiferromagnetic exchange interaction between ferromagnetic layers 45 and 55 will allow magnetic moments 53 and 58 to now deflect at a small angle toward the magnetic field direction and net magnetic moment 40 will subtend the angle between magnetic moments 53 and 58 and will align with HW 80. Hence, magnetic moment 53 is rotated in clockwise direction 94. Since net magnetic moment 40 is the vector addition of magnetic moments 53 and 58, magnetic moment 58 is also rotated in clockwise direction 94.
At a time t2, positive digit current 70 is turned on, which induces positive HD 90. Consequently, net magnetic moment 40 is being simultaneously directed in the positive y-direction by HW 80 and the positive x-direction by HD 90, which has the effect of causing net magnetic moment 40 to further rotate in clockwise direction 94 until it is generally oriented at a 45° angle between the positive x-and positive y-directions. Consequently, magnetic moments 53 and 58 will also further rotate in clockwise direction 94.
At a time t3, word current 60 is turned off so that now only HD 90 is directing net magnetic moment 40, which will now be oriented in the positive x-direction. Both magnetic moments 53 and 58 will now generally be directed at angles passed their anisotropy hard-axis instability points.
At a time t4, digit current 70 is turned off so a magnetic field force is not acting upon net magnetic moment 40. Consequently, magnetic moments 53 and 58 will become oriented in their nearest preferred directions to minimize the anisotropy energy. In this case, the preferred direction for magnetic moment 53 is at a 45° angle relative to the positive y-and positive x-directions. This preferred direction is also 180° from the initial direction of magnetic moment 53 at time to and is defined as ‘0’. Hence, MRAM device 72 has been switched to a ‘0’. It will be understood that MRAM device 72 could also be switched by rotating magnetic moments 53, 58, and 40 in counter clockwise direction 96 by using negative currents in both word line 20 and digit line 30, but is shown otherwise for illustrative purposes.
For the direct write mode, it is assumed that magnetic moment 53 is larger in magnitude than magnetic moment 58, so that magnetic moment 40 points in the same direction as magnetic moment 53, but has a smaller magnitude in zero field. This unbalanced moment allows the dipole energy, which tends to align the total moment with the applied field, to break the symmetry of the nearly balanced SAF. Hence, switching can occur only in one direction for a given polarity of current.
If larger fields are applied, eventually the energy decrease associated with a flop exceeds the additional energy barrier created by the dipole energy of the unbalanced moment which is preventing a toggle event. At this point, a toggle event will occur and the switching is described by magnetic field region 97.
Magnetic field region 95, in which the direct write mode applies, can be expanded, i.e. toggle mode magnetic field region 97 can be moved to higher magnetic fields, if the times t3 and t4 are equal or made as close to equal as possible. In this case, the magnetic field direction starts at 45° relative to the bit anisotropy axis when word current 60 turns on and then moves to parallel with the bit anisotropy axis when digit current 70 turns on. This example is similar to the typical magnetic field application sequence. However, now word current 60 and digit current 70 turn off substantially simultaneously, so that the magnetic field direction does not rotate any further. Therefore, the applied field must be large enough so that the net magnetic moment 40 has already moved past its hard-axis instability point with both word current 60 and digit current 70 turned on. A toggle writing mode event is now less likely to occur, since the magnetic field direction is now rotated only 45°, instead of 90° as before. An advantage of having substantially coincident fall times, t3 and t4, is that now there are no additional restrictions on the order of the field rise times t1 and t2. Thus, the magnetic fields can be turned on in any order or can also be substantially coincident.
The writing methods described with reference to
Since word current 60 is never switched on, magnetic moments 53 and 58 are never rotated through their anisotropy hard-axis instability points. As a result, magnetic moments 53 and 58 will reorient themselves in the nearest preferred direction when digit current 70 is turned off at a time t3, which in this case is the initial direction at time t0. Hence, the state of MRAM device 72 is not switched. It will be understood that the same result will occur if word current 60 is turned on at similar times described above and digit current 70 is not turned on. Furthermore, it will be understood that even if both the word current 60 and the digit current 70 are both turned on simultaneously, with non-varying magnitudes, the same result will occur. This feature ensures that only one MRAM device in an array will be switched, while the other devices will remain in their initial states. As a result, unintentional switching is avoided and the bit error rate is minimized. Thus, in an approach analogous to that used for the MRAM device 71 described with reference to
One vital performance characteristic of the MRAM device 72 is the power used to write information into it, and the power is directly related to the field strength required for switching (also called herein the “flop field”). It will be appreciated that the strength of an applied magnetic field required for causing the magnetic material of a nearly balanced SAF to flop is determined by the anisotropy of the SAF structure (bit magnetic region 15) and the saturation field of the SAF structure (not shown in
Plot 1410, shown in
Also shown in
The dispersed regions 1610 are formed, in accordance with the preferred embodiment of the present invention, by annealing a nearly balanced SAF structure that has been fabricated using conventional deposition techniques, with the ferromagnetic layers and the antiparallel coupling layer having essentially uniform (but not necessarily equal) thicknesses. This process does not significantly alter the nominal thicknesses of the layers 45, 55, 65 of the nearly balanced SAF. The annealing is performed at a temperature and for a duration that is experimentally determined, for a particular set of materials and size parameters of a SAF structure, to optimize the benefits of the WCR by reducing the flop field, while avoiding permanent remanence.
In accordance with another embodiment of the present invention, a method for forming the WCR is to fabricate the antiparallel coupling layer as a plurality of layers. The layers may be of differing materials and may include one or both of antiferromagnetic exchange coupling materials and spacing materials, as described above. The layers are deposited in a manner experimentally determined to optimize the benefits of the WCR by reducing the flop field while avoiding permanent remanence.
In accordance with another embodiment of the present invention, a very thin uniform layer of antiferromagnetic exchange coupling material can be deposited, followed by another layer of antiferromagnetic exchange coupling material that is deposited using a material that is selected for and deposited in a manner that induces thickness variations that are experimentally determined to achieve the optimized results. The material and deposition parameters are chosen to optimize the desired results.
In accordance with another embodiment of the present invention, the WCR are formed by co-depositing a spacer material with the antiferromagnetic exchange material such that regions of reduced coupling are dispersed throughout the sample. This spacer material could be immiscible to the exchange layer used, so as to provide larger regions of reduced coupling dispersed throughout the sample. The material and deposition parameters are chosen to optimize the desired results.
In accordance with yet another embodiment of the present invention, a method for forming the WCR is by depositing a first ferromagnetic layer, then roughening the surface of the ferromagnetic layer, using any well known technique for doing so—for example, by etching or abrading the layer; then depositing the antiparallel coupling layer followed by a second ferromagnetic layer. The first ferromagnetic layer may also be treated so as to induce a three dimensional island-like growth in the antiferromagnetic coupling layer.
Memory systems 450, 550 as described herein can be included in complicated systems-on-a-chip that include, for example an essentially complete cellular radio, or in microprocessors that are used in a very wide variety of electronic devices, including consumer products ranging from portable music players to automobiles; military products such as communication radios and communication control systems; and commercial equipment ranging from extremely complicated computers to robots to simple pieces of test equipment, just to name some types and classes of electronic equipment.
Referring now to
It will be appreciated that the unique SAF structure described herein is advantageous in memory cells with which the Savtchenko writing technique is used (memory cells of either the tunneling type or non-tunneling type), and the SAF structure described herein may be useful in other magnetoelectronic devices as well, wherein low switching fields are important.
In the foregoing specification, the invention and its benefits and advantages have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims.
As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6469878||Feb 8, 2000||Oct 22, 2002||Seagate Technology Llc||Data head and method using a single antiferromagnetic material to pin multiple magnetic layers with differing orientation|
|US6545906 *||Oct 16, 2001||Apr 8, 2003||Motorola, Inc.||Method of writing to scalable magnetoresistance random access memory element|
|US6633498 *||Jun 18, 2002||Oct 14, 2003||Motorola, Inc.||Magnetoresistive random access memory with reduced switching field|
|US20020024780||Jul 17, 2001||Feb 28, 2002||Sining Mao||Spin valve/GMR sensor using synthetic antiferromagnetic layer pinned by Mn-alloy having a high blocking temperature|
|US20020038331||Sep 12, 2001||Mar 28, 2002||Flavin James D.||Method and apparatus for flash load balancing|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8580580||Apr 1, 2010||Nov 12, 2013||Seagate Technology Llc||Magnetic element with varying areal extents|
|US8611053 *||Mar 8, 2012||Dec 17, 2013||HGST Netherlands B.V.||Current-perpendicular-to-the-plane (CPP) magnetoresistive sensor with multilayer reference layer including a Heusler alloy|
|WO2012035355A2||Sep 16, 2011||Mar 22, 2012||Cambridge Enterprise Ltd||Magnetic data storage|
|WO2012076871A1||Dec 6, 2011||Jun 14, 2012||Cambridge Enterprise Limited||Magnectic structure|
|U.S. Classification||365/158, 365/173, 365/171|
|International Classification||G11C11/16, H01F41/30, G01R33/09, H01F10/32|
|Cooperative Classification||B82Y25/00, B82Y40/00, G11C11/16, H01F10/3254, B82Y10/00, H01F41/302, H01F10/3272, H01L43/12, G01R33/093, H01L43/08|
|European Classification||H01L43/12, H01L43/08, B82Y10/00, B82Y25/00, B82Y40/00, H01F10/32N6A, G01R33/09B, H01F10/32N4, G11C11/16, H01F41/30D|
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