|Publication number||US6899534 B2|
|Application number||US 10/369,067|
|Publication date||May 31, 2005|
|Filing date||Feb 18, 2003|
|Priority date||Jul 9, 1997|
|Also published as||US5986209, US6146919, US6166328, US6188021, US6213747, US6265660, US6537051, US7094046, US20010012526, US20030129271, US20050242421, US20060118938|
|Publication number||10369067, 369067, US 6899534 B2, US 6899534B2, US-B2-6899534, US6899534 B2, US6899534B2|
|Inventors||Patrick W. Tandy|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (40), Non-Patent Citations (1), Referenced by (14), Classifications (51), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 09/819,909, filed Mar. 28, 2001, now U.S. Pat. No. 6,537,051, issued Mar. 25, 2003, which is a continuation of application Ser. No. 09/336,925, filed Jun. 21, 1999, now U.S. Pat. No. 6,213,747 B1, issued Apr. 10, 2001, which is a divisional of application Ser. No. 08/890,414, filed Jul. 9, 1997, now U.S. Pat. No. 5,986,209, issued Nov. 16, 1999.
1. Field of the Invention
This invention relates generally to semiconductor devices. More particularly, the invention pertains to surface and external lead configurations of packaged semiconductor devices for electrical connection to other apparatus.
2. State of the Art
The continuing miniaturization of semiconductor devices is crucial to the electronics industry. Numerous improvements have contributed to the industry growth, including the development of leads-over-chip (LOC) assemblies and their inverse, chip-over-leads (COL) configurations. Thus, the die-attach support was eliminated and lead length was reduced, decreasing the package size. Further developments have included packaged devices in which a plurality of dice and leads therefor are encapsulated within a single package. Such is well illustrated, for example, in U.S. Pat. No. 5,331,235 of Chun, U.S. Pat. No. 5,471,369 of Honda et al., U.S. Pat. No. 5,483,024 of Russell et al., U.S. Pat. No. 5,498,902 of Hara, U.S. Pat. No. 5,508,565 of Hatakeyama et al., U.S. Pat. No. 5,530,292 of Waki et al., and U.S. Pat. No. 5,572,068 of Chun.
While such developments have filled a need, there remain applications wherein it is desirable to electrically attach separate, packaged semiconductor devices to each other, and to circuit boards, in combinations providing the desired results. This focuses our attention on the external electrical connections of the package by which it may be connected to other packaged devices, circuit boards, various electrical conduits, and a wide variety of electrical apparatuses.
The state of the art is illustrated by the representative prior art semiconductor devices shown in drawing
A representative example of a known packaged multi-chip semiconductor device 10 of the piggy-back type is shown in drawing
As shown in drawing
This type of construction has several disadvantages. First, the outer leads 24B of the superposed device 10B must be bent differently from outer leads 24A of the underlying device 10A. Thus, the devices 10A and 10B cannot be interchanged, and the outer leads 24B of device 10B are not configured for attachment to a printed circuit board (PCB).
In addition, each device 10C, 10D (not shown) to be stacked atop device 10B requires a different outer lead configuration to enable proper joining of the stacked devices.
Turning now to drawing
Although the state of the art in package configuration is continually improving, ever-increasing demands for further miniaturization, circuit complexity, production speed, reduced cost, product uniformity and reliability require further improvements in semiconductor device connections by which the devices are readily electrically connected to circuit boards, electrical apparatus, and each other.
In particular, the need for a semiconductor device capable of electrical connection to a plurality of substrates, other devices, or various electrical apparatus in several configurations is presently needed.
In accordance with the invention, a package configuration for a semiconductor device is formed wherein the package size is reduced, stacking of packages is enabled without further modification of a lower or upper package, and the bonding of the device to electrical apparatuses is enhanced.
The external package configuration may be used with any internal configuration of dice, leads, insulative layers, heat sinks, die-to-lead connections, etc. Thus, the internal assembly configuration may comprise a Leads-Over-Chip (LOC), Chip-Over-Leads (COL), single or multiple die, wire bonded leads and/or tape-automated bonding (TAB), as well as other variations or combinations in construction.
A semiconductor package is formed in which the conductive lead has an intermediate portion which is encapsulated to have its exposed surface coplanar with the bottom surface of the package.
The outer lead is then an outward extension of the intermediate portion. The intermediate portion provides a bonding surface for joining to a circuit board, device, etc. In a further improvement of the invention, the encapsulant adjacent the edges of the intermediate lead portion is excised to a depth equaling about 0.1-1.0 of the lead thickness. The excised portion may take a variety of configurations.
In another improvement, the semiconductor device is formed with subsurface intermediate leads by which the leads of the apparatus being connected are properly positioned by chamfered sides.
In another improvement, a semiconductor package is formed with castellated sides and/or ends whereby the outer leads are bent upwardly to fit in the castellation grooves, while extending slightly from the grooves to provide bonding sites for electrical connection to other devices, etc. A mold assembly is described, infra, for producing the castellated package.
The invention is illustrated in the following figures, wherein the elements are not necessarily shown to scale:
A new semiconductor device and method of production thereof is provided by the invention. The semiconductor device is a small footprint semiconductor package amenable to alternative conductive connection (a) in a multi-package vertical stacking configuration, (b) in a multi-package horizontal layout, and (c) to a printed circuit board (PCB) or other substrate.
With reference to the drawings of
As defined herein, the inner leads 106 are completely enclosed within the polymeric package 120. The outer leads 118 are completely outside of the package 120, and the intermediate lead portions 112, as formed, are within the bottom package surface 116 of the polymeric package 120 and have a bottom lead surface 114 exposed. The outer leads 118, shown as inverted-J (IJ) leads, of one device 100 may be joined to the intermediate lead portions 112 of another device, if desired, or either the outer leads or intermediate lead portions may be joined to a circuit board, other electrical conduits, or another electrical apparatus.
In accordance with certain embodiments of the invention, the spacing 122 of the leads of the polymeric package 120 between the lead edges 124 of the intermediate lead portions 112 is partially cut away along and adjacent to the intermediate lead edges 124, exposing at least a portion of each edge. The excised chamfer portions 126 may take several cross-sectional forms, as depicted generally in drawing
A thin coating of polymer will sometimes cover the bottom lead surface 114 following removal of the device from the mold. In the manufacturing process, this coating will be subsequently removed to permit electrical connection to a conductor. The top lead surface 128 and lead edges 124 are embedded in the polymeric package 120. The lead thickness 132 (typically between about 0.5 and 3 mils) and the lead-to-lead spacing 122 (typically at least about 2-3 mils) are indicated.
In one embodiment of the invention illustrated in drawing
In another embodiment shown in drawing
In a further embodiment shown in drawing
Use of bottom leads along the sides of a semiconductor package, together with excision of polymeric material from between the bottom leads, provides a number of improvements. For instance, the device 100 may be electrically joined to another device, piggy-back style, which is already joined to, e.g., a circuit board. Or, the device occupies a smaller amount of area for mounting purposes on a substrate.
Turning now to drawing
In this version, the outer leads 118 are truncated horizontal extensions of the intermediate lead portions 112, extending a short distance 146 outwardly, generally no more than about 8 to about 30 mils from the package sides 119. Preferably, distance 146 is between about 10 and about 20 mils. The outer leads 118 have several surfaces which may be electrically connected to other leads or apparatus, including the upper lead surface 148 and the bottom lead surface 114.
The semiconductor device 100 illustrated in drawing
The semiconductor device 100 of drawing
Like the embodiments previously described, the embodiment illustrated in drawing
Turning now to drawing
As shown in drawing
Portions of bottom lead surface 114 which are to be bottom bonded may have adjacent excised chamfer portions 126 excised or removed as previously described in accordance with the embodiment illustrated in drawing
Another embodiment of the packaged semiconductor device 100 is shown in drawing
While the outer leads 118 are shown as short leads like those of the embodiment of drawing
In this embodiment, inner leads 106 are primarily supported by their adhesive attachment to the insulative tape 158.
The mold assembly 160 includes a top plate 160A and bottom plate 160B which are closed together to form a mold cavity 164 therein.
Mold cavity 164 is defined by an inner surface 166A of the top plate 160A and an inner surface 166B of the bottom plate 160B. A polymeric encapsulant is introduced as a hardenable fluid through openings (not shown) as known in the art.
The top plate 160A and bottom plate 160B are configured to produce a casting or polymeric package 120 (see other figures) with an intermediate lead portion 112 and outer lead 118 having bottom lead surfaces 114 which are coplanar with the bottom package surface 116 of the package.
The mold assembly 160 illustrated in drawing
However, the particular groove/column pattern may also be produced in the molding step, using a mold assembly 170 as illustrated in drawing
In the manufacture of the semiconductor devices 100 of the invention, the steps involved include:
Following step f, the attachment areas of the leads may be plated with, e.g., tin to enhance adhesion in a subsequent solder bonding step.
Where a package of the embodiment of drawing
Where a package of the embodiment of drawing
Where portions of the package adjacent the intermediate lead portions are to be removed, an erosion process or other method known in the art may be used. This step will follow removal from the mold (step e) or a subsequent step.
In the lancing/singulation step, the outer leads are cut in conformance to the particular embodiment, as illustrated in drawing
This discussion and these figures presume and show a relatively exacting removal of polymeric packaging material from adjacent the leads. As is well known in the art, the methods of removing such material at the miniature scale will not generally leave precisely flat surfaces or uniform depths and angles. The embodiments of drawing
As described herein, the invention provides a semiconductor package of reduced size, yet having leads for bottom and side/edge bonding or bottom and top bonding of the package. Thus, multiples of the device may be vertically stacked in parallel, and/or be electrically joined in a generally horizontal coplanar configuration. The invention may be applied to a three-dimension-lead (TDL) package having outer leads on the ends as well as the sides or top, together with bottom surface leads. The die/leadframe assembly shown and described herein is exemplary only, and may include other elements such as additional dice and leadframes, heatsinks, dielectric layers, etc., as known in the art.
It is apparent to those skilled in the art that various changes and modifications may be made in the packaging methods and products of the invention as disclosed herein without departing from the spirit and scope of the invention as defined in the following claims.
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|U.S. Classification||425/117, 257/E23.124, 257/E21.504, 257/E25.023, 257/E23.04, 257/E23.048, 425/470, 257/E23.039, 257/E23.193, 425/116|
|International Classification||B29C33/42, H01L25/10, H01L23/31, H01L23/495, H05K3/34, H01L21/56, H01L23/10|
|Cooperative Classification||H01L2924/00014, H01L2224/854, H01L24/48, H01L24/49, H05K3/3426, H01L2924/12044, H01L2224/48091, H01L2224/32245, H01L23/49555, H01L2224/48247, H01L2224/4826, H01L2224/49171, H01L25/105, H01L23/4951, H01L23/3107, H01L2924/14, H01L21/565, H01L2224/32014, H01L23/49513, H01L2224/73215, H01L2224/73265, H01L23/10, H01L2924/01078, H01L23/49551, H01L2225/1029, H01L2225/1041|
|European Classification||H01L23/495G4B, H01L23/495A4, H01L25/10J, H01L21/56M, H01L23/10, H01L23/495A6, H01L23/495G4B6, H01L23/31H|
|Oct 30, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Sep 28, 2012||FPAY||Fee payment|
Year of fee payment: 8
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426