|Publication number||US6907521 B2|
|Application number||US 09/968,350|
|Publication date||Jun 14, 2005|
|Filing date||Sep 28, 2001|
|Priority date||Sep 28, 2001|
|Also published as||US20030065914|
|Publication number||09968350, 968350, US 6907521 B2, US 6907521B2, US-B2-6907521, US6907521 B2, US6907521B2|
|Inventors||Kim L. Saw-Chu, David Wyatt|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (13), Classifications (13), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to Basic Input/Output System (BIOS). More particularly, the invention relates to enabling video BIOS and display drivers to leverage system BIOS platform abstract.
Many of the Graphics Memory Controller Hub (GMCH) configuration control registers, affecting graphics and graphics memory, are in the system dynamic random-access memory (DRAM) controller device. Moreover, the graphics interface is assigned as Device#2 while the system memory controller is assigned as Device#0, which is owned by system Basic Input/Output System (BIOS) and system bus drivers. However, in Plug-n-Play (PnP) operating systems, such as Windows 2000, graphics drivers are not permitted to access registers or resources not in the drivers' scope of ownership or declared PnP configuration space. Accordingly, in integrated and/or embedded graphics platforms, the platform-specific information is often accessed via the video BIOS communicating with the system BIOS. This communication utilizes private Int15h calls (i.e. interrupts).
However, the Windows display drivers cannot invoke the Int15h real-mode handler from within the operating system. Moreover, the display drivers cannot use the video BIOS when internal graphics is configured as a non-Video Graphics Array (non-VGA) display adapter. Thus, the legacy VGA video BIOS is not available when the adapter is secondary to either a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) VGA adapter.
In recognition of the above-stated difficulties with an existing integrated graphics chipset design, such as Graphics Memory Controller Hub (GMCH) design, the present invention describes embodiments for enhanced chipset design that enables communication and handoff between the graphics device and the system Basic Input/Output System (BIOS). Moreover, the enhanced design includes the graphics chipset system management interrupt (SMI) interfaces that enable communication with the system BIOS through a single persistent or consistent mechanism that is available and is operating system (OS) independent. In one embodiment, the graphics chipset (i.e. GMCH), which is sometimes referred to as North-Bridge, provides the capability to generate an SMI under software control by writing to the Peripheral Component Interconnect (PCI) configuration-space register 0E0h through 0E1h in Device#2.
Accordingly, the present embodiments include hardware SMI trigger, a software interface, and an interface means. The hardware SMI trigger is within the BIOS and drivers' addressable space, which enables the hardware to be visible to both the video BIOS and display drivers. The software interface uses a hardware scratch register that may be written and read by video BIOS, display drivers and system BIOS. The system BIOS is signaled using SMI trigger. The interface means includes a means for passing commands and returning status. Consequently, for purposes of illustration and not for purposes of limitation, the exemplary embodiments of the invention are described in a manner consistent with such use, though clearly the invention is not so limited.
In order to properly configure a system, the video BIOS and display drivers need certain information about the platform and user configuration. As stated above, although the information may be available to the system BIOS, this information is often not available to the video BIOS and display drivers. Furthermore, the directive of the Intel driver and BIOS software architecture is to keep the platform specifics in the platform, and to avoid propagating the platform specifics into the video BIOS and/or display drivers. This directive is meant to avoid creating a combinatorial compatibility problem and to ensure correct versioning, given the wide versatility of integrated graphics chipset (i.e. GMCH) configurations.
Accordingly, the embodiments of the present invention define a mechanism in which the video BIOS and display drivers in the graphics chipset (i.e. GMCH) may work as clients of the System BIOS. The mechanism enables the system to notify the software of events. The mechanism also uses the firmware to perform platform-specific functions, which could not otherwise be performed directly by the video BIOS and/or display drivers without detailed knowledge of the platform-specifics. Hence, the present embodiments avoid replicating the platform-specific interfaces by providing for a single common method that the video BIOS and display drivers may use on both desktop and mobile systems.
The enhanced integrated graphics chipset design provides a bimodal interface for detecting, sizing, and initializing or re-initializing a local video memory from the video BIOS or display drivers using common code. This code resides in the system BIOS. Local video memory is a memory that is connected on a separate bus, which is “local” to the graphics controller, as opposed to being connected to the system-wide processor-memory bus. Thus, when present and enabled the local video memory may be initialized by the System BIOS. This allows the system BIOS to be responsible for ensuring the correct setup for the platform and component specific implementation of the local video memory. The system BIOS may also ensure the correct setup of the type of memory used for the local memory. However, the local video memory is associated with, owned, and controlled by, the graphics device. Therefore, from the operating system's perspective, the display driver is expected to manage local video memory. For example, when performing power-management, graphics power management calls are routed through the display driver, and not the system BIOS.
In one mode, an Int15h call is used. However, the Int15h call is typically used only by the video BIOS to call system BIOS during power-up self-test (POST). Hence, this method is typically unavailable to the display drivers that run within the protected mode of the operating system, and therefore, are prohibited from calling software interrupts. In another mode, System Management Interrupt (SMI) is used to trigger entry into System Management Mode (SMM) context. This SMM context is a special operating system independent context supplied by the system BIOS. Thus, both the video BIOS and display drivers may use this context.
In one embodiment, if the video BIOS is called during POST, a new Int15h function (i.e. Function 5F65) may be called. This function is a local memory function starting with the function to return local memory characteristics (i.e. size and speed) and local memory state under various power management conditions. Thus, the video BIOS may not utilize the SMI interface during POST because SMM is often not initialized until just prior to boot. But, the video BIOS may detect that there is no local memory when the new Int15h function is not supported, an error is returned, or zero local memory is returned by the system BIOS in the field for the local memory. However, if a non-zero, non-error value is returned, this value represents the amount of local memory that may be initialized to a returned speed. This information is essential in mode setting. Thus, this embodiment provides faster speed but is more expensive.
In an alternative embodiment, if the video BIOS is not called in POST but a display driver initializes the chipset, the driver cannot reliably count on Int15h interface. Some operating systems do not support the Int15h interface at all, while others may trap the Int15h call in a configuration that interferes with this interface. Therefore, the alternative embodiment provides a register in PCI configuration space for Device#2. The register may be used to trigger an SMI handled by the system BIOS. This register also has read/write configuration bits. SMI interrupts cannot convey CPU register or structure information without this hardware support. Thus, drivers preset the read/write bits that are in turn readable by the system BIOS in SMI. The bits stored in PCI configuration space for Device#2 are equally accessible in all states. Furthermore, unlike the Int15h interface, the SMI/PCI interface allows software to specify the basic parameters used to initialize the local memory (i.e. in terms of size, latency, and speed) or leave these parameters to the system BIOS. Hence, this embodiment provides cheaper solution but slower speed.
In the illustrated embodiment, a bit 102 in the first register triggers an SMI and causes the processor to leave the current context and enter SMM. Other bits 104, 106, 108 in the first register carry function 104, sub-functions 108, and flags 106. The second register provides exchange space 110 for the supplied or returned data.
There are a number of functions supported including local memory initialize, local memory report, and local memory power-down. Both modes of the interface support a call to the system BIOS to power down local memory. Moreover, there must be a method to re-initialize memory on resume after a previous power down. For example, in exiting the S1 power state of an Advance Configuration and Power Interface (ACPI) machine, the system BIOS is not involved since this state is managed under operating system control, which only calls the driver software. Therefore, only the display drivers have the ability and responsibility to perform re-initialization when exiting D1 or D3. This capability provides a means by which the drivers may call system BIOS to perform the platform-specific re-initialization.
A process for enabling communication and handoff between graphics devices and the system BIOS in accordance with an embodiment of the present invention is illustrated as flowcharts in
In the illustrated embodiment of
Once the system BIOS SMI handler is called (at 206), the client continuously polls for SMI bit clear (at 208) or timeout of the server (at 210). Thus, operations 206 and 208/210 may be performed concurrently. Once the SMI bit clear is detected at 208, the result flags are read (at 212) and returned (at 214). If the server times out at 210, the error is unsupported (at 216) and a failure flag is returned (at 218).
In the illustrated embodiment of
After completing the function processing, the SMI handler clears the SMI bit (at 308) before exiting. This indicates that the SMI handler it has been serviced. As stated above, the client software continues to poll for a change from a “1” to “0” in the SMI bit in order to determine that the call has been handled and the data registers contain valid values.
A system level SMI flow block diagram 400 is illustrated in
Advantages of the present embodiments include platform abstraction regardless of characteristics, implementation, and operating systems. Examples of characteristics may include size and speed, while examples of implementation may include local memory configuration through memory module connector or soldered-down. Other advantages include isolation of drivers and video BIOS from platform specifics. This allows generic drivers and BIOS releases that are independent of platform local memory configuration.
The present embodiments also provide reduction in the development cost, support burden, and validation-effort on software. For example, the enhanced integrated graphics chipset design described above leaves much of the complexity of managing memory such as the Rambus dynamic random access memory (RDRAM) timings and levelization to the vendor or original-equipment-manufacturer (OEM). This also allows improved time-to-market for the majority of the market that may not need or use local memory, and avoid unpleasant alternatives that would otherwise require spinning the driver/BIOS to make special version for any special memory types/issues.
Although, previous products have leveraged system BIOS to support local memory management, those products have overlooked many problems of re-initialization. Moreover, these previous products have relied on the memory being continuously in a useable state. However, as described above, the memory may not always be in a useable state but require continuous adaptation of the drivers to perform tasks (especially in the S1/S3 resume scenario) and accommodate platform specifics.
There has been disclosed herein embodiments for for enhanced chipset design that enables communication and handoff between the graphics device and the system BIOS. The enhanced design includes the graphics chipset system management interrupt (SMI) interfaces that enable communication with the system BIOS through a single persistent or consistent mechanism that is available and is operating system (OS) independent.
While specific embodiments of the invention have been illustrated and described, such descriptions have been for purposes of illustration only and not by way of limitation. Accordingly, throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the system and method may be practiced without some of these specific details. In other instances, well-known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5819050 *||Feb 29, 1996||Oct 6, 1998||The Foxboro Company||Automatically configurable multi-purpose distributed control processor card for an industrial control system|
|US6282601 *||Mar 31, 1999||Aug 28, 2001||International Business Machines Corporation||Multiprocessor data processing system and method of interrupt handling that facilitate identification of a processor requesting a system management interrupt|
|US6317798 *||Feb 11, 1999||Nov 13, 2001||Hewlett-Packard Company||Remote initiation of BIOS console redirection|
|US6502146 *||Mar 29, 2000||Dec 31, 2002||Intel Corporation||Apparatus and method for dedicated interconnection over a shared external bus|
|US6505258 *||Feb 29, 2000||Jan 7, 2003||Compaq Information Technologies Group, L.P.||Comprehensive interface between bios and device drivers to signal events|
|US6594721 *||Feb 29, 2000||Jul 15, 2003||Hewlett-Packard Development Company, L.P.||Surprise hot bay swapping of IDE/ATAPI devices|
|US6678830 *||Jul 2, 1999||Jan 13, 2004||Hewlett-Packard Development Company, L.P.||Method and apparatus for an ACPI compliant keyboard sleep key|
|US6697033 *||Nov 28, 2000||Feb 24, 2004||Ati International Srl||Method and system for changing a display device on a computer system during operation thereof|
|US6701383 *||Jun 22, 1999||Mar 2, 2004||Interactive Video Technologies, Inc.||Cross-platform framework-independent synchronization abstraction layer|
|US6711642 *||Jun 11, 2001||Mar 23, 2004||Via Technologies, Inc.||Method and chipset for system management mode interrupt of multi-processor supporting system|
|US6757770 *||Apr 17, 2000||Jun 29, 2004||Kabushiki Kaisha Toshiba||Computer system supporting a universal serial bus (USB) interface and method for controlling a USB corresponding I/O device|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7051222 *||Dec 31, 2002||May 23, 2006||Intel Corporation||Robust computer subsystem power management with or without explicit operating system support|
|US7100034 *||May 23, 2003||Aug 29, 2006||Hewlett-Packard Development Company, L.P.||System for selecting another processor to be the boot strap processor when the default boot strap processor does not have local memory|
|US7434231 *||Jun 27, 2003||Oct 7, 2008||Intel Corporation||Methods and apparatus to protect a protocol interface|
|US7934082 *||Aug 19, 2005||Apr 26, 2011||Panasonic Corporation||Information processing apparatus and exception control circuit|
|US8082429||Dec 20, 2011||Panasonic Corporation||Information processing apparatus and exception control circuit|
|US8909837 *||Dec 30, 2010||Dec 9, 2014||Inventec Corporation||Method for executing system management interrupt by using identifiers|
|US20040128569 *||Dec 31, 2002||Jul 1, 2004||Wyatt David A.||Robust computer subsystem power management with or without explicit operating system support|
|US20040236935 *||May 23, 2003||Nov 25, 2004||Collins David L.||Boot strap processor selection|
|US20040268368 *||Jun 27, 2003||Dec 30, 2004||Mark Doran||Methods and apparatus to protect a protocol interface|
|US20060294149 *||Jun 24, 2005||Dec 28, 2006||Intel Corporation||Method and apparatus for supporting memory hotplug operations using a dedicated processor core|
|US20090049219 *||Aug 19, 2005||Feb 19, 2009||Hideshi Nishida||Information processing apparatus and exception control circuit|
|US20110173361 *||Jul 14, 2011||Hideshi Nishida||Information processing apparatus and exception control circuit|
|US20120124265 *||May 17, 2012||Inventec Corporation||Method for executing system management interrupt|
|U.S. Classification||713/1, 713/300, 713/100, 345/520, 345/531, 345/519, 345/522, 710/260, 713/2|
|International Classification||G06F9/48, G06F15/177|
|Sep 28, 2001||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAW-CHU, KIM L.;WYATT, DAVID;REEL/FRAME:012226/0132;SIGNING DATES FROM 20010921 TO 20010928
|Sep 6, 2005||CC||Certificate of correction|
|Dec 11, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Jan 28, 2013||REMI||Maintenance fee reminder mailed|
|Jun 14, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Aug 6, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130614