|Publication number||US6908831 B2|
|Application number||US 10/966,994|
|Publication date||Jun 21, 2005|
|Filing date||Oct 15, 2004|
|Priority date||Oct 15, 2003|
|Also published as||DE10348021A1, US20050095788|
|Publication number||10966994, 966994, US 6908831 B2, US 6908831B2, US-B2-6908831, US6908831 B2, US6908831B2|
|Inventors||Lincoln O'Riain, Jörg Radecker|
|Original Assignee||Infineon Technologies Ag|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (7), Classifications (7), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches.
Large scale and very large scale integrated devices have a prominent role in silicon technology since the intention is for more and more devices to have space or to be integrated per chip area. In this case, filling deep trenches or buried insulation of doped material or dielectrics for capacitors, for example for storage capacitors of DRAMs, and also filling IT-trenches or trenches having high aspect ratios (AR >5:1) constitute a general challenge in sub-100 nm silicon technologies. The complete encapsulation of doped material is necessary in order to block outdiffusion of dopant atoms, e.g. boron or phosphorus, into the silicon crystal (active area) and, on the other hand, to protect the doped material, which is readily etched, against subsequent wet-chemical etching processes. The capsule containing the doped material additionally serves as an etching stop during subsequent high-temperature processes, such as, for example, vertical/surrounding gate patterning (poly RIE). An oxide which satisfies the material properties, reflow at moderate temperatures (at around 800° C.), low-stress growth, low layer shrinkage during baking, for large scale integration within a trench is borophosphosilicate glass (BPSG), for example. Hitherto, borophosphosilicate glass has not been used as an insulation material, despite its good flow properties, in the FEOL stage of silicon technology since the problem of boron/phosphorus encapsulation has not been solved. Attempts at covering over the borophosphosilicate glass with a high-density oxide are risky, hardly shrinkable owing to the required oxide thickness, and because it is not possible to remove excess nitride liners at the walls of the trenches.
It is accordingly an object of the invention to provide a method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches which overcomes the above-mentioned disadvantages of the prior art methods of this general type. More specifically, the invention teaches the encapsulation of a doped material within a trench of a semiconductor substrate, the doped material preferably being a borophosphosilicate glass (BPSG).
The idea on which the present invention is based includes nonconformally depositing a cover layer above a partly etchedback filling in a trench, in which case the non-conformal deposition method can provide filling layers having an aspect ratio of greater than 5, and thus provides a much higher material thickness in horizontal regions than in vertical regions. Afterward, the cover layer is etched back isotropically by the smaller thickness of the vertical regions, so that the vertical regions of the cover layer are entirely removed and a residual cover layer remains at the horizontal regions in order to cover over the filling in a capsule.
In the present invention, the problem mentioned in the introduction is solved in particular by a method for encapsulating a filling or a doped material within a trench of a semiconductor substrate. The method includes provision of a first barrier layer in a trench provided in a semiconductor substrate and provision of a second barrier layer above the first barrier layer. The trench is filled with a filling. The filling is etched-back in an upper trench section, so that a hole is produced in an upper trench section and a filling residue remains in a lower trench section. A cover layer is non-conformally produced in the upper trench section, so that a first thickness of a bottom region of the cover layer is greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer in the upper trench section are isotropic etched-back, so that, in the wall region, the cover layer and also the second barrier layer are removed and the first barrier layer remains and the bottom region remains covered by a residual cover layer, as a result of which the filling residue is encapsulated by the first barrier layer and the residual cover layer in a capsule.
In accordance with one preferred development, a silicon nitride liner (Si3N4 liner) is deposited as the cover layer.
In accordance with a further preferred development, the silicon nitride liner deposited as the cover layer is formed as a high-density silicon nitride liner, an HDP-SiN liner, since a high density of the cover layer is required in order to avoid possible “leaks” in the topology that enable outdiffusion of dopant atoms.
In accordance with a further preferred development, a high-density chemical vapor deposition method (HDP-CVP method) is provided as the method for depositing the cover layer or the silicon nitride liner or the high-density silicon nitride liner. The high-density chemical vapor deposition method inherently provides a high aspect ratio (AR >5:1) between horizontal deposition planes and vertical deposition planes, precisely the high aspect ratio and the subsequent wet-chemical etching-back forming a residual cover layer at the bottom region, which layer closes the capsule, without excess nitride liners remaining at the wall regions of the trench.
In accordance with a further preferred development, a silicon nitride liner (Si3N4 liner) is provided as the second barrier layer. Providing the second barrier layer as a silicon nitride liner and the cover layer as a silicon nitride liner results in that a homogeneous material transition is available, so that both layers can be etched back isotropically by an etching-back process.
In accordance with a further preferred development, a borophosphosilicate glass (BPSG) is provided as the filling since a borophosphosilicate glass (BPSG) has very good flow properties, the reflow can be carried out at moderate temperatures (around 800° C.), BPSG provides low-stress growth and has low layer shrinkage during baking.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to
A description is given below, on the basis of an exemplary embodiment, of a process chain according to the invention for encapsulating a filling 5, preferably a doped material, with reference to
With reference to
With reference to
With reference to
Consequently, the filling residue 5′, preferably a borophosphosilicate glass, is buried deep in the trench 2 in a manner encapsulated in the capsule 9.
Subsequently, in a preferred development of the invention, the process chain according to the invention is extended to the effect that the process step according to
With reference to
With reference to
Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways. Thus, the method can also be applied to other substrates or carrier materials in addition to semiconductor substrates.
This application claims the priority, under 35 U.S.C. § 119, of German patent application No. 103 48 021.8, filed Oct. 15, 2003; the entire disclosure of the prior application is herewith incorporated by reference.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5229317||Sep 9, 1992||Jul 20, 1993||Nec Corporation||Method for preventing out-diffusion of phosphorous and boron in a bpsg-buried trench|
|US6376893||Aug 15, 2000||Apr 23, 2002||Hyundai Electronics Industries Co., Ltd.||Trench isolation structure and fabrication method thereof|
|US6544861 *||Apr 8, 2002||Apr 8, 2003||Samsung Electronics Co., Ltd.||Method for forming isolation trench|
|US6596607 *||Sep 14, 2001||Jul 22, 2003||Samsung Electronics Co., Ltd.||Method of forming a trench type isolation layer|
|US20020072198 *||Sep 14, 2001||Jun 13, 2002||Ahn Dong-Ho||Method of forming a trench type isolation layer|
|US20030013271||Jul 13, 2001||Jan 16, 2003||Infineon Technologies North America Corp.||Method for high aspect ratio gap fill using sequential hdp-cvd|
|US20030013272 *||Apr 15, 2002||Jan 16, 2003||Hong Soo-Jin||Trench device isolation structure and a method of forming the same|
|US20030022453 *||Sep 30, 2002||Jan 30, 2003||Hynix Semiconductor Inc.||Isolation structure and fabricating method therefor|
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7179730 *||Jul 1, 2004||Feb 20, 2007||Micron Technology, Inc.||Semiconductor damascene trench and methods thereof|
|US7585773 *||Nov 3, 2006||Sep 8, 2009||International Business Machines Corporation||Non-conformal stress liner for enhanced MOSFET performance|
|US7659159 *||May 24, 2007||Feb 9, 2010||Hynix Semiconductor Inc.||Method of manufacturing a flash memory device|
|US7713887 *||Jun 12, 2007||May 11, 2010||Hynix Semiconductor Inc.||Method for forming isolation layer in semiconductor device|
|US20040241945 *||Jul 1, 2004||Dec 2, 2004||Abbott Todd R.||Semiconductor damascene trench and methods thereof|
|US20050266641 *||Oct 8, 2004||Dec 1, 2005||Mosel Vitelic, Inc.||Method of forming films in a trench|
|US20070298583 *||Jun 27, 2006||Dec 27, 2007||Macronix International Co., Ltd.||Method for forming a shallow trench isolation region|
|U.S. Classification||438/435, 438/437, 257/E21.546|
|International Classification||H01L21/762, H01L29/94|
|May 13, 2005||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:O RIAIN, LINCOLN;RADECKER, JORG;REEL/FRAME:016563/0935
Effective date: 20041011
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|Jan 15, 2010||AS||Assignment|
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