|Publication number||US6912170 B1|
|Application number||US 09/525,180|
|Publication date||Jun 28, 2005|
|Filing date||Mar 14, 2000|
|Priority date||Mar 14, 2000|
|Also published as||US6901545, US7237155, US7627796, US20030145262, US20050180234, US20070201293|
|Publication number||09525180, 525180, US 6912170 B1, US 6912170B1, US-B1-6912170, US6912170 B1, US6912170B1|
|Inventors||Alan R. Wheeler|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (1), Classifications (16), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
I. Field of the Invention
The present invention relates generally to a method and apparatus for permanently disabling an integrated circuit (“IC”) input/output (“I/O”) terminal after packaging. More particularly, the present invention relates to placing a disabling device, such as a fuse, between the output driver and the I/O terminal. As a final step in a test process, once all known good I/Os have been determined, the disabling device can be activated to permanently disconnect the I/O terminal from the IC.
II. State of the Art
State of the Art: Before integrated circuits (“IC”) are placed into ordinary operation, they are packaged and tested to determine which I/O terminals function as they were designed to function. The terminals may be in the form of pins, pads, balls or pillars of an array or other conventional configurations. The I/O terminals which do function reliably are called known good I/Os. Based upon the pattern of known good I/Os for a given type of packaged IC, the ICs are sorted, or “binned,” until they are placed onto printed circuit boards for use, often in combination to simulate an entirely functional IC.
The use of unreliable, or known bad, I/Os of an IC produces incorrect or faulty data, or incorrect processing of received data which can cause problems in the operation of a system. To avoid this problem, particularly when fabricating memory modules, a different pattern of printed circuit board trace ends or pads is used for each pattern or combination of known good I/Os. The pattern of trace pads is designed so that no traces contact a known bad I/O. Thus, for each pattern of known good I/Os, design and fabrication of a new printed circuit board trace and trace pad pattern are required. Although this solution of using a variety of printed circuit board designs is effective, it adds cost to the fabrication process and requires excessive printed circuit board inventory. Therefore, it is desirable to avoid the requirement of using different printed circuit board trace patterns for each different pattern of known good I/Os.
The present invention relates to placing a disabling device or disconnect element between an output driver and an input/output terminal of an integrated circuit to enable permanent disconnection of the input/output terminal after packaging. The disabling device may comprise a device such as a fuse or an antifuse formed or otherwise carried on a semiconductor substrate.
In one embodiment, a dynamic random access memory (“DRAM”) is disclosed having a plurality of known good input/output (“I/O”) terminals and at least one known bad I/O terminal. Each known bad I/O terminal is disconnected as a final step in the test process by activating the disabling device through an external stimulus. Two or more DRAMs having complementary known good I/O terminal patterns may then be coupled in parallel on a carrier substrate such as a printed circuit board having conductive traces which extend to both the known good and the known bad I/O terminals. Multiple sets of two or more DRAMs may be placed on the same DRAM module, each set simulating a single whole DRAM. By using the disconnect element of the invention, a common module design may be used for all patterns of known good I/O terminals.
The nature of the present invention as well as other embodiments of the present invention may be more clearly understood by reference to the following detailed description of the invention, to the appended claims, and to several drawings herein, wherein:
In reference to
Once the I/O terminals of an IC have been tested and it has been determined which of the I/O terminals are known good terminals, the IC is sorted and placed in a bin with other ICs having the same pattern of known good terminals, or otherwise marked as having a particular pattern of known good terminals. For example, if only I/O terminal 1-4are known good, the remaining I/O terminals 5-8 being disconnected from the output drivers for those I/O terminals, the package will be placed in a bin with other similar packages which have I/O terminals 1-4 as known good terminals and I/O terminals 5-8 disconnected.
Taken from the appropriate bin or bins by identification from the marking, the ICs may be placed onto a printed circuit board for use in a particular application. Because the nonfunctional or known bad I/O terminals of the IC have been disconnected from the respective output drivers of the IC, it is not necessary to choose a carrier substrate such as a printed circuit board with traces specially designed to avoid contact with the known bad I/O terminals. Traces of a printed circuit board may contact each of the I/O terminals, both the known good and the known bad terminals. In this way, the cost of fabricating and organizing different printed circuit board designs for different patterns of known good terminals is avoided. A single printed circuit board design may thus be used regardless of the known good terminal pattern.
Depending upon the purpose of the IC and the particular application, software can be used to program which of the known good terminals are associated with which traces. For example, where a single partial DRAM has enough DRAM for a particular application, the known bad I/O terminals may be disconnected from their output drivers and, regardless of the known good I/O terminal pattern, the packaged DRAM may be placed in a socket in which all of the I/O terminals are being contacted. Software can be used to identify which I/O terminals are still connected to output drivers and use the DRAM available from those I/O terminals. Alternatively, multiple partially good ICs having complementary known good terminal patterns can be used in parallel to simulate a whole good IC of a given memory capacity. Use of software programming to identify and connect traces to a particular function are well known in the art. Of particular benefit with using the disconnect element as disclosed herein is the ability to use a single printed circuit board trace pattern regardless of the known good I/O terminal pattern.
In a third embodiment of the invention, shown in
While the previous embodiments have illustrated use of multiple memory chips having overall complementary I/O terminal patterns to simulate a wholly functional memory chip, it will be clear to one of ordinary skill in the art that this is not required. Depending on the pattern which a designer chooses to follow, a common printed circuit board trace design may be fabricated to accommodate the present invention using any number of I/O patterns. For example, as shown in
The previous embodiments have all shown memory chips having only eight I/O terminals per chip. Memory chips having only eight I/O terminals were used to simplify the drawings and explanation of the nature of the invention. It will be clear to one of ordinary skill in the art that application of the present invention is not limited to memory chips with only eight I/O terminals, but can easily be applied to chips having any number of terminals.
By simple example,
As shown in
As will be clear to one of ordinary skill in the art, the disconnect element connected between the I/O terminal and output driver for a DRAM as shown and described herein, is not limited to application in a DRAM. For example, there are many applications in which it is desirable to permanently disconnect an input or output of an IC after packaging to avoid communication with that input or output. One particular example of this is an IC having redundant inputs or outputs provided for varying circuit board trace layouts. Using the disconnect element of the present invention, the unneeded inputs or outputs can be permanently disabled.
Although the present invention has been shown and described with reference to particular embodiments, various additions, deletions and modifications that will be apparent to a person of ordinary skill in the art to which the invention pertains, even if not shown or specifically described herein, are deemed to lie within the scope of the invention as encompassed by the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4605872||Dec 6, 1983||Aug 12, 1986||Tokyo Shibaura Denki Kabushiki Kaisha||Programmable CMOS circuit for use in connecting and disconnecting a semiconductor device in a redundant electrical circuit|
|US5111073||Sep 13, 1990||May 5, 1992||Fujitsu Limited||Wafer-scale semiconductor device having fail-safe circuit|
|US5247522||Nov 27, 1990||Sep 21, 1993||Digital Equipment Corporation||Fault tolerant bus|
|US5424986||Dec 19, 1991||Jun 13, 1995||Sgs-Thomson Microelectronics, Inc.||Semiconductor memory with power-on reset control of disabled rows|
|US5455798||Feb 22, 1994||Oct 3, 1995||Sgs-Thomson Microelectronics, Inc.||Semiconductor memory with improved redundant sense amplifier control|
|US5532966||Jun 13, 1995||Jul 2, 1996||Alliance Semiconductor Corporation||Random access memory redundancy circuit employing fusible links|
|US5612918||Dec 29, 1995||Mar 18, 1997||Sgs-Thomson Microelectronics, Inc.||Redundancy architecture|
|US5926156||Nov 9, 1995||Jul 20, 1999||Sharp Kabushiki Kaisha||Matrix type image display using backup circuitry|
|US6141245 *||Apr 30, 1999||Oct 31, 2000||International Business Machines Corporation||Impedance control using fuses|
|US6346846||Dec 17, 1999||Feb 12, 2002||International Business Machines Corporation||Methods and apparatus for blowing and sensing antifuses|
|US6557106||Dec 12, 1995||Apr 29, 2003||International Business Machines Corporation||Power enabling mechanism, a power enabling method, and a controller for an input/output device|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7627796||Feb 26, 2007||Dec 1, 2009||Micron Technology, Inc.||Testing method for permanent electrical removal of an integrated circuit output|
|U.S. Classification||365/225.7, 365/185.05|
|International Classification||G11C29/02, G11C29/00|
|Cooperative Classification||G11C29/02, G11C29/886, G11C17/16, G11C29/022, G11C29/88, G11C17/18|
|European Classification||G11C29/88, G11C29/886, G11C29/02B, G11C17/16, G11C17/18, G11C29/02|
|Mar 14, 2000||AS||Assignment|
Owner name: MICRON ELECTRONICS, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WHEELER, ALAN R.;REEL/FRAME:010688/0306
Effective date: 20000302
|Mar 30, 2001||AS||Assignment|
Owner name: MEI CALIFORNIA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON ELECTRONICS, INC.;REEL/FRAME:011658/0956
Effective date: 20010322
|Mar 22, 2004||AS||Assignment|
|Nov 26, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Oct 1, 2012||FPAY||Fee payment|
Year of fee payment: 8