|Publication number||US6916684 B2|
|Application number||US 10/391,101|
|Publication date||Jul 12, 2005|
|Filing date||Mar 18, 2003|
|Priority date||Mar 18, 2003|
|Also published as||US20040185601|
|Publication number||10391101, 391101, US 6916684 B2, US 6916684B2, US-B2-6916684, US6916684 B2, US6916684B2|
|Inventors||Frank Stepniak, Matthew R. Walsh, Arun K. Chaudhuri, Michael J. Varnau|
|Original Assignee||Delphi Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (21), Classifications (26), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
(1) Field of the Invention
The present invention generally relates to underfill processes and materials for flip-chip mounted die. More particularly, this invention relates to a process for applying an underfill laminate material to a bumped wafer surface, and then thinning the underfill laminate to re-expose the solder bumps to leave an underfill material of uniform and consistent thickness.
(2) Description of the Related Art
Underfilling is a well known technique for promoting the reliability of surface-mount components, such as flip chips and ball grid array (BGA) packages, that are physically and electrically connected with numerous solder bump connections to traces on an inorganic or organic substrate, such as a reinforced epoxy resin laminate circuit board. The underfill process generally involves using a specially formulated dielectric material to completely fill the void between a component, e.g., die, and substrate and to encapsulate the solder bump connections therebetween. The basic function of the underfill is to reduce the thermal expansion mismatch loading on the solder connections. For this purpose, underfill materials must have a coefficient of thermal expansion (CTE) that is relatively close to that of the solder connections, die and substrate to minimize CTE mismatches that would otherwise reduce the thermal fatigue life of the solder connections.
In conventional practice, underfilling takes place after the die is attached to the substrate. The underfill material is placed along the perimeter of the die, and capillary action is relied on to draw the material beneath the die. Dielectric materials having suitable flow and processing characteristics for capillary underfill processes are typically thermosetting polymers such as epoxies. To achieve an acceptable CTE, a fine particulate filler material such as silica is added to the underfill material to lower the CTE from that of the polymer to something that is more compatible with the CTE's of the die, substrate, and the solder composition of the solder connections. For optimum reliability, the composition of an underfill material and the underfill process parameters must be carefully controlled so that voids will not occur in the underfill material beneath the die, and to ensure that a uniform fillet is formed along the entire perimeter of the die. Both of these aspects are essential factors in terms of the thermal cycle fatigue resistance of the solder connections encapsulated by the underfill.
While capillary-flow underfill materials have been widely and successfully used in flip chip assembly processes, expensive process steps are typically required to repeatably produce void-free underfills. Capillary underfill materials are serially applied to die using expensive dispensing equipment, and are then cured at an elevated temperature (e.g., about 150° C.) for several hours. As a result, the capillary underfill process is a batch-like process that disrupts an otherwise continuous flip chip assembly process. Also, the adhesive strength of a capillary underfill material critically depends on the cleanliness of the die after reflow, necessitating costly cleaning equipment and complex process monitoring protocols. As such, the benefits of flip chip assembly using capillary underfill materials must be weighed against the burden of the capillary underfill process itself.
In view of the above, alternative underfill techniques have been developed. One such technique is to deposit a “no-flow” underfill material on the substrate surface, after which the bumped die is placed on the substrate (forcing the solder bumps through the underfill material), and the die is attached (reflow soldered) to the substrate. Another technique is to laminate a film of underfill material to a bumped wafer prior to die singulation and attachment. With this technique, referred to as wafer-applied underfill (WAU), the solder bumps on the wafer must be re-exposed, such as by burnishing or a laser ablation process.
The process of mounting and underfilling flip chips on laminate substrates can be improved and simplified using the laminate underfill process. In particular, an underfill film that can be applied to a die at wafer-level vastly improves economies of scale and eliminates key inefficiencies found in the capillary underfill process. However, a difficulty in implementing the WAU process centers on the burnishing step, which is a chemical-mechanical polishing (CMP) type process that reduces the thickness of the underfill material to something less than the solder bump height. Burnishing must adequately remove the underfill material, both the polymer matrix material (e.g., epoxy) and the filler material (e.g., silica), from the upper bump surface in order to permit the molten solder bumps to wet the metal traces on the substrate during solder reflow. Since yield losses are unacceptable, the importance of exposed bumps cannot be understated. However, the burnishing process presents several challenges. First, post-burnish height uniformity has been observed to play an important role in assembly yield, yet burnishing techniques are often not sufficiently reproducible. For example, too much material is often left around the bumps and too little material remains near the edges of the die after burnishing to form an adequate fillet. Second, burnishing involves the use of a solvent to chemically dissolve (remove) the polymer matrix material. Suitable organic solvents can have safety issues and require special handling of post-burnished material, i.e., burnished films must be redried by a vacuum bake. Furthermore, the ratio of filler to polymer removal depends on the burnishing media, amount of solvent, time, and burnishing force, the latter of which has proven difficult to control. Also, current equipment sets used in wafer CMP fabrication are optimized for the removal of small amounts (e.g., about one micrometer) of hard filler material, while laminate underfill processes require the removal of a relatively thick (about fifty micrometers) and soft (uncured epoxy/polymer mixture) film layer.
In view of the above, it would be desirable if a laminate underfill process were available that overcame the difficulties and shortcomings of existing WAU processes.
The present invention provides a process for underfilling a bumped die surface using a laminating step and film such that the solder bumps on the die surface are exposed during lamination, eliminating the need to remove a portion of the underfill material through a burnishing step. According to a preferred aspect of the invention, the underfill material is amenable to being deposited at the wafer level.
The underfill process of this invention generally entails laminating a compound film to a surface of a component on which solder bumps are present. The component is preferably one of a number of die defined in a wafer, and the compound film is preferably applied to the bumped surface of the wafer. The compound film comprises a first layer containing an underfill material, and a second layer on (e.g., laminated to) the first layer. The underfill material and the second layer comprise first and second polymer materials that differ from each other. The compound film is laminated to the wafer so that the underfill material is forced between the solder bumps and fills spaces between the solder bumps, but does not cover the solder bumps. In contrast, the second layer covers the solder bumps immediately after laminating the compound film to the wafer surface. The second layer is then selectively removed to expose the solder bumps and the underfill material between the solder bumps. Because of the difference in the polymer materials used to form the first and second layers, the second layer can be readily removed from the first layer by mechanical and/or chemical means without substantially removing any of the first layer.
Following removal of the second layer, individual components (die) are singulated from the wafer. Assembly preferably then proceeds by applying a flux adhesive to a substrate to which one of the components is to be attached. The solder bumps on the components are then registered with bond pads on the substrate so that the underfill material is present in a space defined by and between the component and substrate. Thereafter, the solder bumps, underfill material and flux adhesive are heated to melt the solder bumps, during which time the flux adhesive removes any unsolderable metal oxides that would interfere with wetting and bonding of the solder to the bond pads. Upon cooling, the solder forms solid electrical connections that are metallurgically bonded to the bond pads and encapsulated by an underfill formed by the underfill material and adhesive.
According to a preferred aspect of the invention, the lamination process is a series operation instead of a batch operation, and at the completion of the lamination process the solder bumps are exposed and ready for registration with appropriate terminals on a substrate surface to which the component is to be attached. As such, the prior art requirement for burnishing the underfill material to re-expose the solder bumps is completely eliminated, and a suitable thickness for the underfill material on the component can be more readily and consistently obtained by forming the first layer of the compound film to have a uniform thickness. Accordingly, the present invention offers the ability to consistently form underfills of more uniform thickness, while reducing processing costs and avoiding the use of solvents.
Other objects and advantages of this invention will be better appreciated from the following detailed description.
As represented in
The liner 22 can be any conventional liner material used in the art for WAU processes. A suitable liner material is a Mylar or a similar polyolefin. The underfill layer 16 (and therefore the underfill material 18) generally comprises a dielectric polymer material in which a filler material is dispersed. Suitable materials for the polymer matrix include low viscosity resins such as those disclosed in International Publication Number WO 02/33751 A1. The filler material is chosen in part on the basis of having a coefficient of thermal expansion (CTE) that is lower than that of the polymer matrix for the purpose of reducing the overall CTE of the underfill material 18 to something closer to the CTE's of the substrate 26, wafer 11 (and die 10), and solder bumps 12. Suitable compositions for the filler material include silica, though other filler materials could be used, including silicon nitride (Si3N4), silicon carbide (SiC), aluminum nitride (AIN), boron nitride (BN), or various other materials with suitably low CTE's. In view of the lamination process, suitable particle sizes for the filler material are those that will not impede the penetration of the underfill layer 16 by the solder bumps 12.
To facilitate its separation from the underfill material 18, the sacrificial layer 20 is formed of a material that differs in composition from the polymer matrix of the underfill material 18. The type of material best suited for the sacrificial layer 20 will depend in part on the technique used to remove the layer 20. In one embodiment, the sacrificial layer 20 is mechanically removed, such as by peeling, in which case the sacrificial layer 20 is formed of a butadiene-based rubber so as not to adhere excessively to the underfill material 18 following lamination. In another embodiment, the sacrificial layer 20 is removed chemically, in which case the sacrificial layer 20 is formed of a material that can be dissolved or otherwise removed from the surface of the underfill material 18 without removing the underfill material 18 or damaging the solder bumps 12. In this case, suitable materials for the sacrificial layer 20 include a subset of dry film photoresists containing, for example, polymerized methacrylic acid commercially available from Morton under the name Laminar GA film. Suitable chemical techniques for removing the sacrificial layer 20 include spray or immersion etching in an aqueous-based solution containing sodium carbonate or trisodium phosphate in low (e.g., 2 wt. %) concentrations. Because the sacrificial layer 20 is not a permanent component of the die underfill, the layer 20 is preferably free of any particulate filler material.
Following lamination and then removal of the sacrificial layer 20 and liner 22, the die 10 are singulated from the wafer 11 in any suitable manner.
Because the sacrificial layer 20 does not form a permanent part of the underfill 24, the thickness of the sacrificial layer 20 is not critical, other than being capable of removal from the underfill material 18 without undue difficulty. For this reason, a suitable thickness for the sacrificial layer 16 is about twenty-five to about one hundred micrometers, though lesser and greater thicknesses are foreseeable.
In view of the process by which the underfill 24 is applied to the die 10, the underfill 24 can be readily formulated to contain an amount of filler that will yield a CTE that is sufficiently close to that of the solder connections 20 to improve the reliability of the die assembly. As a result, the underfill process of this invention enables CTE matching in a wider variety of flip chip applications than capillary-flow underfill materials and processes. The WAU process of this invention also has the advantage of a simplified manufacturing process and a reduced number of process steps as compared to capillary-flow underfill materials. Because the underfill material 18 is applied in a lamination process that does not result in the underfill material 18 covering the solder bumps 12, the underfill process of this invention avoids the prior art practice of burnishing or ablating a laminated underfill material to re-expose solder bumps on a die surface prior to die attachment. According to a preferred aspect of the invention, the underfill material 18 is deposited at the wafer level, which permits greater economies of scale and eliminates key inefficiencies found in existing no-flow and capillary flow underfill processes.
While the invention has been described in terms of a preferred embodiment, it is apparent that other forms could be adopted by one skilled in the art. Accordingly, the scope of the invention is to be limited only by the following claims.
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|U.S. Classification||438/108, 438/116, 438/612, 428/40.1, 428/41.8, 438/614, 438/660, 438/615, 438/613, 257/E21.503|
|International Classification||H01L21/44, H01L21/56|
|Cooperative Classification||H01L2924/12042, Y10T428/14, Y10T428/1476, H01L2224/32225, H01L2224/73204, H01L2224/73104, H01L24/27, H01L2224/16225, H01L2224/83191, H01L2224/83192, H01L24/83, H01L21/563, H01L2224/73203|
|Mar 18, 2003||AS||Assignment|
Owner name: DELPHI TECHNOLOGIES, INC., MICHIGAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STEPNIAK, FRANK;WALSH, MATTHEW R.;CHAUDHURI, ARUN K.;ANDOTHERS;REEL/FRAME:013891/0328;SIGNING DATES FROM 20030311 TO 20030312
|Dec 11, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Jan 14, 2013||FPAY||Fee payment|
Year of fee payment: 8