|Publication number||US6917554 B2|
|Application number||US 10/626,469|
|Publication date||Jul 12, 2005|
|Filing date||Jul 24, 2003|
|Priority date||Jan 2, 2002|
|Also published as||US20030123299, US20040223375|
|Publication number||10626469, 626469, US 6917554 B2, US 6917554B2, US-B2-6917554, US6917554 B2, US6917554B2|
|Inventors||Ravi P. Annavajjhala|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (26), Non-Patent Citations (1), Referenced by (2), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation application of U.S. patent application Ser. No. 10/038,105, filed Jan. 2, 2002 by Ravi P. Annavajjhala, entitled “Protection Circuit,” which is incorporated herein by reference in its entirety.
This invention relates to computer systems and, more particularly, to methods and apparatus for providing high voltages in circuitry manufactured by processes typically used to provide low voltage tolerant integrated circuitry.
Flash EEPROM memory arrays have been used in personal computers as a type of long term memory. For example, a flash EEPROM memory array may be used in place of a hard disk drive as described in U.S. Pat. No. 5,822,781, entitled “Sector Based Storage Device Emulator Having Variable-Sized Sector”, issued to S. Wells on Oct. 13, 1998, and assigned to the assignee of the present invention. Such a flash memory array provides a smaller, lighter, functional equivalent of a hard disk drive and is not as sensitive to physical damage. Such a flash memory array would be especially useful in portable computers, where space and weight are important considerations. However, these flash EEPROM memory arrays may also require much higher voltages and substantially more power than that directly available from the batteries of low power portable computers.
Typically, a flash memory array is subdivided into blocks and the erase mode may erase one or more blocks of memory cells. The flash memory cell may be erased by removing excess charge from the floating gate. The conventional method of erasing all the cells in a block of flash memory requires the application of 12 volts to the source terminals of all of the memory cells in the block while the drain terminals are left floating and the gate terminals are grounded. Flash memory cells may be programmed by placing excess charge on the floating gate to increase the threshold voltage of the flash memory cell. Programming is typically achieved by applying approximately 11-12 volts to the gate, 6-7 volts to the drain, and grounding the source terminal so that electrons are placed on the floating gate by hot electron injection. Flash memory cells can be read by applying a fixed voltage to the gate of the flash memory cell in order to determine whether the flash memory cell is in an erased or a programmed state. This technique senses the drain-to-source current, Ids, for the flash memory cell. Reading a flash memory cell typically requires the application of 5 volts to the gate, 1 volt to the drain, and grounding the source terminal. Thus, typical voltages required for flash memory applications include 5 volts for the read mode and 6 and 12 volts for both the program and erase modes.
Power for the flash memory device can be provided by a Vcc line and a Vpp line. The Vcc line is the primary power source for the flash device. The supplemental voltage provided by supply line, Vpp, is typically needed only when writing or erasing the memory because of the higher voltages needed during those operations. Vcc can be approximately 5 volts. Vpp, however, might be 3.3, 5, or 12 volts.
When Vpp is large, a correspondingly large voltage stress is encountered by the field effect transistor devices that pass Vpp to the internal nodes of the Flash chip. The high voltage stresses in turn cause premature breakdown of the transistors. Accordingly, transistors capable of tolerating high voltage stresses are suitable for such applications. Field effect transistor devices with thick oxide layers are relatively tolerant to sustained voltage gradients across their gate oxide on the order of 12 volts. However, since such thick oxide devices have a low transconductance (low GM), they have to be made very large to minimize the voltage drop across them. Such transistors can occupy an undue amount of chip surface area and disadvantageously increase chip size and production cost.
Thin oxide transistor devices such as S devices and P devices occupy much less space on the chip, but generally are not capable of withstanding the voltage stress caused by direct coupling to a sustained power pad voltage. Over time, the large voltage gradient can cause the oxide layers of such S and P devices to fail. For this reason, thick oxide transistor devices have typically been used in protection circuit applications.
Like reference symbols in the various drawings indicate like elements.
The invention relates to circuits for protecting low voltage tolerant devices from sustained high voltages with thin-oxide transistor devices. Depicted in
Also connected to the bus 120 are various peripheral components such as long term memory 104 and circuitry such as a frame buffer 106 to which data may be written which is to be transferred to an output device such as a monitor 114 for display. The construction and operation of long term memory 104 (typically electromechanical hard disk drives) is well known to those skilled in the art. However, rather than the typical electro-mechanical hard disk drive, a flash EEPROM memory array may be used as the long term memory 104. Such flash EEPROM memory arrays are programmed and erased through techniques which utilize voltages greater than those typically available to the integrated circuits of more advanced portable computers. Such flash EEPROM memory arrays typically include circuitry for programming and erasing the memory array. Consequently, in accordance with the present invention, such long term memory arrays as well as memory 112 may provide circuitry for generating high voltages from the lower voltages available from the batteries typically utilized with such computers. In order to generate accurate high voltages for programming and erasing such flash EEPROM memory arrays the present invention introduces voltage regulation circuitry needed to generate precise programming voltages.
Circuitry is also shown in
Transitor devices 206 and 208 are special N-type devices referred to as S devices. S devices are basically N-type devices having a very low threshold voltage level. The use and manufacture of S devices are described in detail in U.S. Pat. No. 5,057,715, entitled “CMOS Output Circuit Using A Low Threshold Device,” issued to Larsen et al. on Oct. 15, 1991, and assigned to the assignee of the present invention. Device 206 is connected in diode fashion to node 204. The gate and drain of device 206 are connected to node 204. The source of device 206 is connected to a second diode-configured transistor device 208. The gate and drain of device 208 are connected to the source of device 206. The source of transistor device 208 is connected to node 202. In the depicted embodiment, both S devices have a threshold voltage of about 0.8 volts with transistor body effect.
P device 210 is a p-channel transistor device, which has an oxide layer significantly thinner than the M and O devices described above. The source of device 210 is connected through node 204 to the power supply pad 201 and the source of n-channel device 206. The drain of transistor device 210 is connected to node 202 and the source of device 208. The gate of device 210 is connected to switching logic 300, which is described in more detail hereinbelow.
Also connected to node 202 is a constant current source 214 and a N-type transistor device 216. In a preferred embodiment, current source 214 maintains the branch current at 2-5 microamperes. The drain of transistor device 216 is connected to node 202. The gate of device 216 is connected to pull-down logic 400, which is also described in more detail hereinbelow.
In operation, the circuit of
Switching logic 300 maintains the gate voltage at Vpp when the chip is not in algorithm. During program or erase modes, logic 300 grounds the gate of P device 210, which permits Vpp to pass to the internal nodes of the flash chip. After the algorithm is complete, logic 300 brings the gate of device 210 back to Vpp, which turns device 210 off and prevents Vpp from passing to node 202. Pull down logic 400 then pulses the gate of device 216 with a 20-30 nanosecond Vcc pulse to activate device 216. When device 216 is active, approximately 2Vts is dropped between the device's drain and source. The voltage of node 202 is thus dropped immediately back to Vpp−2Vts. At the terminating edge of the pull down logic pulse, device 216 goes inactive and the circuit 200 resumes steady state, or non-algorithm, operation.
Turning now to
Referring again to
In other embodiments, the protection circuit of the instant invention may be used in different systems to protect low-voltage tolerant devices from high voltage sources. For instance, the circuit 200 can be used to protect circuits on parts of the chip other than the pad. The protection circuit 200 may also be readily modified to work with variable voltage sources or power supply pads. S devices 206 and 208 may be substituted with other transistor devices having acceptable threshold voltages, and can be advantageously replaced with other thin oxide layer devices. The leaker current source 214 may be substituted with variable controlled voltage sources, transistor devices having sub-threshold current, or an RC circuit that maintains node 202 at a reduced voltage during steady state operation. P device 210 can be advantageously replaced with other thin oxide devices which pass an acceptably high percentage of the source or power pad voltage. P device 210 can be replaced with thick oxide M and O devices or a combination of transistor devices. Logic 300 can be substituted with any suitable switching circuit that activates or disables transistor devices in protection circuit 200 to permit the passage of a substantial fraction of the supply voltage. For example, level shifter 312 can be replaced with a resistor divider circuit coupled to N devices, wherein the resistor and N devices are configured such that the output of switching logic 300 is identical but no transistor device experiences stress from a Vpp input. The pull-down circuit 216, 400 can be advantageously replaced with any suitable array of transistor devices that serve to maintain the node voltage 202 at a desired level after completion of an algorithm. Those skilled in the art will appreciate that leaker 214 and pull-down device 216 can in certain circumstances be combined into one transistor device having an appropriate sub-threshold current. The leaker and/or pull-down elements may be eliminated entirely if the other devices are selected so that the appropriate node voltage is maintained at the drain of device 210.
Aspects of the invention provide for one or more of the following advantages. The use of high GM, thin oxide devices greatly reduces the size of the transistor devices, and accordingly reduces the overall cost and size of the chip. The protection circuit can provide for the maintenance of a relatively constant flash chip node voltage when not in algorithm. The circuit can also provide rapid transition from Vpp to steady state node voltage after an algorithm is complete. The circuit also optionally permits the passage of Vpp through a single transistor device with the use of a single switch. Moreover, the protection circuit is much less complex and involves fewer components than previous protection devices, which further reduces material and production costs.
As used herein, the term “thin oxide transistor” refers to a device having an oxide layer substantially thinner than 320 Angstroms. Thick oxide devices typically have a gate oxide that is 320 to 340 Angstroms thick. The thin oxide P devices used in the depicted embodiments preferably have a gate oxide thickness of less than about 250 Angstroms, and most preferably in range of 170 to 190 Angstroms.
The terms “coupled” or “joined,” are used with reference to components that are directly or indirectly joined together. If one or more intermediary components are inserted between two referenced components, the referenced components are still “coupled” or “joined,” as those terms are used herein.
The term “parallel connection,” as used herein, refers to a topology in which current flow is divided among two or more channels from a common starting point or header. Accordingly, circuit elements are considered to be in parallel even if the outputs of the elements are not directly coupled together.
A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.
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|1||Schematic "HVP21LC.1," (Jan. 24, 1997), corresponding to a circuit believed to have been incorporated in a product publicly distributed prior to Jan. 2, 2002 (1 page).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
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|US8847657 *||Jun 22, 2012||Sep 30, 2014||Avago Technologies General Ip (Singapore) Pte. Ltd.||Low power receiver for implementing a high voltage interface implemented with low voltage devices|
|U.S. Classification||365/226, 257/E27.103, 327/534, 361/111|
|International Classification||H01L27/115, G11C16/30|
|Cooperative Classification||G11C16/30, H01L27/115|
|Jan 7, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Feb 25, 2013||REMI||Maintenance fee reminder mailed|
|Jul 12, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Sep 3, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130712