|Publication number||US6918068 B2|
|Application number||US 10/118,271|
|Publication date||Jul 12, 2005|
|Filing date||Apr 8, 2002|
|Priority date||Apr 8, 2002|
|Also published as||US20030192000|
|Publication number||10118271, 118271, US 6918068 B2, US 6918068B2, US-B2-6918068, US6918068 B2, US6918068B2|
|Inventors||David Kenyon Vail, Stephen S. Wilson, Jeffrey D. Volz, Joshua P. Bruckmeyer, Allen G. Plum|
|Original Assignee||Harris Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (2), Referenced by (27), Classifications (12), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to the field of fault-tolerant communications systems, and more particularly, to selecting between multiple buses in a fault-tolerant communications system.
A typical communications system may include multiple devices, which communicate over a communications bus. The bus may be a serial bus, which sends information sequentially, or may be a parallel bus, which sends information over parallel paths, such as may be found in a computer, for example. Unfortunately, if the communications bus fails or is disrupted, the device may fail entirely. Accordingly, systems requiring higher reliability may typically include a plurality of communications buses, so that if one fails, another one may be used. More particularly, the devices connected to the buses may select or be commanded to operate using one bus among the plurality of buses.
One approach to control switching of devices to use a desired bus includes a bus controller to provide a single bus enable signal to the various other devices, typically slave devices. This single bus enable signal is typically implemented via a resistor connected to power, which is delivered to the bus controller. Accordingly, when the bus controller is selectively powered, the bus enable signal is also generated so that a selected bus, that is, the primary bus, is used by the slave devices. Conversely, if the bus enable signal is not present, or at logic “0”, for example, the slave devices switch from the primary bus to a redundant bus. Unfortunately, a shortcoming of such an approach is that some types of faults in the bus enable signal may also cause complete system failure. For example, a bus enable signal might fail as an open circuit or become connected to some other logic signal in the system (i.e., a bridge fault). The signal might also fail in a way that results in increased susceptibility to electrical noise. These types of bus enable faults can cause complete system failure since these failure types can interfere with commanded switch-overs to a redundant bus.
Another approach to selecting between multiple buses, may be considered an autonomous approach. In accordance with this approach, the bus device monitors activity on the buses and uses a selection algorithm to decide which bus to use. Such an approach is further disclosed in U.S. Pat. No. 4,630,265 to Sexton, for example. This approach may also suffer from errors thereby causing failure of the entire system. Along these lines, U.S. Pat. No. 4,837,788 to Bird discloses a repeater for extending local area networks wherein the repeater also makes a bus selection determination based upon signals on the buses.
U.S. Pat. No. 5,555,372 to Tetreault et al. discloses a relatively complicated system including a device which monitors for errors on multiple buses and broadcasts an error signal if the currently selected bus experiences an error. To avoid inconsistent phasing operation when a number of such devices are in use, the device will retransmit a broadcast error signal regardless of the device's current bus selection state.
Unfortunately, the prior art approaches to providing switching of bus devices between multiple buses may suffer from other relatively likely errors, which result in system disruption or failure. For example, those approaches using a single bus enable signal from a bus controller may fail if there is a single error in the bus enable signal (as described above). An autonomous selection system may also suffer from single errors, if the bus selection is inconsistent for some devices using the bus.
In view of the foregoing background, it is therefore an object of the present invention to provide a communications system and associated method, which is more tolerant of possible errors without suffering failure.
This and other objects, features and advantages in accordance with the present invention are provided by a communications system preferably comprising a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the bus device. More particularly, the bus device may include selection circuitry for selecting one of the communications buses based upon the plurality of bus enable signals and while being tolerant of an error on at least one of the bus enable signals. Accordingly, an error in the bus enable signals will not cause system failure.
The bus controllers may include a primary bus controller that generates first and second bus enable signals. In addition, the primary bus controller may generate first and second bus enable signals both having a same value based upon receiving a primary bus select signal. The primary bus select signal may be delivery of power to the primary bus controller.
The bus controllers may also include a redundant bus controller that generates a third bus enable signal. The redundant bus controller may generate the third bus enable signal based upon receiving a redundant bus select signal. Also, the redundant bus select signal may be delivery of power to the redundant bus controller. In other words, a very straightforward and robust, redundant signaling approach may be provided.
The bus device may comprise selection circuitry, which may include a multiplexer or microprocessor, for example. A truth table may be used to determine which communications bus should be selected based upon the bus enable signals received by the bus device.
A method aspect of the invention is for operating the communications system. In particular, the method may include sending a plurality of bus enable signals from at least one bus controller to at least one bus device. The at least one bus device may select one of the communications buses based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime and double prime notations are used to indicate similar elements in alternate embodiments.
Referring initially to
Referring more particularly to
Each data preprocessor 27″, 28″ is connected to a respective bus controller 32, 33 that may be external circuitry from the data preprocessors. Alternately, the bus controllers 32″, 33″ may be included within the circuitry of the respective data preprocessors 27″, 28″. The data preprocessors 27″, 28″ receive respective primary and redundant bus select signals PSS, RSS from other circuitry, not shown. Additionally, the data preprocessors 27″, 28″ may receive input data from other circuitry as will be appreciated by those skilled in the art. The bus controllers 32″, 33″ send a plurality of bus enable signals to the bus devices. The bus devices 24″, 25″ select a communications bus 21″, 22″ based upon the bus enable signals BE1-BE3 and generate output data based upon the selected communications bus.
More particularly, as illustratively shown, the primary bus controller 32″ generates first and second bus enable signals BE1, BE2. The redundant bus controller generates a third bus enable signal BE3. The bus controllers 32″, 33″ generate the bus enable signals BE1-BE3 based upon receiving respective bus select signals PSS, RSS from external control circuitry. The primary and redundant select signals PSS, RSS may be provided in the form of power delivery to the primary data preprocessor 27″, and therefore to the primary bus controller 32″; or to the redundant data preprocessor 28″, and thus to the redundant bus controller 33. In other words, a very straightforward and robust, redundant signaling approach may be provided, as will be readily appreciated by those skilled in the art.
Referring now additionally to
Referring now additionally to
Referring now additionally to
For example, the following truth table may be used to determine which communications bus 21, 22 should be selected, as will be readily appreciated by those skilled in the art.
BE3 BE2 BE1 Select Comments 0 0 0 R Bad BE3 0 0 1 P Bad BE2 0 1 0 P Bad BE1 0 1 1 P Normal case: P Selected, BE1-3 are all working 1 0 0 R Normal case: R Selected, BE1-3 are all working 1 0 1 R Bad BE1 1 1 0 R Bad BE2 1 1 1 P Bad BE3
In the above table, BE1= bus enable signal 1; BE2= bus enable signal 2; BE3= bus enable signal 3; R= redundant communications bus; P= primary communications bus; BE1 and BE2 are from primary controller 32; and BE3 is from the redundant bus controller 33. The communications system 20 in this example is able to tolerate fault in the bus enable signals BE1-BE3 while selecting a communications bus 21, 22. Those of skill in the art will recognize that multiple faults may be tolerated in some embodiments, and that other logic circuitry may be used to carry out the functions of the truth table.
Referring now to
A method aspect of the invention is for operating the communications system 20. In particular, the method may include sending a plurality of bus enable signals BE1-BE3 from at least one bus controller 32, 33 to at least one bus device 24, 25. The at least one bus device 24, 25 may select one of the communications buses 21, 22 based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4630265||Sep 26, 1984||Dec 16, 1986||General Electric Company||Method and apparatus for selecting for use between data buses in a redundant bus communication system|
|US4668465 *||Oct 26, 1984||May 26, 1987||Westinghouse Electric Corp.||Method and apparatus for remotely monitoring a process carried out in a containment structure|
|US4837788||Nov 8, 1985||Jun 6, 1989||Ford Aerospace & Communications Corporation||Repeater for extending local area networks|
|US5155735 *||Mar 31, 1988||Oct 13, 1992||Wang Laboratories, Inc.||Parity checking apparatus with bus for connecting parity devices and non-parity devices|
|US5276678 *||Jun 18, 1990||Jan 4, 1994||Intelect, Inc.||Distributed switching and telephone conferencing system|
|US5471597 *||Dec 8, 1994||Nov 28, 1995||Unisys Corporation||System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables|
|US5555372||Dec 21, 1994||Sep 10, 1996||Stratus Computer, Inc.||Fault-tolerant computer system employing an improved error-broadcast mechanism|
|US5666480||Jun 6, 1995||Sep 9, 1997||Monolithic System Technology, Inc.||Fault-tolerant hierarchical bus system and method of operating same|
|US6052752||Nov 14, 1996||Apr 18, 2000||Daewoo Telecom Ltd.||Hierarchical dual bus architecture for use in an electronic switching system employing a distributed control architecture|
|1||*||Specification for One Channel of the STC Logic, Nov. 10, 2000.|
|2||*||Specifications for the STC Control Logic, Nov. 10, 2000.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7539800 *||Jul 30, 2004||May 26, 2009||International Business Machines Corporation||System, method and storage medium for providing segment level sparing|
|US7669086||Feb 23, 2010||International Business Machines Corporation||Systems and methods for providing collision detection in a memory system|
|US7685392||Mar 23, 2010||International Business Machines Corporation||Providing indeterminate read data latency in a memory system|
|US7721140||Jan 2, 2007||May 18, 2010||International Business Machines Corporation||Systems and methods for improving serviceability of a memory system|
|US7765368||Jul 27, 2010||International Business Machines Corporation||System, method and storage medium for providing a serialized memory interface with a bus repeater|
|US7844771||Nov 30, 2010||International Business Machines Corporation||System, method and storage medium for a memory subsystem command interface|
|US7870459||Oct 23, 2006||Jan 11, 2011||International Business Machines Corporation||High density high reliability memory module with power gating and a fault tolerant address and command bus|
|US7913015 *||Mar 22, 2011||Medtronic, Inc.||Implantable medical device bus system and method|
|US7934115||Dec 11, 2008||Apr 26, 2011||International Business Machines Corporation||Deriving clocks in a memory system|
|US8140942||Sep 7, 2007||Mar 20, 2012||International Business Machines Corporation||System, method and storage medium for providing fault detection and correction in a memory subsystem|
|US8145868||Mar 27, 2012||International Business Machines Corporation||Method and system for providing frame start indication in a memory system having indeterminate read data latency|
|US8151042||Aug 22, 2007||Apr 3, 2012||International Business Machines Corporation||Method and system for providing identification tags in a memory system having indeterminate data response times|
|US8189497 *||Apr 28, 2004||May 29, 2012||Nxp B.V.||Error detection and suppression in a TDMA-based network node|
|US8296541||Oct 23, 2012||International Business Machines Corporation||Memory subsystem with positional read data latency|
|US8327105||Feb 16, 2012||Dec 4, 2012||International Business Machines Corporation||Providing frame start indication in a memory system having indeterminate read data latency|
|US8381064||Jun 30, 2010||Feb 19, 2013||International Business Machines Corporation||High density high reliability memory module with power gating and a fault tolerant address and command bus|
|US8495328||Feb 16, 2012||Jul 23, 2013||International Business Machines Corporation||Providing frame start indication in a memory system having indeterminate read data latency|
|US20040059862 *||Sep 24, 2002||Mar 25, 2004||I-Bus Corporation||Method and apparatus for providing redundant bus control|
|US20060036827 *||Jul 30, 2004||Feb 16, 2006||International Business Machines Corporation||System, method and storage medium for providing segment level sparing|
|US20070036095 *||Apr 28, 2004||Feb 15, 2007||Koninklijke Philips Electronics N.V.||Error detection and suppression in a tdma-based network node|
|US20070288707 *||Jun 8, 2006||Dec 13, 2007||International Business Machines Corporation||Systems and methods for providing data modification operations in memory subsystems|
|US20080016280 *||Jul 3, 2007||Jan 17, 2008||International Business Machines Corporation||System, method and storage medium for providing data caching and data compression in a memory subsystem|
|US20080065938 *||Nov 9, 2007||Mar 13, 2008||International Business Machines Corporation||System, method and storage medium for testing a memory module|
|US20080098277 *||Oct 23, 2006||Apr 24, 2008||International Business Machines Corporation||High density high reliability memory module with power gating and a fault tolerant address and command bus|
|US20080104290 *||Jan 9, 2008||May 1, 2008||International Business Machines Corporation||System, method and storage medium for providing a high speed test interface to a memory subsystem|
|US20120159237 *||Dec 16, 2010||Jun 21, 2012||Honeywell International Inc.||System and Method of Emergency Operation of an Alarm System|
|WO2015047386A1 *||Sep 30, 2013||Apr 2, 2015||Hewlett-Packard Development Company, L.P.||Interpreting signals received from redundant buses|
|U.S. Classification||714/56, 710/38|
|International Classification||H03M13/00, G08C25/00, G06F11/30, G06F11/00, G06K5/04, H04L1/00|
|Cooperative Classification||G06F11/2005, G06F11/2007|
|European Classification||G06F11/20C4, G06F11/20C2|
|Apr 8, 2002||AS||Assignment|
Owner name: HARRIS CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VAIL, DAVID KENYON;WILSON, STEPHEN S.;VOLZ, JEFFREY D.;AND OTHERS;REEL/FRAME:012781/0465;SIGNING DATES FROM 20020320 TO 20020326
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|Mar 30, 2013||AS||Assignment|
Owner name: NORTH SOUTH HOLDINGS INC., NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS CORPORATION;REEL/FRAME:030119/0804
Effective date: 20130107
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