|Publication number||US6919248 B2|
|Application number||US 10/389,857|
|Publication date||Jul 19, 2005|
|Filing date||Mar 14, 2003|
|Priority date||Mar 14, 2003|
|Also published as||US7335947, US20040178457, US20050212039|
|Publication number||10389857, 389857, US 6919248 B2, US 6919248B2, US-B2-6919248, US6919248 B2, US6919248B2|
|Inventors||Richard Francis, Chiu Ng|
|Original Assignee||International Rectifier Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (18), Classifications (25), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to insulated gate switching devices and more particularly to an insulated gate trench type switching device and a method for the manufacture thereof.
Trench type insulated gate semiconductor devices such as trench type MOSFETs and IGBTs are well known. Typically, a trench type insulated gate semiconductor device includes trenches formed in a semiconductive body, which are lined with a gate insulation layer, such as silicon dioxide, and filled with a conductive gate material such as polysilicon to form a gate structure. The semiconductive body typically includes a first region of a first conductivity type (base region) which extends from a first major surface of the semiconductive body to a predetermined depth. The base region is typically disposed over a second region of a second conductivity type (drift region). The trenches extend from the first major surface of the semiconductive body into the drift region.
In a trench type insulated gate semiconductor device according to a known design, diffused regions of a second conductivity type (conventionally designated as source regions in MOSFETs and as emitters in IGBTs), which extend from the first major surface of the semiconductive body to a predetermined depth, are formed adjacent the sidewalls of the trenches by, for example, an implantation step at a vertical angle to the top surface of the semiconductive body through a mask followed by a diffusion drive. As is well known the diffusion drive step will cause the implanted dopants to travel vertically downward into the semiconductive body and travel in a lateral direction in relation to the sidewalls of the trenches simultaneously.
The diffused regions so formed extend to a depth that is less than the thickness of the base region. Therefore, the diffused regions are spaced from the drift region. As a result a region exists in the base region of the semiconductive body conventionally known as the channel region which is disposed between each diffused region and the drift region and adjacent a sidewall of a trench. It is well known that each channel region may be inverted by application of voltage to the conductive material in the trench adjacent thereto thereby allowing current to flow between the diffused region and the drift region.
The length of the channel region is an important variable as it may control such important design factors as the capability of the device to respond to a high switching frequency. To obtain a shorter channel region in a conventional trench type insulated gate semiconductor device, which may result in having a device that is capable of handling higher switching frequencies, the diffused regions may be driven deeper, thereby shortening the channel region. Such a step, however, requires longer diffusion time at higher temperatures both of which are time consuming and thus increase the manufacturing costs. Additionally, longer diffusion time causes extensive lateral diffusion thus increasing the lateral width of the diffused regions. As a result the lateral area that is covered by the diffused regions increases, which in turn results in lower cell density. In addition, the larger lateral width of each diffused region increases the length of the path that is traveled by leakage or other currents under the diffused regions, thereby adversely affecting the ability of the device to withstand avalanche.
It is, therefore, desirable to have a method for manufacturing a device which may allow for obtaining shorter channel regions and higher cell densities at a reduced cost.
It is an object of the present invention to provide an insulated gate trench type semiconductor device.
It is also an object of the present invention to provide a method for manufacturing an insulated gate trench type semiconductor device which allows for adjusting the length of the channel regions of the device and adjusting of the cell density of the device.
An insulated gate trench type semiconductor device according to the present invention includes a plurality of trenches lined with an insulation layer and filled with a conductive material, and a plurality of L-shaped diffused regions formed adjacent the sidewalls of the trenches. According to one aspect of the present invention, each L-shaped diffused region includes a vertically oriented portion which extends from an edge of a sidewall of a trench to a predetermined depth into the base region of the semiconductive body, and a horizontally oriented portion which extends laterally away form the end of the vertically oriented portion.
The vertically oriented portion of each diffused region in a device according to the present invention is formed by directing dopants at an angle other than a ninety degree angle toward a sidewall of a trench at a sufficient energy to implant the same in the sidewall using the edge of the opposing sidewall as a mask. By adjusting the angular direction of the dopants the depth of the vertically oriented portion of each diffused region may be adjusted which in turn can be used to adjust the length of the channel region.
The horizontally oriented portion of each diffused region of an insulated gate trench type semiconductor device according to the present invention is formed by implanting a layer of dopants adjacent the vertically oriented portion of the diffused region. Thus, by implanting the vertically oriented portion of each diffused region using an edge of a sidewall as a mask the depth of the diffused region may be controlled independent of the lateral width of the diffused region thereby allowing the length of the channel region to be controlled without adverse effects on cell density. In addition, the lateral width of the diffused regions may be controlled, thereby allowing the designer to control the capability of the device to withstand avalanche.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
In semiconductor device 10, emitter regions 16 are doped with dopants of a second conductivity type opposite to the first conductivity type. Semiconductor device 10 also includes high conductivity regions 24 of the first conductivity type which extend to a predetermined depth into base region 14. Semiconductor device 10 includes emitter contact 26, which is in electrical contact with high conductivity regions 24 and emitter regions 16, and collector contact 30. Collector contact 30 is in direct electrical contact with conductivity modulating region 12, which is of the first conductivity type. Buffer region 13, which is of the same conductivity type as, but higher concentration than the drift region 11 is disposed between drift region 11 and conductivity modulating region 30. Conductivity modulating region 12 injects carriers into the drift region which results in improving the overall conductivity of the device during operation. Buffer region 13 improves the turn-off speed of the device by reducing the injection rate of the carriers into the drift region and increasing the recombination rate during a switching cycle.
Conductive gate material 22 in each trench 18 is electrically isolated from emitter contact 26 by a respective insulation plug 28. Conductive gate material 22 in each trench is electrically connected to a gate contact (not shown) such that the application of an appropriate bias to the gate contact will cause inversion in those portions of base region 14 adjacent to trenches 18 (channel regions) to enable conduction between emitter contact 26 and collector contact 30 as is well known in the art.
Semiconductive body 5 in the embodiment shown by
Each emitter region 16 in semiconductor device 10 includes vertically oriented portion 15, which extends vertically into base region 14, and horizontally oriented portion 17 which extends laterally away from the top edge of vertically oriented portion 15, thereby forming an upside down L-shaped structure.
The upside down L-shaped structure of emitter regions 16 is advantageous in that the length of vertically oriented portion 15 of an emitter region 16 can be adjusted to achieve the desired length of the channel region; while the length of horizontally oriented portion 17 of an emitter region 16 can be adjusted as desired to obtain the desired cell density. Also, the width of the vertically oriented portion 15 can be controlled thus allowing the designer to control the ability of the device to withstand avalanche. In a device according to the prior art, to achieve a shorter channel region, the emitter region must be driven for a longer period of time. Such a process is time consuming and expensive. In addition, in a drive step to shorten the channel region the lateral width of the emitter region is also increased thereby reducing the cell density that may be achieved, and adversely affecting the ability of the device to withstand avalanche. Thus, having an L-shaped emitter region provides the designer with the flexibility to adjust the vertical depth of the emitter region independent of its lateral width which allows the length of the channel region to be adjusted without affecting the cell density.
Referring next to
Next, the structure shown by
As seen in
Thereafter, mask 34 is formed over the top surface of semiconductive body 5 by, for example, photolithography or any other known method. Mask 34 includes openings 36 over the top surface of semiconductive body 5 between the trenches as shown by FIG. 11. Dopants of the first conductivity type are then implanted into base region 14 through openings 36 in mask 34. Mask 34 is then removed and the dopants which were implanted through openings 36 are driven to form high conductivity regions 24 as shown by FIG. 12.
Next, dopants of the second conductivity type, such as Arsenic, are implanted on the top surface of semiconductive body 5 to form layer 38 as shown schematically by FIG. 13. The implants in layer 38 are then driven in a drive step to a desired depth and a low temperature oxide (LTO) layer 40 is deposited over the top surface of the semiconductive body 5 to obtain the structure shown by FIG. 14. Contact mask 42 is then formed over LTO layer 40 using photolithography. Contact mask 42 includes openings 44. The LTO and portions of layer 38 below openings 44 are then removed by, for example, etching to obtain the structure shown by FIG. 15. It should be noted that LTO layer 40 and layer 38 are etched until at least the top of high conductivity regions 24 is exposed, which results in the formation of horizontally oriented portions 17 of emitter regions 16, and insulation plugs 28. Also, it should be noted that LTO layer 40 remaining over the top surface of layer 38 is etched back to expose portions of the top surface of horizontally oriented portions 17. This result can be accomplished by, for example, anisotropic etching to vertically etch through LTO layer 40 and layer 38 until high conductivity regions 24 is reached, and then selective wet etching of a desired portions of LTO layer 40 to expose portions of the top surface of horizontally oriented portions 17.
Next, emitter contact 26 is sputtered over the top surface of the structure shown by FIG. 15. Emitter contact 26 may be comprised of aluminum or some other suitable metal. The top surface of the structure is then further processed to provide a gate contact (not shown). The back side of semiconductive body 5 may be further implanted with dopants to form buffer region 13, and conductivity modulating region 12. Optionally, semiconductive body 5 may be then thinned from the back before forming buffer region 13 and conductivity modulating region 12. Lastly, collector contact 30 is sputtered onto the backside of semiconductive body 5 to obtain the device shown by FIG. 1.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6118150 *||Sep 23, 1996||Sep 12, 2000||Mitsubishi Denki Kabushiki Kaisha||Insulated gate semiconductor device and method of manufacturing the same|
|US6274437 *||Jun 14, 1996||Aug 14, 2001||Totem Semiconductor Limited||Trench gated power device fabrication by doping side walls of partially filled trench|
|US6583010 *||Apr 20, 2001||Jun 24, 2003||Fairchild Semiconductor Corporation||Trench transistor with self-aligned source|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7361558 *||Jan 20, 2005||Apr 22, 2008||Vishay-Siliconix||Method of manufacturing a closed cell trench MOSFET|
|US7833863||Apr 22, 2008||Nov 16, 2010||Vishay-Siliconix||Method of manufacturing a closed cell trench MOSFET|
|US8183629||Mar 18, 2008||May 22, 2012||Vishay-Siliconix||Stacked trench metal-oxide-semiconductor field effect transistor device|
|US8368126||Apr 7, 2008||Feb 5, 2013||Vishay-Siliconix||Trench metal oxide semiconductor with recessed trench material and remote contacts|
|US8471390||May 2, 2007||Jun 25, 2013||Vishay-Siliconix||Power MOSFET contact metallization|
|US8604525||Nov 1, 2010||Dec 10, 2013||Vishay-Siliconix||Transistor structure with feed-through source-to-substrate contact|
|US8697571||Oct 17, 2012||Apr 15, 2014||Vishay-Siliconix||Power MOSFET contact metallization|
|US8883580||Dec 27, 2012||Nov 11, 2014||Vishay-Siliconix||Trench metal oxide semiconductor with recessed trench material and remote contacts|
|US9064896||Dec 10, 2013||Jun 23, 2015||Vishay-Siliconix||Transistor structure with feed-through source-to-substrate contact|
|US9306056||Oct 30, 2009||Apr 5, 2016||Vishay-Siliconix||Semiconductor device with trench-like feed-throughs|
|US9425304||Aug 21, 2014||Aug 23, 2016||Vishay-Siliconix||Transistor structure with improved unclamped inductive switching immunity|
|US9443959||May 13, 2015||Sep 13, 2016||Vishay-Siliconix||Transistor structure with feed-through source-to-substrate contact|
|US9716166||Apr 7, 2016||Jul 25, 2017||Vishay-Siliconix||Transistor structure with improved unclamped inductive switching immunity|
|US20050148128 *||Jan 20, 2005||Jul 7, 2005||Pattanayak Deva N.||Method of manufacturing a closed cell trench MOSFET|
|US20070284754 *||May 2, 2007||Dec 13, 2007||Ronald Wong||Power MOSFET contact metallization|
|US20080258212 *||Apr 7, 2008||Oct 23, 2008||Vishay-Siliconix||Trench metal oxide semiconductor with recessed trench material and remote contacts|
|US20090050960 *||Mar 18, 2008||Feb 26, 2009||Vishay-Siliconix||Stacked Trench Metal-Oxide-Semiconductor Field Effect Transistor Device|
|US20110101525 *||Oct 30, 2009||May 5, 2011||Vishay-Siliconix||Semiconductor device with trench-like feed-throughs|
|U.S. Classification||438/270, 257/E29.201, 257/E21.345, 257/E29.04, 257/E21.384, 257/E29.038, 438/524, 438/589|
|International Classification||H01L29/78, H01L21/331, H01L29/08, H01L21/336, H01L21/265, H01L29/739, H01L31/062|
|Cooperative Classification||H01L29/0839, H01L29/7813, H01L29/7397, H01L29/66348, H01L21/26586, H01L29/0847|
|European Classification||H01L29/66M6T2W4T, H01L29/78B2T, H01L29/739C2B2, H01L29/08D3|
|Mar 14, 2003||AS||Assignment|
Owner name: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRANCIS, RICHARD;NG, CHIU;REEL/FRAME:013885/0994
Effective date: 20030312
|Dec 19, 2008||FPAY||Fee payment|
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|Jan 21, 2013||FPAY||Fee payment|
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|Jan 9, 2017||FPAY||Fee payment|
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