|Publication number||US6924216 B2|
|Application number||US 10/440,640|
|Publication date||Aug 2, 2005|
|Filing date||May 19, 2003|
|Priority date||Oct 31, 2002|
|Also published as||DE10250888A1, DE10250888B4, US20040087120|
|Publication number||10440640, 440640, US 6924216 B2, US 6924216B2, US-B2-6924216, US6924216 B2, US6924216B2|
|Inventors||Thomas Feudel, Manfred Horstmann, Rolf Stephan|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Non-Patent Citations (1), Referenced by (5), Classifications (24), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the implanting of ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits. More specifically, the present invention relates to a method of forming shallow “halo” structures of field effect transistors.
2. Description of the Related Art
In the last several years, the number of circuit elements manufactured on semiconductor substrates has continuously grown. For example, in modem integrated circuit devices, there may be approximately one billion elements per chip due to the continuing miniaturization of feature sizes.
Presently, circuit elements are commonly fabricated featuring minimal sizes of less than 0.18 μm and the progress in manufacturing technology seems likely to continue on in this manner. However, in the particular case of field effect transistors, with the increasing miniaturization of the transistors, it became apparent that MOSFETs exhibit short-channel effects not predicted by the standard MOSFET models. Such short-channel effects comprise, among others, sub-surface punch-through in NMOSFETs and punch-through in PMOSFETs.
Great efforts have been made and several measures have been taken to prevent short-channel MOSFETs from entering the punch-through regime. Among these measures, implanting dopants under the source/drain extension (SDE) regions has proved to be the most reliable and has, therefore, become the most likely used technique for preventing punch-through behavior in field effect transistors. Such implants have been termed “halo” implants.
However, in view of the reduced lateral dimensions of the transistors, the doping profiles of “halo” implants have to also be restricted to shallower locations, that is, “halo” implantations need to be confined within shallow regions close to the surface of the substrate on which the transistors have to be formed. To obtain the shallow halo doping profiles required for source/drain extensions and channels, all physical mechanisms allowing dopants to penetrate deeper into silicon must be strictly controlled or eliminated. In particular, the principal factor to be controlled is ion channeling. To accomplish this end, shallow profile halo doping processes often used a so-called “pre-amorphization” implantation step before the actual halo dopant implantation. In particular, an amorphous zone is usually formed during a first single pre-amorphization implantation and, during a subsequent implantation process (comprising either a single step or a plurality of steps), the doped regions (halo and source/drain extension regions) are formed. Normally, heavy inert ions like germanium or xenon are implanted at an implant energy of approximately 80-200 keV to fully amorphize the surface region of the substrate.
In the following, a description will be given with reference to
A typical process flow for forming the active regions of the transistor 100 comprising the amorphous regions 5 a, the halo structures 5 h, and the source and drain regions 5S and 5D may include the following steps.
Following the formation of the gate insulation layer 6 and the overlying polysilicon line 3 according to well-known lithography and etching techniques, the amorphous regions 5 are formed during a first step (see
It has been observed that at a predefined implanting dose, local amorphous regions are created by the ions penetrating into the substrate, which eventually overlap as the implanting process is carried out until a continuous amorphous layer is formed.
This amorphous layer is formed with the purpose of controlling ion channeling during the next implanting steps so as to obtain shallow implanting profiles for both the halo regions and the source and drain regions to be formed in the substrate. That is, the implanted ions do not penetrate in an amorphous layer as deeply as in a crystalline layer so that the implanted ions can be confined to shallower regions and the actual doping profile and final dopant concentration of those regions implanted after the pre-amorphization implantation step can be better controlled.
In a next step, as depicted in
The halo regions 5 h of the transistor 100 are then formed during a subsequent step, as depicted in
During a subsequent step, the source and drain regions 5S and 5D of the transistor 100 are completed, as depicted in
As stated above, the pre-amorphization implanting process as depicted in
However, the prior art pre-amorphization process as depicted with reference to
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or at least reduce one or more of these problems. In particular, it would be desirable to provide a technique that allows the prevention and/or reduction of ion channeling during halo implantation and source and drain implantation processes.
In general, the present invention is based on the consideration that ion channeling may be prevented or reduced and a shallow doping profile for optimum transistor design may be obtained by performing a two-step damaging and amorphizing implantation. For example, by performing a first light ion damaging implantation step, a good confinement of the subsequent halo implantation may be obtained. In particular, it has been observed that the crystal damage induced during a first light ion implantation step enables good confinement of the following halo implantation. Moreover, amorphizing the substrate during a subsequent heavy ion implantation may be performed to substantially suppress the channeling, reduce the dopant diffusion and improve the activation layer of the following source/drain and source/drain extension implants. It is, therefore, not necessary to use very high doses (above 1014 cm−2) to fully amorphize the substrate.
According to one embodiment, the present invention relates to a method of amorphizing a crystalline substrate. The method comprises implanting ions of a first dopant material through a surface of the substrate during a first implantation step so as to produce isolated crystal damage into the substrate to a first predefined depth. Moreover, the method comprises implanting ions of a second dopant material through the surface of the substrate during a second implantation step so as to substantially amorphize the substrate to a second predefined depth that is less than said first predefined depth.
According to another embodiment, the present invention relates to a method of forming at least one field effect transistor on a semiconductor substrate. The method comprises forming at least one gate structure above an active region of the transistor and implanting ions of a first dopant material during a first implantation step through the surface of the substrate not covered by the gate structure so as to produce isolated crystal damages into the substrate to a first predefined depth. The method further comprises implanting ions of a second dopant material during a second implantation step through the surface of the substrate not covered by the gate structure so as to substantially amorphize the substrate to a second predefined depth that is less than said first predefined depth.
According to a further embodiment of the present invention, a method of forming at least one field effect transistor on a semiconductor substrate is provided. The method comprises forming at least one polysilicon gate structure above an active region of the transistor and implanting ions of a first dopant material during a first implantation step through the surface of the substrate not covered by the gate structure so as to produce isolated crystal damage into the substrate to a first predefined depth. Moreover, the method comprises implanting ions of a first predefined conductivity type during a second implantation step through the surface of the substrate not covered by the gate structure so as to form halo structures into the portions of the substrate containing the crystal damages, and also comprises implanting ions of a second dopant material during a third implantation step into the halo structures so as to substantially amorphize the substrate to a second predefined depth which is less than the first predefined depth and less than the depth of the halo structures. Furthermore, the method comprises implanting ions of a second predefined conductivity type opposed to the first conductivity type during a fourth implantation step into the amorphized substrate.
According to a further embodiment, the present invention relates to a method of forming at least one active region in a crystalline substrate. The method comprises implanting ions of a first dopant material during a first implantation step through at least one portion of the surface of the substrate so as to produce isolated crystal damage into at least one portion of the substrate to a first predefined depth and implanting ions of a first predefined conductivity type during a second implantation step through the portion of the surface so as to form halo structures into the portion of the substrate containing the damage. The method further comprises implanting ions of a second dopant material during a third implantation step into the halo structures so as to substantially amorphize the substrate to a second predefined depth which is less than the first predefined depth and less than the depth of the halo structures. Moreover, the method comprises implanting ions of a second predefined conductivity type opposed to the first conductivity type during a fourth implantation step into the amorphized substrate.
The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present invention will now be described with reference to the attached figures. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and doped regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present invention is understood to be of particular advantage when used for forming the active regions of field effect transistors. For this reason, examples will be given in the following in which corresponding embodiments of the present invention are applied to the formation of the active regions of a field effect transistor. However, it has to be noted that the use of the present invention is not limited to the formation of the active regions of field effect transistors, but rather the present invention can be used in any other situation in which the realization of shallow doping profiles in a substrate and/or a workpiece is required. The present invention can be carried out in all those situations in which it is required to control the ion channeling during ion implantation steps with the purpose of forming well-confined doping profiles exhibiting a reliable dopant-concentration as well as shallow doping profiles. The present invention can be carried out in all those situations in which optimum design of doped regions in a substrate is required. The present invention is therefore applicable in these situations and the source and drain regions of a field effect transistor described in the following illustrative embodiments are to represent any such portion and/or region of a substrate.
With reference to
The manufacturing process for the formation of the active region of the transistor 100 as depicted in
During a first implanting step according to the present invention, a light ion implantation step is performed for the purpose of implanting ions deep into the silicon substrate so as to induce crystal damages and/or non-overlapping amorphous regions to a predefined depth into the substrate 1. Typical implant elements are silicon or argon at an implant energy higher than 15 keV. It has already been observed that approximately 10% of crystal damage heavily reduces the channeling of subsequently implanted dopants. It is therefore not necessary to use very high doses of dopants (above 1014 cm−2) to fully amorphize the substrate. However, even if the substrate is not fully amorphized during the light ion damaging implantation step, the crystal damages induced allow a good confinement of halo implantation that follows so that shallow halo structures exhibiting an optimum profile tailoring may be realized. The light ion damaging implanting step can be performed at zero degrees tilt angle or at a large tilt angle, as depicted in
Of course, in those circumstances in which the ion beam is kept at an approximately zero degree tilt angle with respect to the surface of the substrate, the substrate 1 does not need to be rotated 180 degrees and the implanting process does not need to be divided into two demi-periods.
Once the damaged regions 5 d have been formed as described above, the manufacturing process is continued to form halo regions into the substrate during the subsequent implantation step as depicted in
In the case in which the ion beam is kept approximately perpendicular to the surface of the substrate, the implanting step does not need to be divided into two segments, but an implanting process comprising a single implanting period can be carried out for the purpose of obtaining the desired final concentration of the halo regions 5 h. A tilt angle other than zero degrees may be used in those circumstances in which halo regions are needed extending considerably into the channel region of the field effect transistor 100, i.e., well beneath the polysilicon gate structure, and less in the vertical direction. In contrast, in those circumstances in which halo structures are needed extending considerably in the vertical direction and less in the horizontal direction, a perpendicular ion beam is preferred, i.e., an ion beam kept at an approximately zero degree tilt angle.
The halo regions 5 h prevent or at least reduce the short-channel effects, in particular the punch-through effect, in the transistor 100. The dopant concentration in the regions 5 h as well as the implant energy and the dopants are selected depending on the type of transistor to be formed on the substrate 1. For instance, boron ions in NMOS and phosphorous ions in PMOS are implanted to form a halo punch-through suppression region in each device. Usually, phosphorous is implanted at 90 keV with a dose of 2×1013 cm−2 at 25 degrees tilt, in two segments, with the substrate rotated 180 degrees between two segments. Similar procedures are used for implanting boron. A thermal treatment such as an annealing step is performed after the halo ion implantation step for diffusing the dopants into the substrate.
Due to the fact that the damaged regions 5 d have been previously formed, ion channeling during the halo implanting step can be better controlled. That is, implanting the halo dopants into the damaged regions 5 d results in halo structures 5 h being formed, exhibiting optimum doping profile tailoring. Moreover, the depth of the halo regions 5 h, i.e., the extension of the halo regions 5 h into the substrate can be better predefined and shallow halo structures can be obtained.
During a next implantation step, as depicted in
Usually, heavy inert ions like germanium or xenon are implanted during these amorphizing implanting steps at an implant energy typically below 150 keV. This implant step is used to suppress the channeling, reduce the dopant diffusion and improve the activation level of the following source/drain and source/drain extension implants. As is apparent from
The manufacturing process is then carried out to complete the transistor 100 according to techniques well known to those skilled in the art. In particular, during a next step, as depicted in
The source and drain regions 5S and 5D of the transistor 100 are then completed during a subsequent step, as depicted in
Once the source and drain regions 5S and 5D have been formed, the manufacturing process is continued to complete the transistor 100 according to techniques well known to those skilled in the art.
All implant steps as described with reference to
The advantage of using a two-step damaging and amorphizing implantation process according to the present invention is based on the fact that ion channeling can be reduced without fully amorphizing the substrate during a heavy ion implanting step. This is accomplished by pre-damaging the crystalline substrate during a first light ion implanting step and subsequently amorphizing the substrate to a depth that is less than a depth to which the substrate is damaged.
Damaging the substrate during a light ion implanting process results in the formation of isolated crystal damage and/or non-overlapping amorphous regions, thereby allowing the formation of shallow halo structures. Isolated crystal damages and/or not overlapping amorphous structures are locations and/or relatively small regions where the crystalline structure of the substrate is damaged and/or destroyed, that is, where the substrate atoms are displaced from their lattice site, due to the collisions (both nuclear and electronic) of the implanted ions against the substrate atoms.
The substrate can then be substantially fully amorphized to a reduced depth during a next heavy ion implantation step by inducing isolated damages and/or not overlapping amorphous regions to overlap so as to form a substantially continuous amorphous layer. Forming a continuous amorphous layer may act to reduce ion channeling during the subsequent ion implantation steps for forming the source and drain extension regions and the source and drain regions so that very shallow source and drain extension regions and source and drain regions can be formed exhibiting an optimum doping profile.
In other words, by performing the two-step damaging and amorphizing implantation process according to the present invention, shallow implant profiles may be obtained, but the substrate may not be fully amorphized to a large depth.
The manufacturing process is therefore simplified, the time-consuming prior art amorphizing implanting steps may be avoided, and manufacturing costs can be kept to a minimum.
It should also be noted that the present invention is not limited to the formation of the active regions of a field effect transistor, but can be used in all those cases in which ion channeling during ion implantation steps has to be prevented and the realization of a shallow implanting profile is required. The present invention does not need special equipment to be provided, but can be implemented in any usual manufacturing process without adding costs or complexity.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
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|U.S. Classification||438/525, 438/514, 257/E21.345, 438/96, 257/E21.336, 257/52, 438/373, 438/480, 438/527, 257/E21.335, 438/369, 257/64, 438/365, 257/63, 438/97, 257/538, 438/486|
|Cooperative Classification||H01L21/26586, H01L21/26506, H01L21/26513|
|European Classification||H01L21/265A, H01L21/265A2, H01L21/265F|
|May 19, 2003||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FEUDEL, THOMAS;HORSTMANN, MANFRED;STEPHAN, ROLF;REEL/FRAME:014103/0530;SIGNING DATES FROM 20021220 TO 20021223
|Sep 20, 2005||CC||Certificate of correction|
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