|Publication number||US6925505 B2|
|Application number||US 10/372,940|
|Publication date||Aug 2, 2005|
|Filing date||Feb 26, 2003|
|Priority date||Feb 26, 2003|
|Also published as||US20040168000|
|Publication number||10372940, 372940, US 6925505 B2, US 6925505B2, US-B2-6925505, US6925505 B2, US6925505B2|
|Original Assignee||Epo Science & Technology Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (4), Classifications (27), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method and a device for controlling data transmission and particularly to a control method and a control device for data transmission between IDE apparatuses.
2. Description of Related Art
Generally, an ordinary CD-ROM drive connects with a personal computer or IDE control device by way of IDE interface (Integrated Device Electronics Interface) to perform data transmission.
Once the data is ready to be transmitted, the IDE controller 10 of the IDE control device sends read control signal to the IDE apparatus 11 first via the signal control transmission line 31 to allow the IDE apparatus 11 outputting data via the data transmission line 33 and the output data being saved in the memory 102. Then, the IDE controller 10 sends write control signal to the IDE apparatus 12 to allow the output data being written in the IDE apparatus 12 from the memory 102 through the data transmission line 34.
The preceding conventional way for data transmission between IDE apparatuses is briefly in that the data of the IDE apparatus 11 is sent to the memory 102 first and then sent to the IDE apparatus 12 from the memory 102. Apparently, the conventional way provides a slower data transmission speed.
Further, U.S. Pat. No. 6,108,724 discloses a fast IDE driver to drive transfers, which allows an IDE controller to connect with a first-in-first-out transfer buffer. While the data is transmitted between the IDE apparatuses, the IDE controller makes output data from one of the IDE apparatuses being saved in the first-in-first-out transfer buffer temporarily instead of being saved in the master memory. Then, the output data is sent to another IDE apparatus via the first-in-first-out transfer buffer to enhance the speed of data transmission.
The crux of the present invention is to further enhance the speed of data transmission between IDE apparatuses.
Accordingly, a primary object of the present invention is to provide a method and a device for controlling data transmission between IDE apparatus and the method and the device can accelerate the speed of the data transmission between the IDE apparatuses substantially and the time for data transmission can be saved effectively.
The present invention can be more fully understood by reference to the following description and accompanying drawing, in which:
A control method of the present invention allows the IDE controller 40, such as an ALTERA EPM7032S or 7064S programmable chip, sends out a read control signal to IDE apparatus 41 via the IDE interface 51, the control transmission line 61 and the IDE interface 53 so that the data can be output through the data transmission line 402. The IDE controller 40 then sends out a write control signal to the IDE apparatus 42 via the IDE interface 52, the control transmission line 62 and the IDE interface 54 so that the output data from the IDE unit 41 can be written in through the data transmission line 402.
Further, the IDE controller 40 of the present invention can be connected to a memory bus 404 so as to connect a memory 405. A switch of the switch chip 403 can be controlled to allow the data being transmitted between the two IDE apparatuses 41, 42 and the memory 405 by way of the two data transmission lines 401, 402 and the memory bus 404.
301 The IDE controller sends read control signal to the IDE apparatus.
302 The IDE apparatus transmits output data to a data transmission line.
303 executing step 306 in case of the output data being not necessary to be saved in the memory, otherwise, executing next step.
304 The switch chip is controlled to allow the data transmission line being joined to the memory.
305 Save the output data in the memory and then executing step 308.
306 The IDE controller further sends a write control signal to another IDE apparatus within a time interval resulting from a cycle of read control signal;
307 Said another IDE apparatus receives the output data from the data transmission line and the output data is written in said another IDE apparatus.
308 The procedure of the present invention is finished.
It is appreciated that the present invention provides a method and a device for controlling data transmitted between IDE apparatuses via data transmission lines directly without the need of the data being saved in a memory or a first-in-first-out buffer in advance. Thus, the speed of data transmission can be enhanced tremendously and the data transmission between the IDE apparatuses and the memory can be performed by means of switch chip design.
While the invention has been described with reference to a preferred embodiment thereof, it is to be understood that modifications or variations may be easily made without departing from the spirit of this invention, which is defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5058004 *||Jan 19, 1990||Oct 15, 1991||Gonen Ravid||Computer gate control circuitry and apparatus to enable a single computer to simultaneously and selectively control a multiplicity of hard disk drives|
|US5446877 *||Jun 23, 1994||Aug 29, 1995||Nakamichi Peripherals Corporation||Method and apparatus for operation of a data archival apparatus allowing for coupling of the data archival device with an ide interface|
|US5649233 *||Aug 18, 1995||Jul 15, 1997||United Microelectronics Corporation||Apparatus for flexibly selecting primary and secondary connectors and master and slave cascaded disk drives of an IDE interface|
|US5867733 *||Jun 4, 1996||Feb 2, 1999||Micron Electronics, Inc.||Mass data storage controller permitting data to be directly transferred between storage devices without transferring data to main memory and without transferring data over input-output bus|
|US5964848 *||Jun 4, 1998||Oct 12, 1999||Elonex I.P. Holdings, Ltd.||Peripheral device control through integrated drive electronics|
|US6108724 *||May 29, 1997||Aug 22, 2000||Gateway 2000, Inc.||Fast IDE drive to drive transfers|
|US6535934 *||Sep 6, 2001||Mar 18, 2003||Ecrm, Incorporated||Transferring data from disk storage directly to a peripheral device|
|US6539442 *||Apr 10, 2000||Mar 25, 2003||Mitsumi Electric Co., Ltd.||Selecting a CD-ROM apparatus connected in cascade with a hard disk by a CD-ROM driver switching a drive selection bit in an IDE interface|
|US6606672 *||Aug 17, 2000||Aug 12, 2003||Mustek Systems Inc.||Single-chip-based electronic appliance using a data bus for reading and writing data concurrently|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7251709 *||Dec 3, 2003||Jul 31, 2007||Hitachi Global Storage Technologies Netherlands Bv||Storage device having a lateral storage director|
|US7730231 *||Sep 17, 2004||Jun 1, 2010||Harman Becker Automotive Systems Gmbh||Data transfer interface for a direct transfer of data from a first device to a second device|
|US20050114575 *||Sep 17, 2004||May 26, 2005||Pirmin Weisser||Data transfer interface|
|US20050125604 *||Dec 3, 2003||Jun 9, 2005||Williams Larry L.||Storage device having a lateral storage director|
|U.S. Classification||710/21, 710/31, 711/100, 710/72, 710/14, 710/33, 710/2, 710/64, 710/32, 710/61, 710/36, 710/74, 710/316, 710/20, 710/38, 710/8, 710/62|
|International Classification||G06F13/14, G06F13/40, G06F13/00, G06F13/38, G06F3/00, G06F3/06, G06F13/12, G06F3/02|
|Feb 26, 2003||AS||Assignment|
Owner name: EPO SCIENCE & TECHNOLOGY INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WANG, HONG-CHUAN;REEL/FRAME:013815/0790
Effective date: 20030212
|Feb 1, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Mar 20, 2013||REMI||Maintenance fee reminder mailed|
|Aug 2, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Sep 24, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130802