|Publication number||US6927160 B1|
|Application number||US 10/144,974|
|Publication date||Aug 9, 2005|
|Filing date||May 13, 2002|
|Priority date||Jun 9, 1999|
|Publication number||10144974, 144974, US 6927160 B1, US 6927160B1, US-B1-6927160, US6927160 B1, US6927160B1|
|Original Assignee||National Semiconductor Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (30), Non-Patent Citations (2), Referenced by (14), Classifications (19), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division of U.S. patent application Ser. No. 09/328,864, filed 9 Jun. 1999, now abandoned.
1. Field of the Invention
The present invention relates to semiconductor circuit manufacturing and, more specifically, to fabricating copper interconnects in an integrated circuit.
2. Discussion of the Related Art
The active devices of an integrated circuit are interconnected through the use of multilevel interconnects to form functional circuits and components. An example of a technique of forming such interconnects in a multilevel-interconnect system is shown in
Copper is a better conductor material than aluminum because of a lower resistivity, thus allowing higher current densities. Copper also shows a better electromigration resistance. However, copper cannot be etched conventionally. Copper damascene technology has thus been developed for forming copper interconnects.
A conventional copper damascene process is described in reference to
An additional problem caused by polishing off the portion of diffusion barrier 36 on top of dielectric layer 32 during the CMP process is heavy oxidation of the top surface of remaining copper layer 38 due to the oxidizing effect of CMP chemistry, and copper exposure to air. The oxidized copper undesirably increases via resistance. A further concern is contamination of dielectric layer 32 after the portion of diffusion barrier 36 on top of dielectric layer 32 is polished off because copper tends to migrate into the exposed dielectric layer 32.
A resist (not shown) is deposited and patterned to define contact regions. Dielectric layer 48, nitride layer 50 and second dielectric layer 52 are then etched to form vias 54, as shown in FIG. 9. The resist is removed. A second resist (not shown) is deposited and patterned to define interconnect regions. Dielectric layer 52 is etched selectively with respect to nitride layer 50, forming trenches 56, as shown in FIG. 10.
What is needed is a method to fabricate a copper interconnect which does not exhibit dishing, oxidized copper and contaminated dielectric.
The present invention provides a method of forming copper interconnects that do not exhibit dishing, oxidized copper and contaminated dielectric. A dielectric layer provided above a substrate is etched to form a trench that defines an interconnect region. A diffusion barrier is formed over the patterned dielectric layer and into the trench. A copper layer is then deposited over the diffusion barrier. A first portion of the copper layer is removed by chemical mechanical polishing (CMP) until the top surface of the diffusion barrier is exposed. A sputter etch removes (a) the material of the diffusion barrier overlying the dielectric layer and (b) the oxidized top surface of the copper layer to form a copper interconnect. The sputter etch prevents copper diffusion into the dielectric layer because, by uniformly removing (a) the material of the diffusion barrier overlying the dielectric layer and (b) the oxidized copper, the dielectric material is prevented from contacting the copper. In one embodiment, the sputter etch is performed by sputter etch equipment configured in situ with dielectric deposition equipment.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
Use of the same reference numbers in different figures indicates similar or like elements.
The present invention provides a method of forming interconnects that do not exhibit dishing, oxidized copper and contaminated dielectric. With reference to
Dielectric layer 102 is blanket deposited over substrate 100 by a well known technique, such as chemical vapor deposition (CVD). Dielectric layer 102 is made of, but not limited to, silicon dioxide (SiO2). The thickness of dielectric layer 102 is generally determined by the height of the interconnect desired. The final height of the interconnect is determined in the subsequent sputter etch which is discussed later. Dielectric layer 102 typically has a thickness of 4500 Å, depending on the processing environment, such as the product made and technology used.
A photoresist layer (not shown) is then formed over dielectric layer 102 and patterned to define the locations of the interconnects. The exposed portions of dielectric layer 102 are then etched to form interconnect trenches 104. After trenches 104 are formed, the photoresist layer is removed.
Next, diffusion barrier 106 is blanket deposited over patterned dielectric layer 102 and into trenches 104, to a thickness of, e.g., 300 Å. Diffusion barrier 106 prevents a subsequent copper layer from migrating into the underlying dielectric layer 102 and is made of a material such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), tungsten nitride (WNx), or tungsten silicide (WSix).
Copper layer 108 is blanket deposited, e.g., by an electro-plating process, over diffusion barrier 106 to a thickness of, e.g., approximately 6000 Å from the top of dielectric layer 102. The process up to this point is that of a conventional damascene process.
Next, referring to
Approximately 100 Å of overetch is performed to ensure complete removal of the portion of diffusion barrier 106 on top of dielectric layer 102 across the substrate. The sputter clean also removes damaged portions of the copper surface, i.e., the oxidized copper, and copper contaminants from dielectric layer 102.
In one embodiment, the sputter etch equipment is similar to conventional sputter etch equipment used for contact/via processes, for example, a sputter etch module developed by AMAT (e.g., Endura PC II based hardware). In another embodiment, the sputter etch equipment is configured in situ with a dielectric deposition equipment so that the portion of barrier film 106 on top of dielectric layer 102 is removed in the sputter module and the substrate is then transferred in vacuum to the dielectric deposition module for additional layers. The sputter etch hardware may be configured in situ to allow removal of any redeposited metals on the chamber walls.
A wafer is picked from load lock 207 and transferred under vacuum through transfer chamber 202 to sputter clean module 206 for barrier removal. After completion of the sputter etch, the wafer is transferred under vacuum through transfer chamber 202 to one of the deposition chambers 203 through 205.
A photoresist layer 118 is deposited over dielectric layer 116 and patterned to define the locations of the contacts. Dielectric layer 112, nitride layer 114 and dielectric 116 are then etched to form vias 120 over interconnects 110. Photoresist layer 118 is then removed.
The remaining steps are similar to those described above for
The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is defined in the following claims.
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|U.S. Classification||438/631, 438/637, 438/645, 438/700, 438/633, 438/692, 438/675, 438/695, 438/687, 438/760, 257/E21.583, 438/697, 438/959, 438/643|
|International Classification||H01L21/768, H01L21/28|
|Cooperative Classification||Y10S438/959, H01L21/7684|
|Feb 9, 2009||FPAY||Fee payment|
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