|Publication number||US6927480 B2|
|Application number||US 10/838,351|
|Publication date||Aug 9, 2005|
|Filing date||May 5, 2004|
|Priority date||May 8, 2003|
|Also published as||US20040222503|
|Publication number||10838351, 838351, US 6927480 B2, US 6927480B2, US-B2-6927480, US6927480 B2, US6927480B2|
|Inventors||Bau-Nan Lee, Cheng-Fen Chen, Chih-Wei Tsai, Chih-Pin Hung|
|Original Assignee||Advanced Semiconductor Engineering, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (12), Classifications (36), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to a multi-chip package, particularly to a multi-chip package with electrical interconnection by using a relay conductor.
A conventional multi-chip package includes a plurality of chips which are electrically connected to a leadframe and sealed inside a molding compound. The leads of leadframe cannot perform as the redistributed traces in the substrate that can be flexibly routed. When the plurality of chips share the same power source, ground plane or signal paths, it is practically not easy to connect the chips to a common lead through bonding wires so that the only way is to create extra traces routing in the outer printed circuit board to connect the common leads after surface-mounting the package.
R.O.C. Taiwan Patent No. 448,518 entitled “multi-chip package with leadframe” discloses a multi-chip package utilizing a leadframe. An internal substrate, such as a printed wiring board, is disposed inside the molding compound as an electrical interconnection between the leadframe and the plurality of chips. Therefore, electrical interconnection for common leads can be achieved without the need of redesigning the bonding pads of the chips. However, the internal substrate is attached to the leads of the leadframe and sealed inside the molding compound, the multi-chip package becomes thicker and the package cost becomes higher.
The main object of the present invention is to provide a multi-chip package with electrical interconnection, a dielectric carrier is provided to fix at least a relay conductor of a leadframe so that the relay conductor is placed on the dielectric carrier at a proper location and is electrically isolated from the leadframe as an interconnecting island of the plurality of bonding wires from the chips. Further, the relay conductor is electrically connected to the common lead of the leadframe by wire bonding. Electrical interconnection for common leads can be achieved, therefore, it is not necessary to place a conventional internal substrate inside the molding compound.
The secondary object of the present invention is to provide a multi-chip package with electrical interconnection. A relay conductor is placed on a dielectric carrier or in an opening of a leadframe to be electrically isolated from the leadframe for interconnecting a plurality of chips through bonding wires without redesigning and changing the original locations of bonding pads of the chips. Thus the length of the bonding wires will be shortened and the potential risk of wire sweep during molding will be reduced.
According to the present invention, the multi-chip package comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. The leadframe has a plurality of leads including at least a common lead. A dielectric carrier is attached to the leadframe, such as a chip pad of the leadframe. The relay conductor has a top surface and a bottom surface, the bottom surface of the relay conductor is attached to the dielectric carrier which makes the relay conductor is electrically isolated from the leadframe, and the top surface of the relay conductor is used for wireNbonding connection. The first chip and the second chip are disposed on the leadframe or on the dielectric carrier and each has an active surface and a back surface respectively. A plurality of first pads are disposed on the active surface of the first chip, and a plurality of second pads are disposed on the active surface of the second chip respectively. The bonding wires electrically connect the first chip to the leads and the second chip to the leads. The bonding wires include a first bonding wire, a second bonding wire and a third bonding wire, wherein the first bonding wire connects one of the first pads of the first chip to the top surface of the relay conductor, the second bonding wire connects one of the second pads of the second chip to the top surface of the relay conductor, and the third bonding wire connects the top surface of the relay conductor to the common lead. Finally, the first chip, the second chip, the bonding wires, and the relay conductor are encapsulated by the molding compound.
Referring to the drawings attached, the present invention will be described by means of the embodiments below.
In the first embodiment of the present invention,
Referring to FIG. 1 and
The leadframe 110 includes a plurality of leads 111 and a chip pad 112. In this embodiment, the leadframe 110 is a leadless leadframe such as quad flat non-leaded (QFN) leadframe or SON leadframe. As showed in
The relay conductor 130 has a top surface 131 and a bottom surface 132. The top surface 131 is used for connecting the first bonding wire 161, the second bonding wire 162 and the third bonding wire 163. The bottom surface 132 is attached to the dielectric carrier 120. The relay conductor 130 can be a metal island composed of iron or copper alloy.
In this embodiment, the first chip 140 is disposed on the dielectric carrier 120, and has an active surface 141 and an opposing back surface 142. The first chip, 140 has a plurality of first pads 143 on the active surface 141. At least one of the first pads 143 is a first common pad 143 a. The second chip 150 is disposed on the dielectric carrier 120, and has an active surface 151 and an opposing back surface 152. The second chip 150 has a plurality of second pads 153 on the active surface 151. At least one of the second pads 153 is a second common pad 153 a. The common lead 111 a is shared with the first common pad 143 a of the first chip 140 and the second common pad 153 a of the second chip 150 via the relay conductor 130.
In the multi-chip package 100, the plurality of bonding wires 160 are used to electrically connect the first chip 140 and the second chip 150 to the leads 111 of the leadframe 110. The bonding wires 160 include at least a first bonding wire 161, a second bonding wire 162 and a third bonding wire 163. The first bonding wire 161 connects the first common pad 143 a of the first chip 140 to the top surface 131 of the relay conductor 130. The second bonding wire 162 connects the electrical community second pad 153 a of the second chip 150 to the top surface 131 of the relay conductor 130. The third bonding wire 163 connects the top surface 131 of the relay conductor 130 to the common lead 111 a of the leadframe 110. Preferably, the first bonding wire 161, the second bonding wire 162, and the third bonding wire 163 are arranged in “Y” shape on the relay conductor 130. The first bonding wire 161 and the third bonding wire 163 can be integrated to be a single bonding wire having a knot on the relay conductor 130. By means of adjusting the location of the relay conductor 130, a flexible wire bonding path for electrical connection is provided to avoid interlacing the first, the second, the third bonding wire 161,162,163 and other bonding wires 160. In this embodiment, the molding compound 170 encapsulates the first chip 140, the second chip 150, the bonding wires 160, 161, 162, 163, the dielectric carrier 120 and the relay conductor 130. Moreover, the leads 111 have a plurality of bottom surfaces exposed, out of the molding compound 170 as outer connections of a leadless multi-chip package.
Therefore, in the foregoing multi-chip package 100, the relay conductor 130 is used as an interconnection island of bonding wires 161,162,163 to complete the electrical connections from the chips to the common leads 111 a. The relay conductor 130 can be located at any proper place on the dielectric carrier 120 and electrically isolated from the leadframe 110, it is not necessary to attach an internal substrate on the chip pad or to create extra redistributed traces on the chips. Accordingly, the multi-chip package 100 of the present invention has the advantage of replacing the conventional internal substrate inside a molding compound and of achieving a common electrical interconnection without altering the locations of the pads 143, 143 a, 153, 153 a of original chips 140, 150. The risk of wire sweep during molding can be greatly reduced due to shorter bonding wires.
According to the second embodiment of the present invention, the type of the leadframe and the relative position of the dielectric carrier and the chip pad of the leadframe are not particularly limited to use. Referring to
In the third embodiment of the present invention, the chip pad and the outer leads are not particularly limited to use in this invention. Referring to
The above description of embodiments of this invention is intended to be illustrated and not limited. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.
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|U.S. Classification||257/666, 257/E23.06, 257/E23.124, 257/E23.052, 257/E23.031, 257/E23.043, 257/E23.049, 257/784, 257/782|
|International Classification||H01L21/68, H01L21/56, H01L23/31, H01L23/495|
|Cooperative Classification||H01L2924/00014, H01L2924/181, H01L24/48, H01L2924/01039, H01L2224/48247, H01L23/3107, H01L21/568, H01L2224/48091, H01L23/49558, H01L2924/01029, H01L23/49541, H01L2924/01033, H01L2924/01006, H01L23/49575, H01L2924/01082, H01L2224/49171, H01L24/49|
|European Classification||H01L24/49, H01L23/31H, H01L21/56T, H01L23/495G6, H01L23/495L, H01L23/495G|
|May 5, 2004||AS||Assignment|
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, BAU-NAN;CHEN, CHENG-FEN;TSAI, CHIH-WEI;AND OTHERS;REEL/FRAME:015299/0587
Effective date: 20040412
|Feb 9, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Feb 11, 2013||FPAY||Fee payment|
Year of fee payment: 8