|Publication number||US6928027 B2|
|Application number||US 10/686,960|
|Publication date||Aug 9, 2005|
|Filing date||Oct 15, 2003|
|Priority date||Apr 11, 2003|
|Also published as||US20040202040, WO2004092966A1|
|Publication number||10686960, 686960, US 6928027 B2, US 6928027B2, US-B2-6928027, US6928027 B2, US6928027B2|
|Original Assignee||Qualcomm Inc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (25), Non-Patent Citations (1), Referenced by (7), Classifications (24), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Application Ser. No. 60/462,653, entitled “A Virtual Dual-Port Synchronous RAM Architecture,” filed Apr. 11, 2003.
1. Field of the Disclosure
The present disclosure relates generally to memory devices and, more particularly, to single-port memory devices.
2. Background of the Disclosure
The need to read and write simultaneously to a computer memory device is satisfied by dual-port memory devices; however, dual-port memory devices are relatively expensive compared to single-port memory devices. A single-port memory device, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), can either read or write during any specific time period, typically during a single clock cycle, but cannot read or write during a specific time period at the same time.
Other memory devices incorporate a single-port SRAM that utilizes separate read and write cycles from a clock. Other memory devices utilize a circuit with a dual port first-in and first-out (FIFO) memory stack, wherein the circuit includes a first and second bank and single-port RAMs to its data are written in alternation and, wherein each bank when not being written to is read from.
Other memory devices include a single-port memory which is used to store an image which can be read from and simultaneously written to. Separate read and write buffers communicate to an arbiter section, which in turn communicates with the single board memory.
Other memory devices simultaneously read and write data into a single-port RAM, wherein new data is stored in a corresponding new data address in a buffer, and a comparison is made of the new data address with a current read address. In the event that the read and write addresses are the same, the new data is stored at a modified address.
When two hosts from different clock regimes (i.e., clocks are asynchronous) want to access the same synchronous RAM, presently there are two architectures that may be utilized. The first architecture may utilize a dual-port synchronous RAM. Control logic needed for a dual-port synchronous RAM may be relatively simple, but the disadvantage of this architecture is that the dual-port synchronous RAM is bigger and more expensive than a single-port synchronous RAM. In addition, some manufacturers may not support a dual-port synchronous RAM in the end product.
Another architecture may utilize a single-port synchronous RAM wherein the single-port synchronous RAM is connected to a clock port to one host's clock. The other host's signals need to be synchronous to the first host's clock; then the synchronous control/data signals from both hosts would pass through an arbitration block, which decides which host would have the right to access the RAM. The problem of this architecture and method is that the clock connecting to the RAM would always be required to be on. Otherwise, if the first host's clock is turned off, the other host could not access the RAM. The other shortcoming of this architecture and method is the delay that would be introduced and the extra hardware that would be required by the synchronization and arbitration requirements.
What is needed is a system and method to accommodate asynchronous hosts that want to access the same RAM at the same time.
Disclosed is a read/write memory device including means to accept signals from a first host and a second host, the first host having a first clock and the second host having a second clock, the signals including a first clock signal and a second clock, a clock switching means for switching between the first clock signal and the second clock signal, a single-port random access memory (RAM) module for storing data, and a RAM clock for synchronizing the clock signals with the RAM module.
Also disclosed is a read/write memory system including a first host and a second host, the first host having a first clock generating a first clock signal and the second host having a second clock generating a second clock signal, a clock switching means for switching between the first clock signal and the second clock signal, a single-port random access memory (RAM) module for storing data, and a RAM clock for synchronizing the clock signals with the RAM module. The read/write memory system disclosed is not, however, limited to two hosts. The architecture disclosed herein may support multiple hosts, each with their respective clocks and the system having means to control access of one host at a time to the RAM.
Further yet, disclosed is a method for storing data in a memory device and for recalling the stored data therefrom including providing a first host and a second host, the first host having a first clock generating a first clock signal and the second host having a second clock generating a second clock signal, switching between the first clock signal and the second clock signal, allowing either the first host or the second host access to a single-port random access memory (RAM) module, and storing data to and recalling the stored data from the RAM module.
The disclosure will now be described in greater detail with reference to example embodiments illustrated in the accompanying drawings, in which like elements bear like reference numerals, and wherein:
In contrast, according to the present disclosure, a read/write memory device 32 provides a virtual dual-port synchronous RAM architecture with a single-port synchronous RAM module. The dual-port synchronous RAM architecture disclosed herein requires minimal hardware costs compared to the prior art. In addition, the virtual dual-port synchronous RAM architecture of the present disclosure provides a more efficient architecture which conserves battery power and therefore extends battery life in those instances where the device is powered by a battery.
The virtual dual-port synchronous RAM architecture is disclosed in
This is further illustrated in
In the virtual dual-port synchronous RAM architecture disclosed herein, the communications between the first host 34 and the second host 36 guarantee that the two hosts will not access the single-port synchronous RAM 52 at the same time. The clock switching unit 44 controls the RAM clock 50 so that the RAM clock 50 switches between the first clock 36 and the second clock 42, based on the signals from the first host 34 and the second host 40. Only one host is allowed access to the single-port synchronous RAM 52 to communicate with one host's address bus, data bus, and RAM control signals. The RAM access signals selection module 54 makes its decisions based on the corresponding host's requests. The access times of the two hosts are not overlapped since only one host accesses the single-port synchronous RAM 52 at a time.
Therefore, disclosed is a virtual dual-port synchronous RAM architecture which utilizes minimum hardware and therefore has reduced costs when compared to a dual-port RAM architecture. In addition, the virtual dual-port synchronous RAM architecture disclosed herein conserves battery power and therefore extends battery life.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the present disclosure. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3715729||Mar 10, 1971||Feb 6, 1973||Ibm||Timing control for a multiprocessor system|
|US4594657||Apr 22, 1983||Jun 10, 1986||Motorola, Inc.||Semaphore for memory shared by two asynchronous microcomputers|
|US4692886 *||Jan 24, 1985||Sep 8, 1987||Sony/Tektronix Corporation||Digital pattern generator|
|US5274678 *||Dec 30, 1991||Dec 28, 1993||Intel Corporation||Clock switching apparatus and method for computer systems|
|US5335931 *||Dec 14, 1992||Aug 9, 1994||Salomon S.A.||Ski having an upper face of variable width|
|US5414703 *||Dec 20, 1993||May 9, 1995||Kabushiki Kaisha Toshiba||Asynchronous cell switch|
|US5511209 *||Apr 16, 1993||Apr 23, 1996||Mensch, Jr.; William D.||Programmable microcomputer oscillator circuitry with synchronized fast and slow clock output signal|
|US5592434 *||Oct 25, 1995||Jan 7, 1997||Mitsubishi Denki Kabushiki Kaisha||Synchronous semiconductor memory device|
|US5614847 *||Aug 24, 1994||Mar 25, 1997||Hitachi, Ltd.||Semiconductor integrated circuit device having power reduction mechanism|
|US5941990 *||Oct 29, 1996||Aug 24, 1999||Nec Corporation||Semiconductor integrated circuit having voltage generation circuit driven by two different clock signals|
|US5996043 *||Jun 13, 1997||Nov 30, 1999||Micron Technology, Inc.||Two step memory device command buffer apparatus and method and memory devices and computer systems using same|
|US6002882 *||Nov 3, 1997||Dec 14, 1999||Analog Devices, Inc.||Bidirectional communication port for digital signal processor|
|US6262939 *||Mar 9, 2000||Jul 17, 2001||Nec Corporation||Semiconductor integrated circuit device|
|US6349391 *||Oct 27, 1999||Feb 19, 2002||Resilience Corporation||Redundant clock system and method for use in a computer|
|US6415390 *||Jul 24, 2000||Jul 2, 2002||Micron Technology, Inc.||Method and apparatus for controlling the data rate of a clocking circuit|
|US6470439 *||Mar 8, 2001||Oct 22, 2002||Sharp Kabushiki Kaisha||FIFO memory control circuit|
|US6496940 *||Jun 7, 1995||Dec 17, 2002||Compaq Computer Corporation||Multiple processor system with standby sparing|
|US6570419 *||Apr 24, 2001||May 27, 2003||Hitachi, Ltd.||Semiconductor integrated circuit having a clock recovery circuit|
|US6650637 *||Dec 14, 1998||Nov 18, 2003||Lucent Technologies Inc.||Multi-port RAM based cross-connect system|
|US6652536 *||Jun 19, 2002||Nov 25, 2003||Primus Medical, Inc.||Snare with anti-skewing|
|US6724686 *||Jan 10, 2003||Apr 20, 2004||Renesas Technology Corp.||Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode|
|US6772278 *||Dec 12, 2001||Aug 3, 2004||Kabushiki Kaisha Toshiba||Data transfer system and data transfer method|
|US6814295 *||Apr 20, 2001||Nov 9, 2004||Koninklijke Philips Electronics N.V.||Frequency sensor for each interface of a data carrier|
|US20020135408 *||Jan 16, 2001||Sep 26, 2002||Chiu Kenny Kok-Hoong||Method and interface for glitch-free clock switching|
|JPH0612313A *||Title not available|
|1||Oliver Aberth: A Multiple Computer Linkage: IEEE Transactions on Computers, vol. 18, No. 12 (1969).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8055936||Dec 31, 2008||Nov 8, 2011||Pitney Bowes Inc.||System and method for data recovery in a disabled integrated circuit|
|US8060453||Dec 31, 2008||Nov 15, 2011||Pitney Bowes Inc.||System and method for funds recovery from an integrated postal security device|
|US8514652||Mar 2, 2011||Aug 20, 2013||Lsi Corporation||Multiple-port memory device comprising single-port memory device with supporting control circuitry|
|US8531907||Jan 28, 2011||Sep 10, 2013||Infineon Technologies Ag||Semiconductor memory device and method|
|US8630143||Jul 17, 2013||Jan 14, 2014||Lsi Corporation||Multiple-port memory device comprising single-port memory device with supporting control circuitry|
|US20100165734 *||Dec 31, 2008||Jul 1, 2010||Sungwon Moh||System and method for data recovery in a disabled integrated circuit|
|US20100169240 *||Dec 31, 2008||Jul 1, 2010||Tolmie Jr Robert J||System and method for funds recovery from an integrated postal security device|
|U.S. Classification||365/189.14, 327/144, 327/152, 711/149, 326/93, 711/168, 711/169, 365/189.08, 711/158, 711/151, 711/150, 711/147, 365/189.03, 365/233.11, 365/189.02|
|International Classification||G11C7/10, G11C11/00, G06F13/16, G11C8/00|
|Cooperative Classification||G06F13/1663, G11C7/1075, Y02B60/1228|
|European Classification||G06F13/16A8S, G11C7/10T|
|Oct 15, 2003||AS||Assignment|
Owner name: QUALCOMM INCORPORATED, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, TAO;REEL/FRAME:014619/0892
Effective date: 20030916
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