|Publication number||US6928242 B1|
|Application number||US 09/689,758|
|Publication date||Aug 9, 2005|
|Filing date||Oct 13, 2000|
|Priority date||Oct 13, 2000|
|Publication number||09689758, 689758, US 6928242 B1, US 6928242B1, US-B1-6928242, US6928242 B1, US6928242B1|
|Inventors||Kevin Paul Demsky, Ladd William Freitag, Matthew James Paschal|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (2), Classifications (26), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the field of testing parallel optical communication transmitters.
2. Background Information
To test Bit Error Ratio (BER) on all channels of a parallel optical communication transmitter, all channels must be exercised. Such testing requires equipment that includes a single data generator and data detector, and they must be switched to each input and output of a laser driver chip until all channels are tested, or in the alternative the test equipment must include multiple data generator/detectors.
In an attempt to solve the problems described above, an on-chip parallel data generator, including a Built In Self Test (BIST) parallel data generator, is integrated into the transmitter so that all optical outputs may be switched synchronously. The BIST generator requires only one clock input which clocks the BIST generator for all channels. However, a problem still exists because when asynchronous BER testing is desired, the electrical inputs cannot be used for any other testing since the parallel inputs of the chip are ignored during BIST operation.
It is, therefore, a principle object of the this invention to provide a built-in self test method and circuit for parallel laser transmitters.
It is another object of the invention to provide a built-in self test method and circuit for parallel laser transmitters that solves the above-mentioned problems.
These and other objects of the present invention are accomplished by the built-in self test method and circuit for parallel laser transmitters that are disclosed herein.
Asynchronous crosstalk measurements are performed when a single channel input is provided by a single data generator and channels adjacent thereto are switching asynchronous to the single data generator. Crosstalk and noise problems may be measured qualitatively and quantitatively by using a BIST generator that generates a pseudo-random bit sequence on many channels as an on-chip noise source. Furthermore, while in BIST mode, any combination of channels may switch at a rate determined by a BIST input clock, or held quiet at a static 0 or 1 for a DC coupled product. This is advantageous while analyzing parameters that are sensitive to noise or crosstalk. Therefore, it is desired that the optical output of a channel responds to the electrical input of that channel, while other channels are running in BIST mode.
As a result, the complexity of testing is significantly reduced in comparison with conventional testing methods, as described in the example above, because only one data generator and one clock source are used. In the alternative, to reduce complexity of testing, fewer, or even no, switches that are capable of switching data at the full data rate, for example coaxial switches, are used. The reduction, or absence, of switches thus reduces complexity of testing. It also gives greater test coverage with only one data generator allowing the user to choose which optical outputs will output BIST data or external asynchronous data.
To that end, the present invention includes a BIST generator that is incorporated into a parallel optical transmitter. The parallel optical transmitter includes N laser driver channels in addition to the aforementioned BIST generator.
An external clock source is applied to the differential inputs of Channel N of the parallel optical transmitter. The external clock inputs are buffered by Channel N and applied to the clock input of the BIST generator. Control signal inputs EBIST and SBIST are used to put the transmitter array in BIST mode.
The external data inputs are applied to the inputs of a data receiver and a signal detector. The signal detector determines if a signal with a valid common mode voltage level is present on the Tx inputs. The data receiver buffers the Tx inputs, and the outputs of the data receiver are connected to a multiplexer input. The BIST generator outputs are applied to a buffer before being connected to the B inputs of the multiplexer. A logic block controls which of two multiplexer inputs is passed by the multiplexer to the inputs of a laser driver. The laser driver then converts the differential input to a single ended current to drive the laser. Thus, the signal detector is connected in parallel with the data receiver and the output of the signal detector is passed to the multiplexer.
The combinations of EBIST, SBIST and SIGDET determines if the input data or BIST data gets passed to the laser driver. In particular, in the “hard BIST” (EBIST) mode, BIST signals are transmitted along all of Channels 0–N. On the other hand, in the “soft BIST” (SBIST) mode, if the signal detector determines the presence of a valid signal, the logic block makes the determination, based on a predetermined logic table, as to whether BIST data or real data is passed through the multiplexer to the inputs of the laser driver of that channel.
As an example, the signal detector is a pull-down detector. In operation, as the signal detector receives external data inputs, if a first node falls below a second node, the signal detection output goes low, indicating that a valid signal is not present, although any polarity may be produced by inverting the comparator inputs. If the external inputs are held low, a comparator of the signal detector indicates that a valid signal is not present.
Before beginning a detailed description of the invention, it should be noted that, when appropriate, like reference numerals and characters may be used to designate identical, corresponding or similar components in differing figure drawings. Further, in the detailed description to follow, example embodiments and values may be given, although the present invention is not limited thereto.
An external clock source 1 may be applied to the inputs of Channel N CHN, during BIST mode operation. Otherwise, the Channel N inputs are data. EBIST 11 and SBIST 12 are control signal inputs used to select the type of data that is passed to the laser driver, choosing from BIST data and external data. OR gate 7 enables the BIST generator 5. Thus, when EBIST and SBIST are 0, BIST generator 5 is disabled, as will be described further below regarding Logic Block 70 in
The combinations of EBIST, SBIST and SIGDET determines if the input data or BIST data gets passed to the laser driver. In particular, in the “hard BIST” (EBIST) mode, BIST signals are transmitted along all of Channels 0–N. On the other hand, in the “soft BIST” (SBIST) mode, if Signal Detector 40 determines the presence of a valid signal on the Tx inputs, Logic Block 70 allows Multiplexer 80 to pass the external data to the laser driver 90.
For example, if the receiver common mode is X volts, and the single ended amplitude of both inputs is Y volts, then the lowest voltage the incoming signal can reach is X−0.5Y volts. The other signal is at X+0.5Y volts. The midpoint of R1 and R2 is the average or common mode=X volts. If this common mode voltage ever falls below a common mode voltage threshold set by R5 and R6, the comparator 110 flips indicating that a signal with a valid common mode is not present. The preceding example only works with DC coupled inputs and with signals having a common mode that is high enough above ground to accommodate setting the common mode voltage threshold between ground and the lowest valid common mode including margins for common mode noise, comparator offset, ground bounce and tolerance in the threshold itself. If signals are too close to ground, the topology can easily be switched to a common mode pull up detector. In this case one would tie the differential inputs high (to VDD), to pass data to the output from the BIST generator 5 in
The following truth table gives only an example of how the logic block 70 of
TRUTH TABLE SBIST SIGDET EBIST LD 0 0 0 DISABLE 0 0 1 BIST 0 1 0 TX 0 1 1 BIST 1 0 0 BIST 1 0 1 BIST 1 1 0 TX 1 1 1 BIST
EBIST and SBIST are selected globally. SIGDET 45 in
This concludes the description of the example embodiments. Although the present invention has been described with reference to illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope and spirit of the principals of the invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without department from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6201829 *||Apr 3, 1998||Mar 13, 2001||Adaptec, Inc.||Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator|
|US6480308 *||Jun 1, 1999||Nov 12, 2002||Sony Corporation||Optical communication apparatus|
|US6549310 *||Jan 8, 1999||Apr 15, 2003||International Business Machines Corporation||Fiber optic data link module with built-in link diagnostics|
|US6564349 *||Feb 25, 2000||May 13, 2003||Ericsson Inc.||Built-in self-test systems and methods for integrated circuit baseband quadrature modulators|
|US6567198 *||Oct 22, 1999||May 20, 2003||Samsung Electronics Co., Ltd.||Wavelength stabilizer in WDM optical transmission system|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7880477 *||Mar 1, 2007||Feb 1, 2011||Infineon Technologies Ag||Integrated circuit arrangement|
|US20080191710 *||Mar 1, 2007||Aug 14, 2008||Johann Peter Forstner||Integrated Circuit Arrangement|
|U.S. Classification||398/23, 365/201, 398/27, 398/194, 398/22, 398/195, 398/196, 398/16, 398/9, 398/182, 375/224, 398/10, 398/17, 398/186, 375/221, 398/197, 714/738, 375/219, 714/739, 714/733|
|International Classification||H04B10/08, H04B10/155|
|Cooperative Classification||H04B10/07, H04B10/50|
|European Classification||H04B10/07, H04B10/50|
|Oct 13, 2000||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DEMSKY, KEVIN PAUL;FREITAG, LADD WILLIAM;PASCHAL, MATTHEW JAMES;REEL/FRAME:011243/0977
Effective date: 20001006
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Owner name: INTELLECTUAL DISCOVERY, INC., KOREA, REPUBLIC OF
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