|Publication number||US6930524 B2|
|Application number||US 09/974,386|
|Publication date||Aug 16, 2005|
|Filing date||Oct 9, 2001|
|Priority date||Oct 9, 2001|
|Also published as||US6906566, US20030067015, US20030067331|
|Publication number||09974386, 974386, US 6930524 B2, US 6930524B2, US-B2-6930524, US6930524 B2, US6930524B2|
|Inventors||Adrian J. Drexler|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (47), Non-Patent Citations (5), Referenced by (13), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller 112 generates the DADJ signal in response to the DCONT signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCK−(D1+D2) as indicated in
In response to the new variable delay VD2, the next rising-edge of the CLKDEL signal occurs at a time T9. The CLKSYNC signal transitions high the delay D2 later at a time T10 and in synchronism with a rising-edge of the CLK signal. At this point, the delay-locked loop 100 is locked. In response to the positive-edge transition of the CLKDEL signal at the time T9, the CLKFB signal transitions high at a time T11 in synchronism with the CLKBUF signal. Once again, the phase detector 110 (
In the delay-locked loop 100, each cycle of the CLK signal the phase detector 110 compares rising-edges of the CLKBUF and CLKFB signals and generates the appropriate DCONT signal to incrementally adjust the variable delay VD until the delay-locked loop 100 is locked. The phase detector 110 could also compare falling-edges of the CLKBUF and CLKFB signals, as in the previously mentioned Manning patent. In this way, the delay-locked loop 100 incrementally adjusts the variable delay VD once each cycle of the CLK signal. Although the example of
In the delay-locked loop 100, the variable delay line 102 typically is formed from a number of serially-connected individual delay stages, with individual delay stages being added or removed to adjust the variable delay VD, as will be understood by those skilled in the art. For example, a plurality of serially-connected inverters could be used to form the variable delay line 102, with the output from different inverters being selected in response to the DADJ to control the variable delay VD. A large number of stages in the variable delay line 102 is desirable with each stage having an incremental delay to provide better resolution in controlling the value of the variable delay VD. In addition, the variable delay line 102 must be able to provide the maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the delay-locked loop is designed to operate. This is true because the variable delay line 102 must provide a variable delay VD of NTCK−(D1+D2), which will have its largest value when the period of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal. The desired fine resolution and maximum variable delay VD that the variable delay line 102 must provide can result in the delay line consisting of a large number of individual delay stages that consume a relatively large amount of space on a semiconductor substrate in which the delay-locked loop 100 and other components of the synchronous memory device are formed. Moreover, such a large number of individual delay stages can result in significant power consumption by the delay-locked loop 100, which may be undesirable particularly in applications where synchronous memory device is contained in a portable battery-powered device.
There is a need for a delay-locked loop that occupies less space on a semiconductor substrate, consumes less power, and more quickly locks on an applied clock signal.
According to one aspect of the present invention, a delay-locked loop, includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a frequency of the input clock signal. A variable delay circuit is coupled to the clock multiplier and generates a delayed clock signal responsive to the multiplied clock signal. The delayed clock signal has a delay relative to the multiplied clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit is coupled to the clock multiplier and to the variable delay circuit to generate the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal.
According to another aspect of the present invention, a delay-locked loop includes a variable delay circuit that receives an input clock signal and generates a delayed clock signal responsive to the input clock signal. The delayed clock signal has a delay relative to the input clock signal and the variable delay circuit controls the value of the delay responsive to a delay control signal. A comparison circuit is coupled to the variable delay circuit and generates the delay control signal in response to the relative phases of the rising-edge transitions of the delayed and input clock signals and in response to the relative phases of the falling-edge transitions of the delayed and input clock signals.
The delay-locked loop 300 includes the variable delay line 304, a feedback delay line 306, a phase detector 308, and a delay controller 310, all of which operate individually and in combination as previously described for the corresponding components in the conventional delay-locked loop 100 of FIG. 1. Thus, for the sake of brevity, the operation of these components will not again be described in detail. In the delay-locked loop 300, the clock multiplier 302 generates a multiplied clock signal MCLK in response to the CLK signal. The MCLK signal has a frequency FMCLK equal to a frequency FCLK of the CLK signal times 2^N, where N is an integer (ie., FMCLK=FCLK×2^N). In the embodiment of
An input buffer 310 develops a clock buffer signal CLKBUF in response to the MCLK signal. The input buffer 310 introduces an input buffer delay DIB, causing the CLKBUF signal to be delayed by the input buffer delay relative to the MCLK signal. The clock multiplier 302 also introduces a delay to the MCLK signal relative to the CLK signal. The delay introduced by the clock multiplier 302 plus the input buffer delay DIB introduced by the input buffer 310 together form the model delay component D1 in the feedback delay line 306. Although the clock multiplier 302 is shown connected before the input buffer 310 in the embodiment of
In the delay-locked loop 300, a clock divider 312 receives the CLKDEL signal and generates a divided clock signal DVCLK having the frequency FCLK of the CLKDEL signal. Thus, in the embodiment of
An output buffer 316 generates a synchronized clock signal CLKSYNC signal in response to the CDVCLK signal, the CLKSYNC being synchronized with the CLK signal. The output buffer 316 introduces an output buffer delay DOB, causing the CLKSYNC signal to be delayed by this amount relative to the CDVCLK signal. The output buffer delay DOB, along with delays introduced by the clock divider 312 and phase detection and correction circuit 314, form the D2 component of the model delay D1+D2 generated by the feedback delay line 306. As illustrated by a dotted line in
The operation of the delay-locked loop 300 will now be briefly described with reference to the signal timing diagram of
The delay-locked loop 300 adjusts the delay of the CLKDEL signal in response to both rising- and falling-edges of the CLK signal, enabling the delay-locked to more quickly lock the CLK and CLKSYNC signals. This is true because the delay-locked loop 300 adjusts the phase of CLKDEL signal more frequently (twice per period TCK of the CLK signal) to thereby lock the CLK and CLKSYNC signals. Moreover, since the frequency of the CLKBUF, CLKDEL, and CLKFB signals is twice the frequency FCLK of the CLK signal, the variable delay line 304 (
In operation, the phase detector 510 detects the phase difference between rising-edges of the CLKBUF and CLKFB signals and applies the corresponding RDCONT signal to the delay controller 514 which, in turn, generates the DADJ signal to adjust the variable delay VD of the CLKDEL signal. The phase detector 512 operates in the same way to detect the phase difference between falling-edges of the CLKBUF and CLKFB signals and applied the corresponding FDCONT signal to the delay controller 514 which, in turn, generates the DADJ signal to adjust the variale delay VD of the CLKDEL signal. The phase detectors 510, 512 and delay controller 514 operate in combination to adjust the delay of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero.
The operation of the delay-locked loop 500 will now be briefly described with reference to the signal timing diagram of
The memory device 800 includes an address register 802 that receives row, column, and bank addresses over an address bus ADDR, with a memory controller (not shown) typically supplying the addresses. The address register 802 receives a row address and a bank address that are applied to a row address multiplexer 804 and bank control logic circuit 806, respectively. The row address multiplexer 804 applies either the row address received from the address register 802 or a refresh row address from a refresh counter 808 to a plurality of row address latch and decoders 810A-D. The bank control logic 806 activates the row address latch and decoder 810A-D corresponding to either the bank address received from the address register 802 or a refresh bank address from the refresh counter 808, and the activated row address latch and decoder latches and decodes the received row address. In response to the decoded row address, the activated row address latch and decoder 810A-D applies various signals to a corresponding memory bank 812A-D to thereby activate a row of memory cells corresponding to the decoded row address. Each memory bank 812A-D includes a memory-cell array having a plurality of memory cells arranged in rows and columns, and the data stored in the memory cells in the activated row is stored in sense amplifiers in the corresponding memory bank. The row address multiplexer 804 applies the refresh row address from the refresh counter 808 to the decoders 810A-D and the bank control logic circuit 806 uses the refresh bank address from the refresh counter when the memory device 800 operates in an auto-refresh or self-refresh mode of operation in response to an auto- or self-refresh command being applied to the memory device 800, as will be appreciated by those skilled in the art.
A column address is applied on the ADDR bus after the row and bank addresses, and the address register 802 applies the column address to a column address counter and latch 814 which, in turn, latches the column address and applies the latched column address to a plurality of column decoders 816A-D. The bank control logic 806 activates the column decoder 816A-D corresponding to the received bank address, and the activated column decoder decodes the applied column address. Depending on the operating mode of the memory device 800, the column address counter and latch 814 either directly applies the latched column address to the decoders 816A-D, or applies a sequence of column addresses to the decoders starting at the column address provided by the address register 802. In response to the column address from the counter and latch 814, the activated column decoder 816A-D applies decode and control signals to an I/O gating and data masking circuit 818 which, in turn, accesses memory cells corresponding to the decoded column address in the activated row of memory cells in the memory bank 812A-D being accessed.
During data read operations, data being read from the addressed memory cells is coupled through the I/O gating and data masking circuit 818 to a read latch 820. The I/O gating and data masking circuit 818 supplies N bits of data to the read latch 820, which then applies two N/2 bit words to a multiplexer 822. In the embodiment of
During data write operations, an external circuit such as a memory controller (not shown) applies N/2 bit data words DQ, the strobe signal DQS, and corresponding data masking signals DM0-X on the data bus DATA. A data receiver 828 receives each DQ word and the associated DM0-X signals, and applies these signals to input registers 830 that are clocked by the DQS signal. In response to a rising edge of the DQS signal, the input registers 830 latch a first N/2 bit DQ word and the associated DM0-X signals, and in response to a falling edge of the DQS signal the input registers latch the second N/2 bit DQ word and associated DM0-X signals. The input register 830 provides the two latched N/2 bit DQ words as an N-bit word to a write FIFO and driver 832, which clocks the applied DQ word and DM0-X signals into the write FIFO and driver in response to the DQS signal. The DQ word is clocked out of the write FIFO and driver 832 in response to the CLK signal, and is applied to the I/O gating and masking circuit 818. The I/O gating and masking circuit 818 transfers the DQ word to the addressed memory cells in the accessed bank 812A-D subject to the DM0-X signals, which may be used to selectively mask bits or groups of bits in the DQ words (i.e., in the write data) being written to the addressed memory cells.
A control logic and command decoder 834 receives a plurality of command and clocking signals over a control bus CONT, typically from an external circuit such as a memory controller (not shown). The command signals include a chip select signal CS*, a write enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*, while the clocking signals include a clock enable signal CKE* and complementary clock signals CLK, CLK*, with the “*” designating a signal as being active low. The command signals CS*, WE*, CAS*, and RAS* are driven to values corresponding to a particular command, such as a read, write, or auto-refresh command. In response to the clock signals CLK, CLK*, the command decoder 834 latches and decodes an applied command, and generates a sequence of clocking and control signals that control the components 802-832 to execute the function of the applied command. The clock enable signal CKE enables clocking of the command decoder 834 by the clock signals CLK, CLK*. The command decoder 834 latches command and address signals at positive edges of the CLK, CLK* signals (i.e., the crossing point of CLK going high and CLK* going low), while the input registers 830 and data drivers 824 transfer data into and from, respectively, the memory device 800 in response to both edges of the data strobe signal DQS and thus at double the frequency of the clock signals CLK, CLK*. This is true because the DQS signal has the same frequency as the CLK, CLK* signals. The memory device 800 is referred to as a double-data-rate device because the data words DQ being transferred to and from the device are transferred at double the rate of a conventional SDRAM, which transfers data at a rate corresponding to the frequency of the applied clock signal. The detailed operation of the control logic and command decoder 834 in generating the control and timing signals is conventional, and thus, for the sake of brevity, will not be described in more detail.
It is to be understood that even though various embodiments and advantages of the present invention have been set forth in the foregoing description, the above disclosure is illustrative only, and changes may be made in detail, and yet remain within the broad principles of the invention. For example, many of the components described above may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate, may be realized through software executing on suitable processing circuitry. Therefore, the present invention is to be limited only by the appended claims.
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|U.S. Classification||327/158, 327/161|
|International Classification||H01L31/0328, H03L7/06, H03L7/087, H03L7/081|
|Cooperative Classification||H03L7/087, H03L7/0812|
|European Classification||H03L7/081A, H03L7/087|
|Oct 9, 2001||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DREXLER, ADRIAN J.;REEL/FRAME:012246/0906
Effective date: 20010925
|May 1, 2007||CC||Certificate of correction|
|Jan 15, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Jan 16, 2013||FPAY||Fee payment|
Year of fee payment: 8