|Publication number||US6930942 B2|
|Application number||US 10/901,183|
|Publication date||Aug 16, 2005|
|Filing date||Jul 29, 2004|
|Priority date||Jun 10, 2003|
|Also published as||CN1833293A, CN100466108C, DE602004018770D1, DE602004030733D1, EP1634301A1, EP1634301B1, EP2045817A1, EP2045817B1, US6795359, US20050002249, WO2004112049A1|
|Publication number||10901183, 901183, US 6930942 B2, US 6930942B2, US-B2-6930942, US6930942 B2, US6930942B2|
|Inventors||R. Jacob Baker|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (35), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 10/457,366, filed Jun. 10, 2003 (now U.S. Pat. No. 6,795,359), the subject matter of which is incorporated by reference herein.
The present invention relates to current measurement. For example, current may be measured to sense status of resistor-based memory devices such as magneto-resistive random access memory (MRAM) devices, which store logic values as resistive states of memory cells.
A MRAM device is one approach to implementing a resistance-based memory. In a MRAM each resistive memory cell typically includes a pinned magnetic layer, a sensed magnetic layer and a tunnel barrier layer between the pinned and sensed layers. The pinned layer has a fixed magnetic alignment, and a magnetic alignment of the sensed layer can be programmed to different orientations. The resistance of the cell varies, depending on the alignment of the sensed layer. One resistance value, e.g., a higher value, is used to signify a logic “one” while another resistance value, e.g., a lower value, is used to signify a logic “zero”. The stored data is read by sensing respective resistance values of memory cells and interpreting the resistance values thus sensed as logic states of the stored data.
For binary logic state sensing, the absolute magnitude of memory cell resistance need not be known, only whether the resistance is above or below a threshold value that is intermediate to the logic one and logic zero resistance values. Nonetheless, sensing the logic state of a MRAM memory element is difficult because the technology of the MRAM device impose multiple constraints.
A MRAM cell resistance is sensed at the column line of the addressed cell. In order to sense the cell, a row line connected to that cell is typically grounded while the remaining row lines and column lines are held at a particular voltage. Reducing or eliminating transistors from a memory cell tends to reduce the cell area requirements, increasing storage density and reducing costs. A cell of a crosspoint array, as discussed above, includes no transistors. This is achieved by allowing each resistive element to remain electrically coupled to respective row and column lines at all times. As a result, when a memory cell is sensed, it is also shunted by a significant sneak current path through the other memory cells of the addressed row line.
In a conventional MRAM device, the high resistance state has a resistance of about 1MΩ. An element in a low resistance state has a resistance of about 950 KΩ. The differential resistance between a logic one and a logic zero is, thus, typically about 50KΩ or about 5% of scale. Accordingly, a sensing voltage across a sensed MRAM device varies by about 5% of scale between the logic one and logic zero states.
One approach to sensing MRAM resistance is to integrate a current corresponding to sensing voltage over time, and to sample the resulting integrand voltage. This can be done by applying a voltage to an input of a transductance amplifier, and accumulating a current output by the amplifier with a capacitor.
A conventional sensing technique compares Vcap with Vref, allowing Vcap to increase until Vcap exceeds Vref and then discharging a capacitor until Vcap is again below Vref. Pulses indicating a comparison result can be counted to measure the sensing voltage, which, in turn, indicates an element's resistance state. Problems arise, however, when large counts accumulate during a sampling period.
The present invention provides techniques in which currents supplied to a capacitor during and discharging intervals are set to affect counts.
According to an exemplary embodiment of the present invention, an MRAM cell logic state is sensed by configuring a memory cell so as to form a sensing voltage across the cell that is related to a resistance of the cell. The sensing voltage is applied to an input of a transconductance amplifier, which outputs a sensing current related to the sensing voltage. The sensing current is integrated over time to measure the sensing voltage.
During integration, the sensing current is summed alternately with either a positive or a negative current. The positive current summed with the amplified sensing current charges the capacitor until it exceeds a reference voltage, and then the negative current summed with the amplified sensed current discharges the capacitor until it is again below the reference voltage. Pulses are provided periodically to a digital counter, with an UP count pulse provided when the capacitor exceeds the reference voltage, and a DOWN count pulse provided when the reference voltage exceeds that on the capacitor. By comparing the count value of the digital counter to a threshold value at a known time interval after initializing the counter, the logical state of the sensed MRAM cell can be ascertained. If the magnitude of positive current is maintained below the negative current, that is, Iup<Idown, then the range of the counter is improved by reducing the count over each sampling period.
These and other features and advantages of the invention will be more clearly understood from the following detailed description, which is provided in connection with the accompanying drawings.
In an exemplary embodiment of the present invention a signal representing a programmed resistance state of a resistive memory cell is received at an amplifier coupled to a capacitor. The capacitor is further coupled to a comparator coupled to a reference voltage source and controlled by a clock. The output of the comparator is coupled to a pair of switches. A first switch connects a positive current source to the capacitor and a second switch connects a negative current source to the capacitor. The comparator output could alternatively be connected to a single switch that connects to both positive and negative current sources and is switchable between the positive and negative current sources. The positive current integrated with the sensing current from the amplifier charges the capacitor and the negative current integrated with the sensing current discharges the capacitor. The outputs of the comparator are further coupled to an UP/DOWN counter also controlled by a clock. The current source circuit includes the positive current source, the negative current source and the switches. The amount of positive current is kept below the amount of negative current, that is, Iup<Idown. The UP/DOWN counter contains a digital value acquired over a sampling period for the memory cell.
A power supply (not shown) provides a source of electrical voltage that maintains the various electrical potentials at which the circuit operates. The power supply defines three potentials including a ground potential 20, an operating voltage Vcc for the circuit elements, and the voltage Va 24 connected as indicated above. In one implementation, the voltage Va 24 is approximately 5 volts.
As illustrated, sneak path memory cells, e.g., 34, 40, 42, 44, 46, forming a subset of the plurality of memory cells 14, are connected between the column line 30 and a respective plurality of row lines 6. Each row line 6, except for the one connected to sensed cell 38, is grounded by a respective switching device 51. Thus a voltage divider is formed by the parallel combination of sneak path cells, e.g., 34, 40, 42, 44, 46 connected in series with the particular resistance cell 38 being sensed. Column line 30 defines a sensing node between the sneak path cells and the sensed cell 38. The sensing voltage at column line 30 is coupled to the sensing circuit 130.
In one embodiment, the resistance of selected resistive memory cell 38 ranges from about 900KΩ to about 1.1MΩ. In various embodiments prepared using current technology, memory cell resistance may be found in a range from about 900KΩ to about 1MΩ in the low resistance state and from about 950KΩ to about 1.1MΩ in the high resistance state. In a particular device, the low and high ranges do not overlap. It is understood that advances in the technology of the resistive cell may yield different resistance values to which the present invention may nonetheless be effectively applied.
A noise shaping based sensing amplifier used in a MRAM to sense the voltage and thus the logic state of a memory cell results in an inherent offset. For example, in the low resistance state, the input voltage to the sense amplifier may be 1.992 mV and in the high resistance state, the input voltage may be 2.212 mV. The actual signal to be sensed is the difference between these two voltages or about 220 μV. Sensing circuit 130 reduces or eliminates the offset from the data (input voltages), that is, the roughly 2 mV common to both input voltages.
Because the output of the sense amplifier is a series of UPs and DOWNs to a counter, reduction or elimination of the offset can reduce the size of the counter used to count the number of UPs and DOWNs. In general the counter must be large enough to count the maximum and minimum values that can occur in a sampling period. For example, the UP counts correspond to increasing the value in the counter by one (+1) and DOWN counts correspond to decreasing the value in the counter by one (−1). The sequence 1 1 1 −1 1 −1 then corresponds to an average of (4−2)/6 or ⅓. Reducing the offset has the effect of reducing the maximum value that occurs in a sampling period, which is three in this example because of the initial string of three 1's.
At the end of the sampling period, the count value indicates the proportion of the sampling period during which Vcap exceeded Vref, and this, in turn, is a measure of Vin. The count value need not, however, be equal to the indicated proportion; for example, the offset can be reduced so that a count of zero indicates the proportion when at high resistance and a higher non-zero count indicates the proportion when at low resistance.
Compensation for the offset can be accomplished by adjusting bias currents used in the sense amplifier. A positive bias current provided while the capacitor is charged can be set below a negative bias current provided during discharge. For a typical sense amplifier to function properly, the average of the positive and negative bias currents must equal the input current. That is, ginVin=average of Iup and Idown.
Comparator 426 has two outputs, where output 444 is shown with an inverter to indicate that it is the negative (opposite logical state) of output 445. Alternatively, output 445 could be inverted to obtain output 444. The current source 430 is adapted to alternately supply or withdraw a current from the first capacitor plate 420 according to the state of a pair of switches 464, 466, which are open or closed depending upon a feedback to each switch from the comparator 426. Both switches cannot be closed concurrently. The clocked comparator further includes a second input 438 adapted to be maintained at a reference voltage Vref by a reference voltage source 440 and a clock input 442 adapted to receive a clock signal CLKcmp. The outputs 444, 445 of comparator 426 are coupled to switches 464, 466, which could be transistors that control connection of Iup (positive) and Idown (negative) current of the current source circuit 430 to first capacitor plate 420. Switch 464 is coupled to output 444 of comparator 426 and switch 466 is coupled to output 445 of comparator 426. Outputs 444, 445 of the comparator are further coupled to UP/DOWN inputs 446, 447 respectively of a clocked counter 448. The clocked counter includes a clock input 450, a preset input 452 and a digital count output 454 including a plurality of digital output lines 456.
In operation, a preset voltage is established across capacitor 422 by the analog preset circuit 434. A digital preset value is established at the output 454 of counter 448 by a signal transition applied at the digital preset input 452.
Assuming that the preset voltage on the capacitor 422 is less than the reference voltage Vref applied at the second input 438 of the comparator 426, the inverted output 444 of the comparator 426 will apply a corresponding UP input at the input 446 of the digital counter 448 as soon as the clock input 442 of the comparator 426 receives a clock signal transition. The outputs 444, 445 of the comparator are also applied to both switches 464, 466 respectively of the current supply circuit 430. Accordingly, while Vcap<Vref switch 464 is closed and switch 466 is open and the charging current to capacitor 422 is Iin+Iup. Then, when Vcap>Vref, outputs 444 and 445 open switch 464 and close switch 466 respectively so that the discharge current from capacitor 422 is Iin−Idown.
The voltage on the capacitor 422 rises above the voltage threshold defined by the reference voltage Vref applied at input 438 of comparator 426. Thereafter, the voltage on capacitor 422 continues to rise until a clock transition is detected at clock input 442 of comparator 426. Upon detection of a clock transition, the logical state of the outputs 444 and 445 of comparator 426 toggle (e.g., from “0” to “1” after inversion of output 444 and from “1” to “0” at output 445) and apply a corresponding UP input at the input 446 of the digital counter 448. Responsively, the current supply circuit 430 changes state to withdraw current from capacitor 422. As current is withdrawn from capacitor 422, the voltage on the capacitor falls to, and then below the reference voltage Vref level. Thereafter, when the clock signal at input 442 of comparator 426 transitions, the comparator output toggles again, but this time a DOWN signal is provided to input 447.
Counter 448 cyclically counts away from its preset value and back toward it. Consequently, the counter counts UP and DOWN during alternate charging and discharging intervals and the time average value of the digital counter or the value at the end of the sampling period should approximate one of two values—a high value for a low resistance and a low value for a high resistance.
As noted above, current 414 from the amplifier 412 adds with the currents 460, 462 from the current supply circuit 430 in accordance with the switches 464, 466 being open or closed. Without the bias current supplied by the current supply circuit 430, the sense of the current 414 out of the amplifier 412 tends to charge capacitor 422 so that capacitor 422 charges more quickly than it discharges. Consequently, more rising transitions of the comparator clock signal occur while the voltage on capacitor 422 exceeds Vref than while it is less than Vref. In some instances, the voltage on capacitor 422 will rise to the point where the discharge that occurs during one clock interval is insufficient to bring the voltage of the capacitor 422 below the reference voltage. Consequently, the voltage on the capacitor is above the reference voltage for multiple consecutive rising transitions of the clock.
Current source circuit 430 has two current sources 460, 462 which are manufactured so that certain currents are provided. Current sources 460, 462 can, for example, be switches that are always on, providing fixed currents. That is, current sources 460, 462 can be implemented as circuits that include one or more transistors that are always on such as followers. Alternatively, circuits could be used in which it is possible to control the current by changing the voltage on a transistor's gate.
Using current source circuit 430 in which the magnitude of Iup (positive) current is below the magnitude of Idown (negative) current reduces the average of the number of UPs and DOWNs input to the counter per sampling period and thus the size (number of bits required) of the counter can be reduced. This gives the counter a better overall range.
By adjusting the magnitudes of Iup (positive) and Idown (negative) current, the center point of both the sense amplifier and the counter can be moved. When adjusted optimally, the counter output will end up approximating zero. That is, Iup+ginVin≈Idown results in a centering of the counter so that the up/down counts for different resistance values all have smaller maximum and minimum values and, therefore, the counter can be made smaller.
For example, using an equal amount of Iup and Idown the counter output for a logical zero (0) or high resistance might be 156 and the counter output for a logical one (1) or low resistance might be 180. Using unequal amounts of Iup and Idown the counter output for a logical zero (0) might be 0 and the counter output for a logical one (1) might be 24. A significantly smaller counter is required—a six bit counter may suffice where a nine bit counter might otherwise be necessary.
The memory controller 502 is also coupled to one or more memory buses 507. Each memory bus accepts memory components 508, which include at least one memory device 17 that includes sensing circuit 400. Each of the memory components 508 may be a memory card or a memory module. Examples of memory modules include single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). The memory components 508 may include one or more additional devices 509. For example, in a SIMM or DIMM, the additional device 509 might be a configuration memory, such as a serial presence detect (SPD) memory. The memory controller 502 may also be coupled to a cache memory 505. The cache memory 505 may be the only cache memory in the processing system. Alternatively, other devices, for example, processors 501 may also include cache memories, which may form a cache hierarchy with cache memory 505. If the processing system 500 include peripherals or controllers which are bus masters or which support direct memory access (DMA), the memory controller 502 may implement a cache coherency protocol. If the memory controller 502 is coupled to a plurality of memory buses 507, each memory bus 507 may be operated in parallel, or different address ranges may be mapped to different memory buses 507.
The primary bus bridge 503 is coupled to at least one peripheral bus 510. Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus 510. These devices may include a storage controller 511, a miscellaneous I/O device 514, a secondary bus bridge 515, a multimedia processor 518, and a legacy device interface 520. The primary bus bridge 503 may also coupled to one or more special purpose high speed ports 522. In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port (AGP), used to couple a high performance video card to the processing system 500.
The storage controller 511 couples one or more storage devices 513, via a storage bus 512, to the peripheral bus 510. For example, the storage controller 511 may be a SCSI controller and storage devices 513 may be SCSI discs. The I/O device 514 may be any sort of peripheral. For example, the I/O device 514 may be a local area network interface, such as an Ethernet card. The secondary bus bridge may be used to interface additional devices via another bus to the processing system. For example, the secondary bus bridge may be an universal serial port (USB) controller used to couple USB devices 517 via to the processing system 500. The multimedia processor 518 may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to one additional devices such as speakers 519. The legacy device interface 520 is used to couple legacy devices, for example, older styled keyboards and mice, to the processing system 500.
The processing system 500 illustrated in
While embodiments of the invention have been described in the illustrations above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. While the present invention has been described in terms of MRAM, it is not limited thereto but is applicable to, for example, PCRAM and other circuits in which signals are sensed at different levels. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims.
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|U.S. Classification||365/209, 365/158, 365/189.09|
|International Classification||G11C27/02, G11C11/16, G11C7/06|
|Cooperative Classification||G11C27/024, G11C11/16, G11C2207/061, G11C7/06|
|European Classification||G11C11/16, G11C27/02C, G11C7/06|
|Jun 6, 2006||CC||Certificate of correction|
|Jan 15, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Jan 16, 2013||FPAY||Fee payment|
Year of fee payment: 8