US 6938193 B1 Abstract In an ECC circuit of an ECC circuit-containing semiconductor memory device, an error correcting code/syndrome generating circuit and a data correcting circuit are disposed. In portions of the ECC circuit connected to buses, a data bus input control circuit for controlling input of a data from a data bus; an error correcting code bus input control circuit for controlling input of an error correcting code from an error correcting code bus; and an error correcting code bus output control circuit for controlling output of an error correcting code to the error correcting code bus are disposed. A portion corresponding to an error correcting code generator of a conventional technique is included in the ECC circuit, so that the ECC circuit can function both as an error correcting code generator and a decoder. As a result, the entire device can be made compact.
Claims(9) 1. An ECC circuit-containing semiconductor memory device comprising:
error correcting code generation means including a circuit having a function to generate an error correcting code consisting of plural bits on the basis of a data consisting of plural bits;
data storage means for storing said plural bits of said data;
error correcting code storage means for storing said plural bits of said error correcting code; and
decoding means including a circuit having a function to generate a syndrome for error correction by calculation processing on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, and a circuit having a function to correct an error of each bit of said data,
wherein the functions of said error correcting code generation means and said decoding means are carried out by a shared circuit such that said shared circuit generates said error correcting code and said syndrome,
said error correcting code generation means has a function to generate, in a test mode, a memory testing error correcting code such that a data row of said memory testing error correcting code has the same repeat pattern of a data row of said data on the basis of said data, and
said pattern includes, as arbitrary two bits, four types of patterns: (0 0) (0 1), (1 0) and (1 1).
2. The ECC circuit-containing semiconductor memory device of
3. An ECC circuit-containing semiconductor memory device comprising:
error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits;
data storage means for storing said plural bits of said data;
error correcting code storage means for storing said plural bits of said error correcting code;
decoding means having a function to correct an error of each bit of said data by calculating a syndrome for error correction on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means; and
data input control means for arbitrarily change, in a test mode, a value of each bit of said data supplied to said error correcting code generation means,
wherein said decoding means has a function to generate an arbitrary testing syndrome in the test mode.
4. An ECC circuit-containing semiconductor memory device comprising:
error correcting code generation means including a circuit having a function to generate an error correcting code consisting of plural bits on the basis of a data consisting of plural bits;
data storage means for storing said plural bits of said data;
error correcting code storage means for storing said plural bits of said error correcting code;
decoding means including a circuit having a function to generate a syndrome for error correction by calculation processing on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, and a circuit having a function to correct an error of each bit of said data; and
data input control means for changing, in a test mode, a value of each bit of said data supplied to said error correcting code generation means, into a value different from said value of each bit of said data,
wherein the functions of said error correcting code generation means and said decoding means are carried out by a shared circuit such that said shared circuit generates said error correcting code and said syndrome, and
said decoding means has a function to generate, in the test mode, a syndrome in such a pattern that no data bit is to be correspondingly corrected but any data bit is to be correspondingly corrected when any bit of said syndrome is inverted.
5. A method of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means including a circuit having a function to generate an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing said plural bits of said data, error correcting code storage means for storing said plural bits of said error correcting code, and decoding means including a circuit having a function to generate a syndrome for error correction by calculation processing on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, and a circuit having a function to correct an error of each bit of said data, said error correcting code generation means sharing a circuit with said decoding means, and said shared circuit having a function to generate said error correcting code and said syndrome, wherein the functions of said error correcting code generation means and said decoding means are carried out by a shared circuit such that said shared circuit generates said error correcting code and said syndrome, comprising the step of:
generating a memory testing data and a memory testing error correcting code in a pattern of the same type as a pattern of said memory testing data, including, as arbitrary two bits, four types of patterns in said patterns: (0 0), (0 1), (1 0) and (1 1), and writing said memory testing data in said data storage means and said memory testing error correcting code in said error correcting code storage means for testing said data storage means and said error correcting code storage means.
6. The method of testing an ECC circuit-containing memory device of
7. The method of testing an ECC circuit-containing memory device of
8. A method of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing said plural bits of said data, error correcting code storage means for storing said plural bits of said error correcting code, and decoding means having a function to correct an error of each bit of said data by calculating a syndrome for error correction on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, comprising the step of:
generating a memory testing data and a memory testing error correcting code each including, as arbitrary two bits, four types of patterns: (0 0), (0 1), (1 0) and (1 1).
9. A method of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing said plural bits of said data, error correcting code storage means for storing said plural bits of said error correcting code, and decoding means having a function to correct an error of each bit of said data by calculating a syndrome for error correction on the basis of said data stored in said data storage means and said error correcting code stored in said error correcting code storage means, comprising the step of:
generating an arbitrary testing syndrome by generating, from said data, a testing error correcting code in a pattern different from a pattern of said error correcting code.
Description The present invention relates to a semiconductor memory device containing an error correcting code circuit (ECC circuit). In accordance with recent increase in the storage capacity of a semiconductor memory device, the probability of failure occurring in any of memory elements included in the semiconductor memory device or the probability of error write and error read has been increased. Therefore, an ECC circuit-containing semiconductor memory device having a function to detect a data error from an electric signal and correct the detected error has been proposed. An ECC circuit has an error correcting function designed on the basis of a coding theory. An error is corrected through encoding as follows: Information to be originally transferred is sent with redundancy added in accordance with a given rule, and a receiver checks whether or not the received information accords with the rule, so as to detect and correct an error in accordance with the result of the check. Therefore, in an ECC circuit-containing semiconductor memory device, in order to improve its reliability, redundancy is added to digital information so as to be processed more easily and systematically with a machine. As an example of the conventional technique, an ECC circuit-containing semiconductor memory device and its operation disclosed in Japanese Laid-Open Patent Publication No. 5-54697 will now be described with reference to The I/O control circuit Now, an operation to write a data in the ECC circuit memory block First, in writing a data in the ECC circuit memory block Next, the error correcting code generator Formulas (1):
Next, in reading a data from the ECC circuit memory block Then, in order to correct an error of each bit of the read 8-bit data, the decoder At this point, the data corresponding to the bit string of the syndrome (namely, a test matrix H) is represented by the following Formula (2): Formula (2):
For example, when S The 8-bit data resulting from this error correction is output to the output data line In this manner, a data is written in or read from the ECC circuit memory block Next, the structure and the operation of another semiconductor memory device containing an ECC circuit designated as a second conventional example will be described. Since the ECC circuit of As is shown in In the circuit of Next, an operation in a test mode will be described. When the test mode signal On the other hand, an error correcting code, (C In this manner, in the ECC circuit-containing semiconductor memory device of the second conventional example, errors of two or more bits are corrected by testing memory cells included in the data storage area The first and second conventional examples, however, have the following problems: In the first conventional example, in the case where different test patterns (such as a checker pattern) should be respectively used for testing the data storage area and the error correcting code storage area, the test cannot be rapidly carried out. In the second conventional example, although test patterns can be variously changed, the area occupied by the entire semiconductor memory device is increased on the contrary. Therefore, it is difficult to sufficiently meet demand for compactness of electronic equipment including the semiconductor memory device. Furthermore, in the structure shown in An object of the invention is providing a semiconductor memory device containing an ECC circuit with a simplified structure which can exhibit high performance suitable to compactness of electronic equipment for mounting the semiconductor memory device, and providing a test method for improving the reliability of the ECC circuit-containing semiconductor memory device. The first ECC circuit-containing semiconductor memory device of this invention comprises error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits; data storage means for storing the plural bits of the data; error correcting code storage means for storing the plural bits of the error correcting code; and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, wherein the error correcting code generation means and the decoding means share a circuit. In this manner, an error correcting code generating circuit and a decoder, which are separately provided in the conventional technique, can be constructed by using the shared circuit. As a result, the semiconductor memory device can be made compact. The second ECC circuit-containing semiconductor memory device of this invention comprises error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits; data storage means for storing the plural bits of the data; error correcting code storage means for storing the plural bits of the error correcting code; and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, wherein the error correcting code generation means has a function to generate, in a test mode, a memory testing error correcting code in a pattern of the same type as a pattern of the data on the basis of the data. In this manner, the semiconductor memory device can be provided with a function to detect a defect or the like derived from interference or the like between adjacent memory cells in each storage means by generating a checker pattern and a stripe pattern without additionally preparing error correcting code patterns for memory test. The third ECC circuit-containing semiconductor memory device of this invention comprises error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits; data storage means for storing the plural bits of the data; error correcting code storage means for storing the plural bits of the error correcting code; decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means; and data input control means for arbitrarily change, in a test mode, a value of each bit of the data supplied to the error correcting code generation means, wherein the decoding means has a function to generate an arbitrary testing syndrome in the test mode. In this manner, a defect of the decoding means can be detected, resulting in further improving the reliability of the ECC circuit-containing semiconductor memory device. The fourth ECC circuit-containing semiconductor memory device of this invention comprises error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits; data storage means for storing the plural bits of the data; error correcting code storage means for storing the plural bits of the error correcting code; decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means; and data input control means for changing, in a test mode, a value of each bit of the data supplied to the error correcting code generation means, wherein the decoding means has a function to generate, in the test mode, a syndrome in such a pattern that no data bit is to be correspondingly corrected but any data bit is to be correspondingly corrected when any bit of the syndrome is inverted. In this manner, a defect of the error correcting code storage means can be detected. The first method of this invention of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing the plural bits of the data, error correcting code storage means for storing the plural bits of the error correcting code, and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, comprises the step of generating a memory testing data and a memory testing error correcting code in a pattern of the same type as a pattern of the memory testing data, and writing the memory testing data in the data storage means and the memory testing error correcting code in the error correcting code storage means for testing the data storage means and the error correcting code storage means. In this manner, the storage means can be tested by generating various patterns for detecting a defect of each storage means of the ECC circuit-containing semiconductor memory device without additionally preparing test patterns. In the first method of testing an ECC circuit-containing memory device, a defect derived from interference or the like between adjacent memory cells in each storage means by writing a checker pattern in the data storage means and the error correcting code storage means. The second method of this invention of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing the plural bits of the data, error correcting code storage means for storing the plural bits of the error correcting code, and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, comprises the step of generating a memory testing data and a memory testing error correcting code each including, as arbitrary two bits, four types of patterns: (0 0), (0 1), (1, 0) and (1 1). In this manner, defects of two or more bits included in a word can be detected. The third method of this invention or testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing the plural bits of the data, error correcting code storage means for storing the plural bits of the error correcting code, and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, comprises the step of generating an arbitrary testing syndrome by generating, from the data, a testing error correcting code in a pattern different from a pattern of the error correcting code. In this manner, a defect of the decoding means can be detected. The fourth method of this invention of testing an ECC circuit-containing semiconductor memory device including error correcting code generation means for generating an error correcting code consisting of plural bits on the basis of a data consisting of plural bits, data storage means for storing the plural bits of the data, error correcting code storage means for storing the plural bits of the error correcting code, and decoding means having a function to correct an error of each bit of the data by calculating a syndrome for error correction on the basis of the data stored in the data storage means and the error correcting code stored in the error correcting code storage means, comprises the step of generating, in a test mode, a syndrome in such a pattern that no data bit is to be correspondingly corrected but any data bit is to be correspondingly corrected when any bit of the syndrome is inverted. In this manner, a defect of the error correcting code storage means can be detected. Embodiment 1 Main peripheral circuits are an input control circuit Now, read and write operations of the ECC circuit-containing semiconductor memory device having the aforementioned structure will be described. First, in writing a data in the ECC circuit-containing semiconductor memory device, an 8-bit data, (D Next, in reading a data from the ECC circuit-containing semiconductor memory device, a 1-word data read from the memory cell array —Specific Circuit Configuration— In the ECC circuit-containing semiconductor memory device of this embodiment, as compared with the semiconductor memory devices of the first and second conventional examples shown in —Operation Method— Now, the operations for the error correcting code generation, the syndrome generation and the data correction of the ECC circuit First, the following Formulas (3) are used in the operation for generating a 4-bit error correcting code from eight data bits: Formulas (3):
It is understood from Formulas (3) that the ECC circuit-containing semiconductor memory device of this embodiment has the following two characteristics: The first characteristic is that the same number of bits are assigned for calculating the respective bits, C The second characteristic is that the error correcting code of four bits is generated in a pattern of the same type as the pattern of the data of eight bits. For example, in the case where a checker pattern is written as a data, namely, when (D In contrast, in using the conventional error correcting code represented by Formulas (1), when (D The checker pattern and the stripe pattern are effective test patterns for detecting a defect such as interference between physically adjacent memory cells (each corresponding to a bit) in a test of memory cells. In the conventional ECC circuit-containing semiconductor memory device, however, it is necessary to use a dedicated test pattern for conducting a test using the checker pattern or the stripe pattern. On the contrary, in the ECC circuit-containing semiconductor memory device of this embodiment, since the generated error correcting code pattern is of the same type as the pattern of the data, error correcting codes suitable for various tests can be generated by using data patterns without additionally preparing various types of test patterns. Accordingly, the number of test patterns necessary to be prepared can be reduced. Formulas (3) can be changed as follows:
On the other hand, Formulas (4) used for generating a syndrome corresponding to Formulas (3) for generating the error correcting code are represented as follows: Formulas (4):
Formulas (4) can be changed as follows:
Furthermore, data correction carried out in detecting an error as a result of generating a syndrome is conducted in accordance with the following Formulas (5): Formulas (5):
The following Formula (6) represents a test matrix H used in the ECC circuit-containing semiconductor memory device of this embodiment and corresponding to Formula (2) described as the conventional technique: Formula (6):
Also as described with respect to the conventional technique, the syndrome s is represented by the following formula:
—Circuit Operation— The circuit operation of the ECC circuit-containing semiconductor memory device of this embodiment will now be described. In generating an error correcting code, an 8-bit data on the data bus In generating a syndrome, an 8-bit data on the data bus In this manner, in the circuit operation of the ECC circuit-containing semiconductor memory device of this embodiment, since the same number of data bits are used in calculating each bit of the error correcting code as described above (as represented by Formulas (3)), the circuit delay caused in calculating the respective bits for generating the error correcting code can be constant, resulting in smoothly generating the error correcting code. In Formulas (3) used for calculating the respective bits of the error correcting code, arbitrary two bits of the data bits can be exchanged plural times as described above, and also in Formulas (4) used for calculating the respective bits of the syndrome, arbitrary two bits of the data bits can be exchanged plural times. Also, Formulas (3) can be changed as follows by replacing bits C When a 16-bit data (D It is assumed also in this embodiment that a 4-bit error correcting code is generated from an 8-bit data by using Formulas (3) described in Embodiment 1. In other words, this embodiment is also characterized by generating, from an 8-bit data, a 4-bit error correcting code in a pattern of the same type as that of the data. This error correcting code pattern has the following regularity: To a formula for calculating an error correcting code bit with an even subscript, an odd number of data bits with even subscripts and an even number of data bits with odd subscripts are assigned. For example, to bit C In test patterns that can be generated in accordance with the aforementioned regularity, the correspondence between specific data bits and error correcting code bits is exemplified as follows:
In writing a data “0” in all the memory cells in the memory cell array In writing the checker pattern in the entire memory cell array Moreover, in writing a stripe pattern along the row direction (lateral stripe pattern) in the memory cell array In this manner, this embodiment employs the rule for generating an error correcting code in which an odd number of data bits with even subscripts and an even number of data bits with odd subscripts are assigned to a formula for calculating an error correcting code bit with an even subscript and an odd number of data bits with odd subscripts and an even number of data bits with even subscripts are assigned to a formula for calculating an error correcting code bit with an odd subscript. Accordingly, an error correcting code in the partial checker pattern can be generated by using a data in the partial checker pattern, an error correcting code in the partial checker bar pattern can be generated by using a data in the partial checker bar pattern, an error correcting code in the partial all-0 pattern can be generated by using a data in the partial all-0 pattern, and an error correcting code in the partial all-1 pattern can be generated by using a data in the partial all-1 pattern. When the respective memory cells in the memory cell array Accordingly, in the method of generating an error correcting code of this embodiment, since a data pattern can be used for generating an error correcting code pattern of the same type, a defect such as interference between memory cells (bits) adjacent to each other in any direction can be advantageously detected in the memory test without additionally preparing test patterns dedicated to error correcting codes. Embodiment 3 As is shown in As described with respect to the conventional technique, in an ECC circuit-containing memory device capable of correcting a 1-bit error, in order to conduct a memory test without using a signal line for inputting/outputting an error correcting code between an ECC circuit memory block and an external device, it is necessary to detect defects of two or more bits included in one word through a test using data bits alone. By using conventional memory test patterns, however, defects of two or more bits cannot be detected. For example, when four test patterns, (D In this embodiment, the following nine patterns are used as test patterns for data bits generated by the test circuit -
- (D
**0**D**1**D**2**D**3**D**4**D**5**D**6**D**7**C**0**C**1**C**2**C**3**) - Pattern 1 (0 0 0 0 0 0 0 0 0 0 0 0)
- Pattern 2 (1 1 1 1 1 1 1 1 1 1 1 1)
- Pattern 3 (0 1 0 1 0 1 0 1 0 1 0 1)
- Pattern 4 (1 0 1 0 1 0 1 0 1 0 1 0)
- Pattern 5 (0 0 1 1 0 0 1 1 0 0 1 1)
- Pattern 6 (1 1 0 0 1 1 0 0 1 1 0 0)
- Pattern 7 (1 1 1 1 0 0 0 0 1 1 1 1)
- Pattern 8 (0 1 0 1 1 1 1 1 1 0 1 0)
- Pattern 9 (1 0 1 0 1 1 1 1 0 1 0 1)
As a rule for generating the nine patterns, each test pattern always includes four kinds of patterns, (0 0), (0 1), (1 0) and (1 1), as combinations of arbitrary two bits including bits not adjacent to each other in the respective bits thereof. When the test is conducted by the test circuit**22**by using the nine patterns, arbitrary two bits having a defect can be detected as a 2-bit defect in any one or more of the test patterns. Since the test circuit**22**for generating the patterns is thus provided, defects of two or more bits can be detected in both data bits and error correcting code bits in the memory cell array of the ECC circuit-containing semiconductor memory device.
- (D
The test circuit The test circuit When hardware such as a tester is additionally provided, data bits in the memory cells can be directly accessed. Embodiment 4 As is shown in Now, operations for normal write, test mode write, normal read and test mode read and the corresponding circuit operations of the ECC circuit In the normal write operation, Formulas (3) described in Embodiment 1 are used for generating a 4-bit error correcting code from an 8-bit data. Also, in the normal read operation, a syndrome is generated by using Formulas (4) described in Embodiment 1. In the test mode write operation, the following Formulas (7) are used:
As a characteristic of Formulas (7) used in the test mode write operation, one bit D Therefore, when the normal read operation is conducted after the test mode write operation, a syndrome, (S Next, the circuit operation will be described. In the test mode write operation, the data bus input control circuit In generating a syndrome, the data bus input control circuit In order to test the data correcting circuit In this manner, according to Embodiment 4, the multifunctional test can be carried out in the ECC circuit Furthermore, in order to test the error correcting code storage area -
- 1. There is no bit to be correspondingly corrected; and
- 2. When an error correcting code includes a 1-bit error, one bit of the syndrome is inverted so that the corresponding data bit can be always corrected. Accordingly, in the case where there is no bit error in the normal read operation, a data the same as a written data can be read.
When the error correcting code, (C -
- (1, 0, 1, 1) obtained in the case where bit C
**1**is an error; - (1, 1, 0, 1) obtained in the case where bit C
**2**is an error; - (1, 1, 1, 0) obtained in the case where bit C
**3**is an error; and - (0, 1, 1, 1) obtained in the case where bit C
**0**is an error. Therefore, in the normal read operation, bit D**0**, D**1**, D**2**or D**3**is inverted to be output. In this manner, a defect of one bit of the error correcting code is detected, and thus, the error correcting code storage area can be tested.
- (1, 0, 1, 1) obtained in the case where bit C
Table 1 lists all possible defective patterns of the error correcting code storage area and test patterns used for detecting the respective defective patterns in the test mode write operation. In this manner, according to Embodiment 4, the error correcting code storage area
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