|Publication number||US6941489 B2|
|Application number||US 10/084,533|
|Publication date||Sep 6, 2005|
|Filing date||Feb 27, 2002|
|Priority date||Feb 27, 2002|
|Also published as||DE10304447A1, DE10304447B4, US20030163763|
|Publication number||084533, 10084533, US 6941489 B2, US 6941489B2, US-B2-6941489, US6941489 B2, US6941489B2|
|Original Assignee||Hewlett-Packard Development Company, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (30), Classifications (7), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Modern computing systems utilize various hardware and software techniques to detect internal data errors. One such technique used within RAID I/O devices includes multiple redundant central processing units (CPUs) to duplicate processing. The results are compared and, if identical, a decision is made as to whether the data is error-free. If errors are detected, a decision is made as to which of the redundant devices is correct.
In RISC processors, redundant processing cores are sometimes implemented on a common die to similarly provide redundant error checking techniques. Redundancy may also be duplicated at lower level devices (e.g., an ALU) to provide like error-detect capabilities for parity level decisions. RISC processors also sometimes implement error correction code such as in connection with cache entries. However, data errors within the random and speculative logic of RISC processors are particularly difficult to detect; and there are no practical error correction techniques suitable for operations such as prefetch, branch prediction and bypassing.
There may be many causes of data errors within RISC processors. By way of example, cosmic ray particles may flip a bit within a logical latch of the processor. Dynamic logic and storage nodes are particularly susceptible to cosmic and alpha particles that perturb internal storage cells. Even static logic devices (e.g., NOR gates) may exhibit error or noise due to cosmic particles.
Accordingly, prior art techniques exist that may “detect” logical errors and the like within RISC processors. Nevertheless, redundant detection techniques often complicate timing and bypass logic; it may for example take up to three extra cycles to perform a compare between redundant devices, which greatly complicates the write-back logic of parallel pipelines.
Moreover, within the prior art, the “recovery” associated with data errors is quite difficult and cumbersome. Often, for example, this recovery involves analyzing and electing which of two redundant devices to use as the appropriate data. The prior art has even implemented three redundant devices to help this analysis and election. Improvements are thus needed to facilitate data recovery in the event of logical errors in modem processors. One feature of the invention is to provide recovery logic within the RISC processor to recapture lost or corrupted data written to register files. Other features of the invention are apparent within the description that follows.
The invention in one aspect includes methodology to perform an extra read from a register file prior to writing to that register file. The data from the extra read is stored in a buffer (e.g., another register file). After a time period—defined herein as a “checkpoint”—a check is made as to whether any data errors have occurred; if there are no errors, the buffer is flushed and processing continues per normal; if there are errors, the register file is rewritten with contents from the buffer and the program counter is reset to the prior checkpoint, wherein after processing re-executes program instructions from the last checkpoint. Checkpointing of the register file may occur at predetermined time periods, e.g., every 100 cycles. The checkpointing period may be defined by the memory size of the buffer; typically that buffer has a fraction of the memory capacity of the register file, since a flush occurs at every checkpoint. By way of example, the buffer may include twenty registers as compared to one hundred twenty eight registers in the register file. The register file of the invention may utilize an extra read port with the register file to perform the extra read. In accord with certain aspects, the invention may perform the extra read for every write to the register file; alternatively, the invention may perform the extra read for a subset of the writes to the register file.
The invention thus protects the processor from inadvertent data errors, such as a corrupted speculative write to the register file. At the end of each pipeline, often identified by those skilled in the art as the “write-back” stage, the register file is architected; any delay in the write-back stage increases the b ass logic. Accordingly, the invention preferably architects the register file in norm write-back operations; but a backup copy of the affected register is made within the buffer in case of data errors. In one aspect, checkpointing occurs after each fixed number of cycles; a larger buffer increases the time slice available for recovery d between checkpoints. Prior to each register write, the prior value is read and stored within the buffer. At each checkpoint, therefore, the older data may be rewritten t the register file so that the program may return to a prior checkpoint location e.g., via the program counter) to re-execute the instructions. The invention thus circumvents errors caused by random cosmic rays or alpha particles within processor logic.
In yet another aspect, the invention circumvents additional bypass logic which might otherwise be required, due to the extra read, by reading the register file at the same time instruction operands are read during pipeline execution of instructions; bypass logic already exists within certain RISC processors to accomplish this. Accordingly, the extra read of the invention may be accomplished just prior to the execution stage of the pipeline since the register implicated by the instruction has just been identified.
In still another aspect, the invention utilizes its existing write port to recover data from the buffer to the register file; in another aspect, an additional register file write port is utilized. Preferably, the register file has an additional read port to perform the extra read.
Preferably, error correction code is used in connection with the buffer.
The invention is next described further in connection with preferred embodiments, and it will become apparent that various additions, subtractions, and modifications can be made by those skilled in the art without departing from the scope of the invention.
A more complete understanding of the invention may be obtained by reference to the drawings, in which:
In operation, an instruction unit 22 provides instructions to an execution unit 24 with an array of pipeline execution units 26 through a mux 28. A program counter 29 serves to sequentially step through the program threads of the program initiating those instructions. Pipeline execution units 26 have execution stages 30 a-30 n so as to perform, for example, fetch (F), decode (D), execute (E) and write-back (W) operations known to those skilled in the art. Pipeline stage 30n may for example architect any of the registers within register file 12 as a write-back stage W, through data bus 32 and write mux 14 (supporting the multiple write ports). Individual stages 30 of pipelines 26 may transfer speculative data to other execution units, and/or to register file 12, through bypass logic 40; this speculative data may reduce hazards within other individual stages 30 in providing the data forwarding capability for architecture 10; this speculative data also serves to enhance processor performance by writing speculative data to register file 12 as predictive of final architected loads to registers therein. Data may be read from register file 12 through read mux 16 (supporting the multiple read ports) and data bus 42.
Prior to architecting data to a register within register file 12, the prior data of that register is written to buffer 20. Preferably, this read is performed at the same time instruction operands are read for an instruction in a pipeline 26, which is just prior to the execute E stage of that pipeline 26. For example, if stage 30 c represents the execute stage, and stage 30 b represents the decode D stage, then speculative data representing a future architected store may be transferred from stage 30 b—and through bus 50, logic 40, and bus 56—to a register of register file 12. The prior data of that register is read prior to the storing of that speculative load, so it is saved in backup. Generally, data is read from read port 18 of register file 12 and stored in buffer 20 through bus 60. However, other data paths between register file 12 and buffer 20 may be used as a matter of design choice, such as through bus 42, mux 28, bypass logic 40 and bus 52, as shown.
In summary, prior data of a particular register is stored within buffer 20 prior to a register load of that register within register file 12. The prior data within that register is read and stored in buffer 20, via read port 18 and bus 60, just prior to architecting the new data within the register of register file 12, e.g., at a write-back stage through bus 32.
At every checkpoint, defined in more detail below, architecture 10 is evaluated for data errors. The architecting of data after a speculative load may be preferentially delayed during the check for data errors. If no data errors are detected since the last checkpoint, buffer 20 is flushed and processing of instructions from unit 22 continue; a delayed speculative load may also be architected. If data errors are detected, then register file 12 is reloaded with data from buffer 20, through buffer write bus 70 and write port 19 (or another write port of processed through write mux 14), and counter 29 is reset to re-execute instructions corresponding to the last checkpoint; processing thereafter continues to the next checkpoint.
Checkpointing of register file 12 occurs in the following way, as illustrated by the flowchart 100 of FIG. 2. At step 102, an instruction is decoded for a register write (i.e., a “load”) of data to a register (illustratively identified as register “M”) within the register file. Prior to writing that data, pre-existing data within register “M” is read from the register file, at step 104, and then stored in the buffer, at step 106. Register “M” may be loaded, as directed from the decoded instruction, at step 107 (step 107 may occur at other locations within flowchart 100).
If the current cycle does not correspond to a checkpoint, as defined at step 108, then processing of subsequent instruction decodes again proceeds at step 102. As illustrated in
Those skilled in the art should appreciate that buffer logic 20 may take the form of a register file. Typically, that register file has many fewer registers than register file 12, since buffering only occurs between checkpoints.
The invention thus attains the features set forth above, among those apparent from the preceding description. Since certain changes may be made in the above methods and systems without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawing be interpreted as illustrative and not in a limiting sense. It is also to be understood that the following claims are to cover all generic and specific features of the invention described herein, and all statements of the scope of the invention which, as a matter of language, might be said to fall there between.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3736566 *||Aug 18, 1971||May 29, 1973||Ibm||Central processing unit with hardware controlled checkpoint and retry facilities|
|US5119483 *||Jul 20, 1988||Jun 2, 1992||Digital Equipment Corporation||Application of state silos for recovery from memory management exceptions|
|US5269017 *||Aug 29, 1991||Dec 7, 1993||International Business Machines Corporation||Type 1, 2 and 3 retry and checkpointing|
|US5568380 *||Aug 30, 1993||Oct 22, 1996||International Business Machines Corporation||Shadow register file for instruction rollback|
|US5692121 *||Apr 30, 1996||Nov 25, 1997||International Business Machines Corporation||Recovery unit for mirrored processors|
|US6629271 *||Dec 28, 1999||Sep 30, 2003||Intel Corporation||Technique for synchronizing faults in a processor having a replay system|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7159154 *||Jul 8, 2003||Jan 2, 2007||Intel Corporation||Technique for synchronizing faults in a processor having a replay system|
|US7389455 *||May 14, 2006||Jun 17, 2008||Texas Instruments Incorporated||Register file initialization to prevent unknown outputs during test|
|US7409589 *||May 27, 2005||Aug 5, 2008||International Business Machines Corporation||Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor|
|US7437593 *||Jul 14, 2003||Oct 14, 2008||International Business Machines Corporation||Apparatus, system, and method for managing errors in prefetched data|
|US7487334 *||Feb 3, 2005||Feb 3, 2009||International Business Machines Corporation||Branch encoding before instruction cache write|
|US7516361 *||Jan 13, 2006||Apr 7, 2009||Sun Microsystems, Inc.||Method for automatic checkpoint of system and application software|
|US7739547||Jun 7, 2007||Jun 15, 2010||International Business Machines Corporation||Failure recovery and error correction techniques for data loading in information warehouses|
|US8020072||Sep 13, 2011||International Business Machines Corporation||Method and apparatus for correcting data errors|
|US8301992||Aug 7, 2009||Oct 30, 2012||International Business Machines Corporation||System and apparatus for error-correcting register files|
|US8732550 *||Dec 8, 2009||May 20, 2014||Fujitsu Limited||Processor and error correcting method|
|US8924692||Dec 26, 2009||Dec 30, 2014||Intel Corporation||Event counter checkpointing and restoring|
|US9063747 *||Apr 28, 2011||Jun 23, 2015||Freescale Semiconductor, Inc.||Microprocessor systems and methods for a combined register file and checkpoint repair register|
|US9218377||Jun 5, 2008||Dec 22, 2015||International Business Machines Corporation||Failure recovery and error correction techniques for data loading in information warehouses|
|US9256497 *||Mar 25, 2014||Feb 9, 2016||Intel Corporation||Checkpoints associated with an out of order architecture|
|US9372764||Nov 26, 2014||Jun 21, 2016||Intel Corporation||Event counter checkpointing and restoring|
|US20040153769 *||Jul 8, 2003||Aug 5, 2004||Yung-Hsiang Lee||Technique for synchronizing faults in a processor having a replay system|
|US20050015664 *||Jul 14, 2003||Jan 20, 2005||International Business Machines Corporation||Apparatus, system, and method for managing errors in prefetched data|
|US20060174095 *||Feb 3, 2005||Aug 3, 2006||International Business Machines Corporation||Branch encoding before instruction cache write|
|US20060271820 *||May 27, 2005||Nov 30, 2006||Mack Michael J||Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor|
|US20060294435 *||Jan 13, 2006||Dec 28, 2006||Sun Microsystems, Inc.||Method for automatic checkpoint of system and application software|
|US20070061645 *||May 14, 2006||Mar 15, 2007||Texas Instruments Incorporated||Register file initialization to prevent unknown outputs during test|
|US20080109687 *||Oct 25, 2006||May 8, 2008||Christopher Michael Abernathy||Method and apparatus for correcting data errors|
|US20080307011 *||Jun 5, 2008||Dec 11, 2008||International Business Machines Corporation||Failure recovery and error correction techniques for data loading in information warehouses|
|US20080307255 *||Jun 7, 2007||Dec 11, 2008||Ying Chen||Failure recovery and error correction techniques for data loading in information warehouses|
|US20090150649 *||Dec 10, 2007||Jun 11, 2009||Jaume Abella||Capacity register file|
|US20100088572 *||Apr 8, 2010||Fujitsu Limited||Processor and error correcting method|
|US20110035643 *||Aug 7, 2009||Feb 10, 2011||International Business Machines Corporation||System and Apparatus for Error-Correcting Register Files|
|US20110161639 *||Jun 30, 2011||Knauth Laura A||Event counter checkpointing and restoring|
|US20120278592 *||Apr 28, 2011||Nov 1, 2012||Tran Thang M||Microprocessor systems and methods for register file checkpointing|
|US20150278025 *||Mar 25, 2014||Oct 1, 2015||Dennis M. Khartikov||Checkpoints associated with an out of order architecture|
|U.S. Classification||714/10, 714/E11.114, 714/15|
|International Classification||G06F11/00, G06F11/07|
|Jul 2, 2002||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
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Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., COLORAD
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|Aug 11, 2009||CC||Certificate of correction|
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|Nov 9, 2015||AS||Assignment|
Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, TEXAS
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