|Publication number||US6941537 B2|
|Application number||US 10/067,244|
|Publication date||Sep 6, 2005|
|Filing date||Feb 7, 2002|
|Priority date||Feb 7, 2002|
|Also published as||US20030145460|
|Publication number||067244, 10067244, US 6941537 B2, US 6941537B2, US-B2-6941537, US6941537 B2, US6941537B2|
|Inventors||Rebecca A. Jessep, David W. Boggs, Carolyn McCormick, John H. Dungan, Daryl A. Sato|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (29), Classifications (67), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is directed to standoff arrangements to control distance and provide electrical function.
The performance requirements for semiconductor devices continue to increase. Performance may be improved, for example, with the addition of further input and output signal connections. To accommodate these additional connections in small surface mount packages, soldered grid array technology has been used and continues to develop. As one example, Bump/Ball Grid Arrays (BGAs) have conductive bumps/balls (e.g., solder and/or conductive-filled polymer) arranged in a conductive grid array pattern and serving as the connectors. This density is further increased in MicroBGAs (μBGA) and Chip Scale Packages (CSPs). As advantages, the higher density BGA reduces package size, and also helps lead to decreased printed circuit board (PCB) size, shorter leads/interconnections, reduced weight, improved electrical performance, and/or decreased cost.
With regard to gaining widespread use, both reliability of semiconductor packages and low cost of manufacture may help promote maximized package adoption/use. The BGA package conductive bumps/balls are the package's interface with the receiving substrate printed circuit board (e.g., PCB) upon which the BGA package is mounted. It has been found within research directed toward the present invention that the reliability of this interface can sometimes be affected by package standoff distance. If used between a PCB and a package, standoff distance may be, for example, the distance from the top plane of the PCB to the bottom edge of the BGA package after mounting. It has been found in the present research that the inability to control Surface Mount Technology (SMT) assembly deviations in standoff distance can lead to solder collapse and low cyclic fatigue life.
In addition to physical integrity, electrical performance is another consideration of conductive grid array (as well as any) mounting technology. More particularly, as system functions increase, package power demand (e.g., electrical current conduction) likewise may increase. Such current may be delivered through the PCB layers to the die through some of the conductive bumps/balls, but as they become smaller, the conductive bumps/balls may not be able to handle a required electrical current conduction capacity, or an excessive number of conductive bumps/balls may be required to do so. Further, other electrical components/functions (e.g., resistors, capacitors, inductors) may be required in the area proximate to the conductive grid array, which may place limits on the conductive grid array design.
Needed are arrangements to control semiconductor package standoff distance, and to provide convenient electrical functions.
The foregoing, and a better understanding of the present invention, will become apparent from the following detailed description of example embodiments, and the claims, when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing, and following, written and illustrated disclosure focuses on disclosing example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only, and that the invention is not limited thereto. The spirit and scope of the present invention are limited only by the terms of the appended claims.
The following represents brief descriptions of the drawings, wherein:
Before beginning a detailed description of the subject invention, mention of the following is in order. When appropriate, like reference numerals and characters may be used to designate identical, corresponding or similar components in differing figure drawings. Further, in the detailed description to follow, example sizes/models/values/ranges may be given, although the present invention is not limited to the same. Well-known power/ground connections to substrates, ICs and other components may not be shown in great detail within the FIGs. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in simplistic diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., specifics should be well within the purview of one skilled in the art. Where specific details are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with, variation of these specific details.
While the following detailed description will describe example embodiments of arrangements in the context of an example BGA arrangement having conductive bumps/balls as a conductive grid array, practice of the present invention is not limited to such context, i.e., practice of the present invention may have uses with other types of chips and with other types of mounting and packaging techniques. For example, practice of the present invention may be able to be made in the context of the aforementioned μBGA and/or CSP arrangements.
Turning now to the detailed description,
The BGA package 100 may have an example package height A of 2.0 mm (see FIG. 1). The conductive bumps/balls 160 may be utilized in whole or in part as electrical interconnections for signal, power and/or ground inputs/outputs to the die. The conductive bump/ball 160 height A1 may be an example 0.635 mm. There may be, for example, multiple (e.g., two) dies 120 within a single BGA package 100, and each may be separately connected with conductive (e.g., gold) wires 140 (e.g., in a stacked CSP). Such BGA package 100 is subsequently mounted to a PCB (shown hereafter in FIG. 4).
Turning next to
Turning next to
More particularly, the example
Turning next to the inter-layers 420, inter-layers La, Lc, and Le may be of, for example, prepreg material, alternating with inter-layers Lb and Ld made of, for example, a copper-clad resin core. The prepreg material may be, for example, “pre-impregnated” fiberglass fabric saturated with a polymide, epoxy or other resin partially cured during a coating operation and deposited on the fabric. The core material may be copper clad resin. Vias 320 may extend in a variety of lengths/arrangements, for example, may extend totally through the PCB (see FIG. 4), extend totally within the PCB, or connect to one side of the PCB from one of the inner layers.
During mounting, alignment is important in that, if the conductive bumps/balls 160 are not aligned with lands 340, the bump-/ball-to-land connections are not reliable (e.g., they can disadvantageously short-circuit with neighboring lands and/or pads). Further, lack of co-planarity of conductive bumps/balls and lands may also inhibit reliable connections (i.e., some of the opposing conductive bumps/balls and lands may be unable to touch due to non-planarity, thereby never completing the electrical conduction path).
In the uncontrolled standoff arrangement of
As further disadvantages within the
As further related alignment discussions, while the above-discussed conductive (e.g., gold) wires 140 may serve to improve electrical performance, the conductive (e.g., gold) wires 140 do nothing to help with alignment, and in fact, are often applied at an assembly stage subsequent to the alignment/solder-jointing stage.
Turning next to standoff variation discussions, variation in S (see
As to additional assembly requirements, example suitable methods/times of adding the standoff arrangements (standoff/power pins) may include installation during a SMT assembly operation, as any standoff arrangements may be held on through any solder paste. An alternative installation time might be at a pick-and-place operation. In either method, the standoff arrangement may be able to be held in place by solder or other conductive material applied at a wave operation.
In addition to standoff, the example embodiment in
Since a weight/assembly pressure of the BGA package may now be borne by the standoff/power pins rather than the conductive bumps/balls, smaller conductive bumps/balls may be able to be used so as to achieve a grid array of increased density within a same-size grid array. Alternatively, an existing grid array could be made smaller to enable a smaller package size, allowing for construction of smaller electrical devices. The
The illustrated standoff/power pin structure has example platforms (shelves) 610 which, when the standoff/power pins are positioned in countersinks 620 in the BGA package 100 and in the receiving substrate 310, buttress against such components so as to control the standoff distance of the BGA package in relation to the receiving substrate. When the package is assembled, the mounted rigid standoff/power pin will enable a standoff distance S′ between the BGA package and the receiving substrate to be controlled dependent on the distance between the platforms (shelves) 610, and the depth of the countersinks 620. Alternatively, the countersinks may be absent and the platforms (shelves) could rest on, and be attached to, a package surface. In another embodiment, one or more platforms (shelves) may be absent, with the standoff distance determined by the length of the standoff/power pin structure relative to the standoff/power pin mounting depth.
As mentioned previously, the standoff/power pin may be constructed of a material that will allow the standoff/power pin to also perform electrical functions, e.g., serve as an electrical conduction path from the receiving substrate layers to the BGA package. The standoff/power pin may be of a solid material in monolithic construction, or alternatively, may be of a more complex multi-layered construction such as having differing conductive surfaces 630 and insulated surfaces 640. Power delivery from the receiving substrate 310 to the BGA package 100 may be improved as the conductive surface 630 of each standoff/power pin may be designed to directly contact an example PCB power layer 410′ and an example power plane 150 when the standoff/power pin is installed upon mounting. Alternatively, the standoff/power pin may be designed to contact a receiving substrate's ground layer and receiving substrate's ground plane.
As a further embodiment, rather than providing simple electrical conduction path functions, the standoff/power pins may be able to be designed to provide other types of electrical functions to one or both of the electrical components being mounted together. In a simplistic example, the standoff/power pin may be constructed of a rigid but electrically resistive material, to result in a tubular resistor. Continuing with another example, the standoff/power pin could be of a more complex, multi-layered construction having conductive material inner and outer layers separated by an intermediate dielectric material layer, to result in a tubular capacitor. More particularly, an outer conductive layer of the standoff/power pin may serve as a first plate of the capacitor, while an inner conductive layer may serve as a second plate of the capacitor, with an insulating or dielectric layer being disposed therebetween. In this example embodiment, the standoff/power pin could serve a double function, both in control of standoff distance and as a capacitance device. Such dual standoff/capacitance arrangement may be particularly useful with dies, packages, etc. requiring decoupling capacitors.
It should be noted that, in such a situation, the capacitive-type standoff/power pin may be providing an electrical function solely to a single substrate rather than electrically interfacing the two substrates. As one example, the capacitive device could serve as an electrical path/device for one of the substrates in that the inner conductive layer and the outer conductive layer could be electrically connected to the same substrate, while the capacitive device is electrically insulated from the other substrate. However, the standoff/power pin would still provide physical interfacing by contacting both substrates to control the standoff distance. As yet another example, the standoff/power pin may be formed into a tubular inductor, or may be of an even more complex construction containing ones of resistors, capacitors and inductors, to result in, for example, a complex impedance arrangement, an electronic filter arrangement, and so forth.
In conclusion, reference in the specification to “one embodiment”, “an embodiment”, “example embodiment”, etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments. Furthermore, for ease of understanding, certain method procedures may have been delineated as separate procedures; however, these separately delineated procedures should not be construed as necessarily order dependent in their performance, i.e., some procedures may be able to be performed in an alternative ordering, simultaneously, and so forth.
This concludes the description of the example embodiments. Although the present invention has been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
While the foregoing example embodiments illustrate using the standoff arrangements of the present invention to provide dual standoff control and electrical function between a package and another substrate, practice of alternative embodiments of the present invention may also have uses providing dual standoff control and electrical function between other types of items. This includes, for example, providing standoff/electrical-functions between stacked dies, between a die and a substrate, and so forth. Further, the standoff arrangements are not limited to standoff/power pins, or to arrangements that penetrate the components (e.g., substrates) to which it provides the standoff or electrical function. Finally, practice of the various embodiments of the present invention is not limited to arrangements providing the standoff and electrical functions equal to one another. For example, an embodiment may have standoff/electrical-function arrangements in which standoff/power pins have a primary purpose of power delivery, and a lesser function of standoff distance control, or vice versa.
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|U.S. Classification||716/137, 257/E23.068, 257/E23.067, 257/E21.511|
|International Classification||H05K1/14, H01L23/498, H01L21/60, H05K3/30, H05K1/02|
|Cooperative Classification||H01L2924/181, Y02P70/613, H01L24/45, H01L2924/00014, H01L2924/351, Y10T29/49147, Y10T29/4913, Y10T29/49155, Y10T29/49144, H01L24/48, H01L2924/19042, H01L2924/19041, H05K3/308, H05K3/303, H05K1/0231, H01L2924/01079, H01L2924/01082, H05K2203/167, H01L2224/81801, H01L2924/3011, H05K2201/10734, H01L2224/1319, H05K1/023, H05K2201/2036, H05K2201/10022, H01L2224/48465, H01L2924/01322, H05K2201/09809, H01L2924/01057, H01L2924/01033, H05K1/145, H05K2201/1053, H05K1/0233, H01L23/49811, H01L2224/32225, H05K2201/10871, H01L24/81, H01L2924/014, H05K2201/10659, H01L2224/73265, H01L2224/48227, H05K2201/10303, H01L2924/15311, H01L2924/01029, H01L2924/19043, H01L2924/30105, H01L2924/01005, H01L2924/0105, H05K2201/10568, H01L23/49827, H01L2224/48091, H01L2224/45144, H01L2224/81136|
|European Classification||H01L24/81, H01L23/498E, H05K1/02C2E, H01L23/498C, H05K3/30C|
|May 2, 2002||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JESSEP, REBECCA A.;BOGGS, DAVID W.;MCCORMICK, CAROLUN;AND OTHERS;REEL/FRAME:012856/0663
Effective date: 20020422
|Feb 25, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Feb 20, 2013||FPAY||Fee payment|
Year of fee payment: 8