|Publication number||US6955947 B2|
|Application number||US 10/941,185|
|Publication date||Oct 18, 2005|
|Filing date||Sep 14, 2004|
|Priority date||Nov 30, 2001|
|Also published as||US6790709, US20030104679, US20050040498|
|Publication number||10941185, 941185, US 6955947 B2, US 6955947B2, US-B2-6955947, US6955947 B2, US6955947B2|
|Inventors||Rajen Dias, Biju Chandran|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (10), Classifications (35), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This U.S. patent application is a divisional of U.S. patent application Ser. No. 10/000,252, filed Nov. 30, 2001 now U.S. Pat. No. 6,790,709.
1. Field of the Invention
The present invention relates to the backside metallization and dicing of microelectronic device wafers. In particular, the present invention relates to forming a substantially V-shaped notch extending into the microelectronic device wafer from a back surface thereof prior to metallization and dicing.
2. State of the Art
In the production of microelectronic devices, integrated circuitry is formed in and on semiconductor wafers, which is usually comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide may be used. As shown in
After the integrated circuit areas 202 have been subjected to preliminary testing for functionality (wafer sort), the microelectronic device wafer 200 is diced (cut apart), so that each area of functioning integrated circuitry 202 becomes a microelectronic die that can be used to form a packaged microelectronic device. One exemplary microelectronic wafer dicing process uses a circular diamond-impregnated dicing saw, which travels down the scribe streets 204 lying between each of the rows and columns. Of course, the scribe streets 204 are sized to allow passage of a wafer saw blade between adjacent integrated circuit areas 202 without causing damage to the circuitry therein.
As shown in
Prior to dicing, the microelectronic device wafer 200 is mounted onto a sticky, flexible tape 222 (shown in
As shown in
However, in the dicing of microelectronic device wafers 200, dicing saws (metal impregnated with diamond) may cause chipping of the backside metallization layer 216 to expose a portion of the semiconductor wafer back surface 218. Since the thermal interface material 234 does not wet the semiconductor wafer back surface 218, microgaps 236 form between the thermal interface material 234 and the semiconductor wafer back surface 218, and a poor (sagging) thermal interface material fillet 238 results between the heat dissipation device 232 and the backside metallization layer 216, as shown in FIG. 14.
During the operation of the microelectronic die 224 stresses occur at the interface between the backside metallization layer 216 and the thermal interface material 234, particularly at corners/edges 244 of the microelectronic die 224. These stresses can result in delamination, generally starting at the microelectronic die corners/edges 242. This delamination results in a decrease in thermal conductivity and moisture encroachment. With a decrease in thermal conductivity comes the risk of overheating in the microelectronic die 224, which can result in the damage or destruction thereof. The microgaps 236 and the poor thermal interface material fillet 238 exacerbate the delamination.
Therefore, it would be advantageous to develop techniques to effectively dice microelectronic device wafers while reducing or substantially eliminating the possibility of delamination propagation.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
The present invention includes forming a substantially V-shaped notch in the back surface of a microelectronic device wafer, opposite scribe streets thereof, prior to backside metallization. When the microelectronic wafer is diced into separate microelectronic dice, the dice channel meets the substantially V-shaped notch. This results in a microelectronic die structure that greatly reduces or prevents delamination between the backside metallization and a thermal interface material subsequently applied to form a thermal contact between the microelectronic die and a heat dissipation device.
The interconnection layer 108 are generally alternating layers 112 of dielectric material, including but not limited to silicon dioxide, silicon carbide, silicon oxy fluoride, carbon doped silicon oxides, silicon nitride, epoxy resin, polyimide, bisbenzocyclobutene, and the like, and layers of patterned electrically conductive material, including copper, aluminum, alloys thereof, and the like. The methods and processes for fabricating the interconnection layer 108 will be evident to those skilled in the art.
As previously discussed, a plurality of scribe streets 116 separates the individual integrated circuitry areas 114. Generally the scribe streets 116 run perpendicularly to separate the integrated circuitry areas 114 into rows and columns. Preferably, at least one guard ring 118 isolates integrated circuitry areas 114 from the scribe streets 116, as discussed previously in relation to
As shown in
The substantially V-shaped notch 122 includes two sidewalls 124 and 124′ that terminate at an intersection location 126 within the semiconductor wafer 102. The substantially V-shaped notch 122 is preferably formed by bevel cuts are made in two orthogonal directions and each cut is centered between scribe lines (i.e., edges of the scribe streets 116 (not shown)) visible from the microelectronic wafer device active side 104.
As shown in
The microelectronic device wafer 100 is then diced from the semiconductor wafer active surface 104, as shown in
The substantially V-shaped notch 122, as shown in
The attachment of heat dissipation device 152 to the backside metallization layer 128 can be achieved by a number of methods, including, but not limited to the following three methods. First and preferred, the thermal interface material 154, in a thin preformed structure, is sandwiched between the heat dissipation device 152 and the backside metallization layer 128 and held together with a clamp. The clamped assembly is sent through a solder reflow oven where the thermal interface material 154 melts and forms a solid-state bond with the heat dissipating device 152 and the backside metallization layer 128 including the portion of the backside metallization layer 128 along the bevel sidewall 138. In a second method, the thermal interface material 154 is pre-applied to the heat dissipation device 152 by solder reflow. The heat dissipating device 152 is then placed on the backside metallization layer 128 and held together with a clamp. The clamped assembly is sent through a solder reflow oven where the thermal interface material 154 melts and forms a solid-state bond with the backside metallization layer 128 including the portion of metallization layer 128 along the bevel sidewall 138. In a third method, the thermal interface material 154 is pre-applied to the backside metallization layer 128 by solder reflow. The heat dissipation device 152 is then placed on the thermal interface material 154 and held together with a clamp. The clamped assembly is sent through a solder reflow oven where the thermal interface material 154 melts and forms a solid-state bond with the backside metallization layer 128 including the portion of metallization layer 128 along the bevel sidewall 138.
During the attachment of the heat dissipation device 152 with the thermal interface material 154, the thermal interface material 154 wets and wicks/extends between the backside metallization layer 128 on the beveled sidewall 138 and the heat dissipation device 152 to from a fillet 156, as shown in FIG. 7. The backside metallization layer 128 on the beveled sidewall 138 will result in a predictable fillet 156. The fillet 156 can be affected by varying a depth 158 of the substantially V-shaped notch 122, varying the angle α (see FIG. 3), and the selection of the thermal interface material 154, as will be understood by those skilled in the art. Thus, the position of the fillet 156 on the beveled sidewalls 138 can be controlled. Therefore, the thermal interface material 154 can avoid any chipping that may result from the dicing of the microelectronic device wafer.
Furthermore, the beveled sidewall 138 eliminates the microelectronic die corners/edges 242, which are shown in FIG. 14. This, in turn, greatly reduces or eliminates stresses that occur at the interface between the backside metallization layer 128 and the thermal interface material 154 during the operation of the microelectronic die 144, thereby greatly reducing the chances of delamination.
Moreover, thermal interface materials 154 are generally more compliant than the backside metallization layer 128 and the semiconductor wafer 102. Thus, the thicker thermal interface material 154 over the beveled sidewalls 138 will allow the thermal interface material 154 to deform to accommodate and relieve stress, thereby also greatly reducing the chances of delamination.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
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|U.S. Classification||438/121, 257/E23.087, 257/E29.022, 257/E23.194, 438/122, 257/E21.599|
|International Classification||H01L21/50, H01L21/44, H01L23/544, H01L23/42, H01L21/48, H01L29/06, H01L21/68, H01L21/78, H01L23/00, H01L21/46, H01L21/301|
|Cooperative Classification||H01L2924/10155, H01L29/0657, H01L2221/68327, H01L2224/73253, H01L2924/01078, H01L2924/10158, H01L23/42, H01L21/6836, H01L21/78, H01L2224/16, H01L23/562, H01L2224/04026, H01L2924/01079, H01L2224/0401|
|European Classification||H01L21/683T2, H01L23/562, H01L23/42, H01L21/78|
|Sep 14, 2004||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DIAS, RAJEN;CHANDRAN, BIJU;REEL/FRAME:015807/0384
Effective date: 20011130
|Apr 15, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Mar 6, 2013||FPAY||Fee payment|
Year of fee payment: 8