|Publication number||US6968424 B1|
|Application number||US 10/215,139|
|Publication date||Nov 22, 2005|
|Filing date||Aug 7, 2002|
|Priority date||Aug 7, 2002|
|Publication number||10215139, 215139, US 6968424 B1, US 6968424B1, US-B1-6968424, US6968424 B1, US6968424B1|
|Original Assignee||Nvidia Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (50), Classifications (18), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
Embodiments of the present invention relate to the field of data compression and data management. More specifically, embodiments of the present invention relate to the field of using data compression to increase available memory to a computer system, e.g., for use by an operating system, application program, driver, etc.
2. Related Art
Prior art computer systems extend available memory resources by data compression. Well known compression techniques exist for reducing the size of digital data while retaining the information stored in the data. Data compression has many advantages, including extending the available amount of memory resources available to a computer system as well as increasing system performance by reducing the amount of required read and write accesses to a disk storage unit. The amount of compression that is achievable for any piece of data depends largely on the nature of the data being compressed.
In the system 10 shown in
Although the hardware compression/decompression engine performs better than the software compression/decompression processes employed by the prior art system of
Therefore, the above described memory page compression techniques of the prior art are incompatible with most commercially available operating systems.
Accordingly, an embodiment of the present invention provides a system and method for performing memory page compression that is compatible with commercially available operating systems. In yet another embodiment, the present invention is directed to a memory page compression system that utilizes a hardware compression/decompression engine. In yet another embodiment, the present invention is directed to a memory page compression system that performs compression and decompression of memory pages in a way that is transparent to the operating system.
A method and system are described for implementing transparent compressed memory paging within a computer system. Memory page compression is performed in volatile memory to increase resources available to the computer system and to reduce disk accesses to thereby increase system performance and reduce power consumption. In the various embodiments described herein, the compression is performed transparently to the operating system which requires no special software interfaces to make use of the reclaimed memory. In addition, the operating system is presented with a fixed sized physical memory map that does not dynamically change size depending on the nature of the data stored in the memory pages. Furthermore, the memory pages stored on the disk storage unit are uncompressed.
In a first embodiment, memory page compression is performed in hardware to provide an extended amount of volatile memory, e.g., “reclaimed volatile memory.” The physical memory map presented to the operating system is of a fixed size because this reclaimed volatile memory is not made available to the operating system but is rather used as a hardware controlled disk cache to increase system performance. In this embodiment, the size of the disk cache may vary due to the achievable compression ratio of the memory pages. Moreover, in this embodiment, a novel method is employed to reduce duplicate memory pages between the physical memory map and the disk cache. According to this embodiment, disk reads place pages into the uncompressed memory cache and a pointer is placed into the disk cache. If the memory page is not used for a while, it is bumped from the uncompressed cache, compressed and stored in the non-cache memory available to the operating system. If the memory is written by the processor, then the unmodified page is removed from the disk cache list, compressed, and stored in the disk cache. The modified version is placed in the uncompressed memory cache. Subsequently, the processor may obtain the original page from the disk cache and page duplicates are avoided.
In another embodiment, the reclaimed volatile memory is made available in a transparent way to the operating system while maintaining the appearance of a fixed-sized physical memory space presented to the operating system. This appearance is maintained by providing a fixed-sized physical memory space to the operating system (e.g., the “operating system physical memory space”) that is larger than the physical memory space available in the volatile memory space (e.g., the “actual physical memory space”). However, variable compression ratios of the actual physical memory space lead to a varying sized operating system physical memory space. Therefore, to maintain the appearance of a fixed sized operating system physical memory space, this embodiment performs the following actions. If the actual physical memory space becomes near exhausted (e.g., due to a poor compression ratio), a special process is automatically triggered that exclusively allocates blocks of operating system physical memory space to a driver thereby removing them from operating system usage. It is appreciated that the driver does not use this memory space, it merely deallocates it from the operating system to prevent memory over-run. When the compression ratio improves such that more free space becomes available in the actual physical memory space, the driver will allocate the memory block thereby returning it back to the operating system for use.
In the second embodiment, the actual physical memory stores a majority of compressed memory pages and a minority of uncompressed memory pages that are frequently used. A special cache table used for quickly identifying the uncompressed pages for rapid retrieval thereof for supply to the operating system. Compressed memory pages may be linked via pointers in each compressed page. The identification of empty memory pages is made more efficient by a special “empty memory page” which contains a listing of empty memory pages in the actual physical memory space. Multiple empty memory pages may be linked via pointers in each. In one implementation, the size of the uncompressed memory pages can be from 0.5 kilobytes to 4 kilobytes while the compressed memory pages can be from 64 bytes to 256 bytes. In one embodiment, the compressed memory page is set to a size, e.g., 128 bytes, to hide the DRAM precharge period to increase performance.
Reference will now be made in detail to the preferred embodiments of the present invention, a method and system are described for implementing transparent compressed memory paging within a computer system, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
A volatile memory 230 is provided which may be implemented using dynamic random access memory (DRAM), in one implementation, but could be of any type of well known volatile memory, e.g., SRAM, RAM, etc. The volatile memory 230 interfaces with a hardware chipset 140 for controlling access to the DRAM 230. The volatile memory 230 is accessed using a second physical memory map (presented over bus 150) and stores a majority of compressed memory pages in one embodiment. The volatile memory 230 may also contain a minority of uncompressed memory pages in this embodiment. Importantly, the chipset 140 contains a hardware implemented compression/decompression engine 142 and a translation table to translate between the first physical memory space (made available to the operating system 124) and the second physical memory space (used by the volatile memory 230). Any of a number of well known compression/decompression techniques may be employed within the hardware engine 142.
In operation, the hardware engine 142 compresses some of the memory pages of the first physical memory space for storage into the DRAM 230. By compressing, this extends the amount of physical memory available in the computer system. However, the chipset 140 provides only uncompressed memory pages over bus 132 to the processor. This is done by performing decompression within the engine 142 before any pages are supplied to the processor over bus 132. Therefore, the operating system 124 sees only memory pages of the first physical memory map, e.g., uncompressed pages. It is appreciated that one uncompressed memory page of the first physical memory map may map to one or more compressed memory pages of the second physical memory map depending on the amount of compression available for the page. It is further appreciated that the decompression/compression engine does not operate on the uncompressed pages stored in DRAM 230.
Therefore, the usage model is generally to increase available memory for the computer system in an operating-system-transparent way. For example, expanding memory through compression from 256 MB to 512 MB could significantly reduce the number of disk accesses, which improves performance and reduces power consumption (e.g., for mobile disk drives). No changes in operating system software should be required. With support up to 2 GB of physical memory, up to 4 GB available memory could be offered.
As shown in
The pages of physical memory map 220 map onto physical memory map 230 a but physical memory map 220 is larger than memory map 230 a (e.g., larger than 2 GB in this example) due to page compression. The extended memory made available due to the hardware controlled page compression is shown as portion 240 which is the second portion of memory space 220. In this embodiment of the present invention, this portion 240 is not shared with the operating system but is rather used by the disk subsystem as a disk cache to increase system performance. One exemplary compressed memory page 232 is shown. Memory page 232 can be between 64 and 256 bytes in size, in one implementation. One preferred size is 128 bytes. An uncompressed memory page 222 may map to one or more compressed pages of memory map 230 a.
The amount of memory 240 will vary in size dynamically depending on the compression ratio of the memory pages within the DRAM 230 as shown by physical memory space 230 a. Although, the disk cache 240 dynamically varies in size, depending on the compression ratio achieved within the DRAM 230, in contrast, the physical memory map 220 a provided to the operating system does not vary in size. As a result, the use of the disk cache 240 as well as the compression/decompression of the memory pages are both done transparently to the operating system 124.
For example, a machine with 256 MB DRAM could have almost 512 MB available by memory extension. Of this, 256 MB could be used for the disk cache, so almost all applications will be in cache. No changes in any software is necessary in this scenario because the compression is transparent. Moreover, machines with 2 GB of physical memory could have up to 4 GB of available memory.
In a second embodiment of the present invention, the memory made available via page compression is made available transparently to the operating system in a mechanism that does not burden the operating system with the dynamically varying size of the reclaimed physical memory. Generally, the hardware presents a fixed size logical memory to the operating system (for example twice as physical size) for its use. The fixed size of the logical memory is based on a typical compression ratio. However, when the compression ratio drops to a predetermined level, the physical memory may not be unable to hold all the compressed data that the operating system thinks it can use according to the size of its logical memory. In this case, actions can occur to address this situation. Either the system starts paging-out pages in a pre-reserved disk location or the system trims the number of available pages in the operating system. For trimming the operating system pages, one embodiment uses an OS driver. The OS driver starts locking dummy pages and notifies the hardware that pages could be discarded (and released from physical memory). Therefore, according to this embodiment, the OS driver acts as a consumer of free memory from the operating system when the compression ratio goes down, and returns them back when the compression ratio improves.
The above described functionality is explained with reference to memory usage scenarios depicted in
In effect, the OS driver “steals” memory from the operating system thereby forcing the amount of used memory to decrease. The size of the memory block 280 can vary, but in the worst case situation it would be (y-x) in size and would correspond to the situation where the compression is so poor that little to no compression is happening at all.
The memory block 280 remains deallocated from the operating system until some other event occurs that obviates the need for the memory block 280. In one embodiment, the other event occurs when the used portion 236 falls below a “low threshold” point 282. Accordingly, at the low threshold point 282, a different interrupt is triggered causing the OS driver to deallocate the block 280 from its use thereby freeing the block for the operating system.
Generally, accessing compressed memory can cause a significant performance slow down. To reduce such penalty, this embodiment manages a cache of uncompressed data in volatile memory. In one embodiment, a twin-bank memory architecture cache can be used which is organized as a 2-way set associative cache, for instance, where data are stored in the DRAM 230 and tags are stored within the chip-set 140. Memory reads will start access into both DRAM banks simultaneously and in parallel with on-chip tag lookups. Since on-chip tag lookup will be completed much before DRAM access is completed, way selection can be pre fan-out. Therefore, on the memory path there will be no delays. In one embodiment, there is a multiplexer on the data path anyway, so the data transition delay is the same and control can be pre-computed a clock earlier.
In one embodiment, at least 32 MB of cache 540 is provided. With a cache line of 1 KB, it translates into 32 K lines cached in DRAM. Equivalent tags are stored on-chip. For a 4 GB physical memory, 32 bit addresses are used, with 2 way×16 MB cache, therefore, only 8 bits are used for TAG. In one example, a valid bit is not necessary if it is guaranteed that both ways will be always in use and contain valid cache line. Dirty bit is an option for reducing recompression of unmodified cache lines. An LRU bit can be used. Minimum on chip SRAM could be 16 K 8+8+1 bits (e.g., about 33 KB) in one implementation.
The physical memory space 230 a is divided into a portion 550 that contains compressed pages and a cache 540 that contains uncompressed pages. In one embodiment, frequently used pages are cached into 540. Assuming a memory size of 2 GB, for instance, the cache 540 can be approximately 32 MB with the remainder being the compressed region 550. However, the cache size can be of any length. Page requests that arrive at the chip set 140 are compared against a cache table 522 which contains a listing of cache tags (which are the MSBs of the page addresses) and their associated page designators. In one embodiment, the designators are pointers into the physical memory map 230 a for the associated page. If there is a tag hit (e.g., for page 510 b), then the requested page exists in cache memory 540 and is directly supplied to the processor by the chipset 140 without any compression/decompression involvement.
However, if there is a cache miss (e.g., page 510 a), then the page must be decompressed before it can be supplied to the processor. In this case, the translation table 144 locates the first compressed page 560 a that corresponds to the requested page 510 a. In one embodiment, there is a one-to-one mapping between the page 510 a in physical memory 270 and its first compressed page 560 a in physical memory 230 a. A hash table can be used to provide the mapping. Depending on the compression ratio, multiple compressed pages 560 a–560 c may be required to represent the requested page 510 a. In this case, each compressed page contains a pointer 592 to the next page in the sequence, if there are more than one page. In this case, the compressed pages are obtained and decompressed by engine 142 and then supplied to the processor by the chipset 140 as page 510 a.
When a new page is to be stored in cache 540 (or when more than one page is required to store a compressed page), then empty pages need to be located. In one embodiment, the empty pages are identified by placing pointers to the empty pages within a special “empty pointer page” 560 d also called a “free list.” This page 560 d contains pointers, “P,” to the empty pages. Multiple empty pointer pages 560 d–560 i can be linked together via their own pointers 590. This is an efficient mechanism for locating empty pages because it requires fewer reads since reading one page 560 d yields many free pages.
Regarding the memory space 550, when an empty page is located, or set of pages are located, the new page is compressed and stored therein. Regarding the cache 540, when an empty page is located, the cached page is written therein without compression and the cache table 520 is updated to reflect the new addition. Infrequently used pages within the cache 540 can be “cached out” of memory 540.
In one embodiment a free list 560 d is a 128 byte data block containing: (1) a header; (2) a pointer to the next data block in the free list; and (3) pointers to free blocks. In one implementation, the 128 byte block could contain 126/3=40+1 pointers and 2 bytes of CRC16 bits. CRC16 can be important because corrupting a linked list could case memory corruption or even system hanging. An exemplary data structure is shown below.
Free list data block (128 bytes):
Free list data block (128 bytes): 3 bytes 123 bytes 2 bytes NEXT FREE [0 to 39] CRC16
In one example, hardware 140 caches two or more free lists of data blocks. Released pages are appended and the requested block is removed in such case. In the case that the number of blocks in the cache is above an upper watermark, a predetermined number of data blocks pointers are removed from cache and added into the free list. In the case that number of blocks in the cache is below the lower watermark, the predetermined number of data block pointers are replenished from free list.
Generally, since all memory accesses are monitored by the system, it also monitors disk accesses to avoid duplicities of the disk cache 240 and the physical memory without cooperation from the operating system. Each time a disk page is read into memory, a page is also marked that it belongs to the disk cache. If the memory is read, then accessed bits of pages can be updated, e.g., to determine later on what should be removed from the cache. If the disk page is written by the processor, then a copy of page is made and stored in the disk cache. It still stays within the disk cache, but it is marked as removed from the physical memory. As a result, there are no duplicities in the disk cache and the physical memory because the same page is just in two lists.
With reference to
At step 605 of
Regarding page reading, if the processor reads the page, and the page (or a page pointer) is located in cache 240, then the page is supplied through the cache 240 and not from the disk. If the processor reads the page, and the page is located in the non-cache portion of 230 a, then the non-cache portion of 230 a supplies the page after decompression. If the processor reads the page, and the page is located in the cache portion 540, then portion 540 supplies the page without decompression.
Regarding page writing, at step 625, if the processor tries to update this memory page, then step 630 is entered. At step 630, before the page is modified, the page pointer is removed from the disk cache list of disk cache 240, the page is compressed (if necessary), and the compressed version is stored in the disk cache 240. Then, at step 635, the processor is allowed to modify the uncompressed page and the modified page remains in the uncompressed cache 540 and in the memory pages list.
At step 640, if the original page is requested by the processor again (e.g., the disk block is again requested), the compressed page is obtained from the disk cache 240, not from the disk storage 180. In this way, duplicate pages are not stored in memory. By performing the above procedure, the original page is not duplicated in both the disk cache 240 and the portion of the physical memory 230 a available to the operating system.
Although any form of compression can be used with the present invention, in one exemplary embodiment, 2 types of compression processes and their combinations can be employed. One is based on replacing repeating text with pointers and a second one is based on statistical distributions of values. For the first one, decompression is serial in nature and for the second one decompression could be parallel on multiple streams. Usually the highest compression ratios are achieved if pointer replacement happened first and the results are passed through encoding based on statistics.
The speed of decompression is important for reducing latency penalties. For LZ type compression, a critical feedback path is determined by memory throughput and the variable bit size decoder throughput. For Huffman type compression, it is determined by the variable bit size decoder throughput. For improving parallelism, one stream of variable bit sized codes can be split into 2 or more streams on interleaving base (knowing offsets of sub-streams). The 0.13μ standard memory generators produce SRAM running at 300 MHz or more. Having an LZ de-compressor with back pointers to minimum 2 B repeating sequences, and also assuming larger memory line reading/writing, the system can asymptotically hit almost 2 B/clock (for minimum 3 B repeating sequence hit almost 3 B/clock).
Having dual-ported memory, the system can almost double throughput, for instance, 300+MHz*2 bytes/clock*2 ports=1200 MB/s. Assuming 1 KB cache sectors, 1024 bytes/4 bytes/clock=256 clocks each 3.3 ns equals 853 ns (at least) additional latency which is realistic for minimum 3 B repeating patterns. Using register arrays, 128×64 b 2 R+2 W ports and minimum 3 B repeat pattern, then what is achieved is 1024/6 bytes/clock=171 clock*3.3 ns equals 570 ns as the worst case. Assuming a unique distribution of addresses during miss within 1024 bytes block, then the penalty for byte 0 is 0 ns and worst penalty for byte 1023 is 570 ns–3.3 ns, then the average will be a 285 ns decompression penalty. Since a cache hit ratio of 32+ MB cache will be high (over 97% can be expected), the average penalty is expected to be much less then 8.55 ns.
Latency of compression is not as important as throughput. Cache lines, which should be written-back from cache and therefore compressed can be buffered and multiple cache lines can be compressed independently in parallel. In the case that compression throughput is lower than memory write throughput (2.1 GB/s), buffers can be used to deal with burst traffic. If the system can compress 2 bytes/clock (register arrays 2 R+2 W) on 300+ MHz then one compressor will be able handle 600+ Mbytes/s. This means that 2–3 compressors can be used in the worst case according to one embodiment of the present invention.
A cache line after compression can be any arbitrary size smaller or equal to 1 KB (in the case of the cache line which cannot be compressed, it will be indicated by a dedicated bit). To avoid the problem of memory fragmentation, in one embodiment, the compressed line should be split into fixed sized blocks. 128 bytes blocks are selected to avoid wasting memory. In such case, 8×24 bit pointers are used for 2 GB physical memory. The 8×3 bytes equal 24 bytes which dictate a 32 byte index structure. This leaves 8 bytes for internal use.
An example data structure that can be used according to one exemplary embodiment is shown below:
Index entry: 1 byte 0–24 bytes 10–31 bytes 0/1 byte Header 0 . . 7 Pointers Tail bytes Split info Header: 7 6 5 4 3 2 1 0 — A M S T T T T Description: Letter Meaning — Reserved T Entry type S Split info (T = 0001–0111) present if S = 1. M Line was modified if set to 1. A Line was accessed if set to 1. Entry type (T): Value Meaning 0000–0111 Number 0–7 × 128 byte blocks needed 1000 Uncompressed, 8 × 128 byte blocks needed 1001 Entry paged-out to hard disk 1010–1111 Reserved Pointers (at byte address A): 23. 16. 15. 8. 7. 0. A + 2 A + 1 A + 0
The optional split information is an 8 bit value indicating the number of last bytes does not need to be compressed (and still does not require additional data block to be allocated). Therefore, access to the last N bytes is not delayed by decompression as a performance optimization. Assume, that on average only 5–6 of the data 8 blocks will be in use (e.g., with a 50% or less compression ratio). Assume that a compressed stream will finish on any byte boundary with equal probability. In such case, on average 64 bytes will be unused. Taking advantage of this fact, it is indicated S=1 and also indicated are the number of last bytes that are stored in uncompressed form (split info byte).
Therefore, if DRAM cache miss is in any address 0..1023 with equal probability, in 1 out if 16 cases, the system can hit the last 64 bytes, which in frequent cases will be uncompressed (and can be available immediately without sequential decompression). Tail bytes are used in case the number of bytes beyond last data block will fit into this “extension” of the data block, so no new data block needs to be allocated.
Other optimizations are described below. By placing an index into the first data block, it will be possible to start decompressing data immediately after first memory access for retrieving the index block (and data block too, if merged). From 128 bytes only 23 bytes are header in the worst case, so remaining 105 bytes could be decompressed. Assuming 4 bytes per clock can be processed, then 26 cycles*3.3 ns=86 ns are needed, which is mostly opening and reading the bank of the DRAM. First 32 bytes (16 bytes) does not need to be compressed because it will unlikely produce any benefits, but access time could be reduced by around 3.2%.
The foregoing descriptions of specific embodiments of the present invention, a method and system are described for implementing transparent compressed memory paging within a computer system, have been presented for purpose of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
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|U.S. Classification||711/113, 711/E12.019, 711/154, 711/E12.061, 710/68, 711/173, 711/170|
|International Classification||G06F12/08, G06F12/10, G06F12/00|
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|Aug 7, 2002||AS||Assignment|
Owner name: NVIDIA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DANILAK, RADOSLAV;REEL/FRAME:013182/0516
Effective date: 20020805
|Feb 21, 2003||AS||Assignment|
Owner name: NVIDLA CORPORATION, CALIFORNIA
Free format text: RE-RECORD TO CORRECT RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL/FRAME 013182/0516;ASSIGNOR:DANILAK, RADOSLAV;REEL/FRAME:013769/0325
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Owner name: NVIDIA CORPORATION, CALIFORNIA
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