|Publication number||US6975165 B2|
|Application number||US 10/942,109|
|Publication date||Dec 13, 2005|
|Filing date||Sep 15, 2004|
|Priority date||Mar 15, 2002|
|Also published as||EP1492291A1, US20050105633, WO2003079624A1|
|Publication number||10942109, 942109, US 6975165 B2, US 6975165B2, US-B2-6975165, US6975165 B2, US6975165B2|
|Inventors||Jose Ma. Lopez Villegas, Josep Samitier I Marti|
|Original Assignee||Seiko Epson Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (1), Referenced by (16), Classifications (9), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to a method and system for the conversion of Digital Phase Shift Keying signals (PSK) into Digital Amplitude Shift Keying signals (ASK). The basic operating principles of the invention are the locking of resonant circuits by superharmonic injection, together with the interference phenomena.
The cascade connection of the proposed system with an envelope detector allows the direct demodulation of Binary PSK signals (BPSK) without any need for a carrier recovery system, (i.e. Costas Loop). Both system and method can be extrapolated to the demodulation of Quadrature PSK signals (QPSK) or M-ary PSK signals (MPSK).
The general application fields of the invention are digital communications, particularly wireless digital communications.
The digital phase shift keying of a sinusoidal signal (PSK) is one of the most efficient modulation techniques, both in terms of noise immunity and required bandwidth. Nevertheless, the demodulation of PSK signals requires complex demodulator systems. Therefore, other less efficient digital modulation schemes are usually preferred because of their simpler demodulation, for instance Frequency Shift Keying (FSK) or Amplitude Shift Keying (ASK).
The simplest PSK signal is the Binary PSK signal (BPSK). In this case, the carrier phase is shifted between two possible states, 0░ and 180░, according to the bit stream. BPSK signals can be easily obtained by multiplying the carrier by +1 (0░ phase state) or by −1 (180░ phase state). From the receiver point of view, it is impossible to know if the phase of an incoming BPSK signal corresponds to 0░ state or to 180░ state. This is due to the fact that the actual propagation path from the emitter to the receiver is usually unknown. To avoid this indetermination, the information to be transmitted is coded as transitions between phase states, instead of being coded as fixed phase values. Therefor, when a logic “1” has to be transmitted then the phase of the carrier signal is shifted, whereas the phase is unchanged for a logic “0”, or vice versa. The signal coded in this way is known as Differential BPSK (DBPSK). It should be noted that from the signal point of view there is no difference between BPSK and DBPSK. The only difference between them is the pre-processing (at the transmitter side) or post-processing (at the receiver side) of the base-band signal.
The usual procedure for demodulating BPSK signals is that of coherent demodulation. Basically, the demodulation process consists of multiplying the received signal by a reference signal at the same frequency as the original carrier.
Mathematically, the BPSK signal can be expressed by:
BPSK=▒Acos (wt+φ) (1)
Where the +sign corresponds to the 0░ phase state and the—sign to the 180░ phase state. A is the amplitude of the received signal, and φ is the arbitrary phase due to signal propagation.
The reference signal, S, is given by (the amplitude is set to 1 for simplicity):
The product, P, can be expressed as follow:
P=▒A cos(wt+φ)Ěcos(wt)=▒A/2 cos(φ)▒A/2 cos(2 wt+φ) (3)
Finally, by low pass filtering P, the following base band term is obtained:
PLPF=▒A/2 cos(φ) (4)
The result is a signal, PLPF, which reproduces the original modulation (▒). From (4), if the propagation phase φ is 0░ or 180░, the efficiency of the demodulation process reach its maximum (regardless of the phase indetermination). On the contrary, if φ=▒90░, the efficiency of the demodulation process is null. This fact points out the first drawback of the coherent demodulation of PSK signals, which is the propagation phase uncertainty. The second, and most important, is the availability of a reference signal at exactly the same frequency as the original carrier.
The usual way to overcome both problems is by using a carrier recovery circuit. The most common of these circuits is the Costas Loop, the characteristics and operation of which are depicted in
In the locking state, that is to say when the error function is zero, the Costas Loop acts as a demodulator of BPSK signals. In fact, the base band modulator signal (regardless of sign uncertainty) is found at the output of the first low pass filter (LPF1 in
The main drawback of the coherent demodulation procedure is the locking time of the demodulator. During this time, the demodulator system is not working properly. This fact could lead to a loss of data at the beginning of communications or malfunctioning in burst mode communications.
In the way of an example, U.S. Pat. No. 5,347,228 employs the coherent demodulation procedure, which is based on the Costas Loop (as shown in
U.S. Pat. No. 4,631,486 proposes an alternative procedure to achieve a phase reference which permits demodulation. In this case a certain average of the received phasors is carried out, from which a phase reference estimate is obtained. Each received phasor is compared with the reference to demodulate the signal and is then used to refine the phase reference estimate. This procedure possesses the advantage of being able to correctly demodulate signals received in a discontinuous fashion, without loss of information associated with the tuning time. Its inconvenience is the greater complexity of the demodulator system and the implicit requirement to know the modulating signal bit period in order to perform phasor averaging.
Another possible demodulation procedure for signals employing digital phase modulation is the proposal in U.S. Pat. No. 4,989,220. This method is applicable to digital phase modulated signals which only involve changes between adjacent phase states. Basically, the operating principle consists of multiplying the received with the signal received in a previous time period. The time difference is obtained through the use of a delay component and is adjusted so that it is equal to the bit time. The result of this multiplication is filtered by a lowpass filter in order to produce the dc component of the resultant signal. Only when there are phase changes in a bit period will there be a change in the value of the dc component. In this case, demodulation is carried out directly, synchronization not being required. The basic disadvantage is that the modulating signal bit period must be known beforehand.
With respect to the stated background, this invention presents the advantages of coherent demodulation (input signal tracking and demodulation process which is independent of the modulating signal bit period), but without the requirement for the explicit use of a frequency and phase locking loop (PLL or Costas loop). In essence, the proposed system is a converter of digital phase modulation (PSK) signals into digital amplitude (ASK) signals. ASK modulation is the simplest modulation scheme, both from the signal generation point of view and its demodulation, however, it is not very efficient with regards to noise immunity. The information contained in an ASK signal is transmitted by modifying the amplitude between two pre-established values. Demodulation of these signal is very simple as it only requires an envelope detector, for example, a diode and lowpass filter, followed by amplification and/or signal regeneration as necessary (
This invention concerns a system and method for the conversion of digital phase modulated (PSK) signals into digital amplitude modulation (ASK) signals and is characterised because, in its simplest BPSK to ASK converter version, it consists of a power divider, PDIV, with an input injected with a BPSK signal at a frequency of 2f, where f is half the carrier signal frequency. The outputs of this divider are first, i1, which is connected to a first argument divide by two stage having a natural tuneable resonant frequency Div1, together with a second output i2 of the same amplitude, frequency and phase as i1, connected to a second argument divide-by-two stage having a natural tuneable resonant frequency Div2, obtaining an output signal O1 from the first divider Div1 and an output signal O2 from the second divider Div2 at a frequency of f and which have a phase difference of 0░ or 180░, depending on the phase changes of the input signal.
Both signals are connected to the inputs of a power combiner PC1, the output of which is the sum of the two signals O1 and O2. When the phase difference between the two is 0░, additive interference takes place in the combiner, and when this difference is 180░, a subtractive interference occurs, so that the result is an ASK signal.
The proposed system is extrapolable to phase modulation with a greater number of symbols. Thus, it is possible to construct a OPSK to ASK converter using a power divider PDIV which provides four outputs, i1, i2, i3 and i4, all with equal amplitude, frequency and phase, which feed four argument divide-by-two stages, Div1, Div2, Div3 and Div4, with tuneable resonant frequencies. The outputs of these dividers, O1, O2, O3 and O4 are made to interfere two-by-two using power combiners to generate three ASK output lines, so that each one changes its output amplitude when input phase changes of 90░, 180░ and 270░ respectively are produced. A similar procedure could be employed to make an M-PSK to M-1 parallel ASK line converter which responds to each of the possible phase changes in the input signal.
The dependency of the divider output signal phase on two arguments (O1, O2 etc), is the essential operational principle of the invention and is based on the fact that the argument dividers, Div1, present a locking phenomenon of both frequency and phase of its circuit when injected with a signal having a frequency close to the second harmonic of its fundamental resonant frequency. According to what has been established and verified by the inventors, this argument locking phenomenon (frequency and phase) is due to the non-linear response, which is presented to a greater or lesser extent by the components used in the argument divider circuit. The following may be pointed out as the more common sources of non-linearity:
Non-linearity is responsible for harmonic mixing, which then produces new spectral components. When the argument divider is injected with a signal having a frequency 2f, which is close to 2fr (where fr is the divider resonant frequency), the non-linearity (particularly those of the second order) lead to an additional contribution (of voltage and/or current) to the frequency 2f−fr≈fr. This contribution is added to that already existing at the same frequency, so that argument divider resonance characteristics are modified. It is demonstrated both analytically and experimentally, that the change in argument divider operating conditions can be expressed as a variation, Δfr, of its resonant frequency (shown in
Δfr=αAif Sin (θ) (5)
where α is a parameter which depends on the type of predominant non-linearity, Ai is the amplitude of the input signal at a frequency of 2f and angle θ is expressed as:
Where φ and φ are the input and output signal phases respectively. The value of k also depends on the non-linearity which is predominant in the circuit, for example, k=0░ if the non-linearity is due to a current which is variable with the bias voltage and k=90░ is the non-linearity is attributable to a variable capacity.
Additionally, the Oi output from an argument divider Divi, can be expressed as:
O i =A ocos (2πf t+φ) (7)
where Ao is the signal amplitude and t is the time.
By taking (7) into account, the variation in the resonant frequency can be expressed by:
By combining (5) and (6) with (8), the differential equation is obtained which governs the argument divider response dynamics to the injected input signal. The balanced state (lock-in state) is achieved when dφ/dt=0; or the same thing said in a different way, when the output signal frequency is exactly half the input signal frequency and therefore Δfr=f−fr.
By substituting this condition in (5), two possible values of balance are obtained for angle θ, which may be expressed as follows:
It has been shown that the first, θe, corresponds to a stable balance situation, whereas the second, θm, is a meta-stable balance situation. The stable balance angle θe will be small provided that the input signal has a frequency close to twice the divide-by-two argument divider's natural resonant frequency.
From (6) it can be deduced that the locking condition is not unique for output phase φ, and that there is a 180░ indetermination, which is nothing more than a mathematical consequence of the argument divide-by-two. It can also be deduced that if a phase change occurs in the input signal of value Δφ, then in order to return to the balance conditions (locking), a phase change must be produced in the output signal, Δφ, which could be:
From the analysis of the argument divider dynamic response to the input signal phase changes, it can be deduced that there is an input signal phase change critical value Δφc, which is given by:
where θm and θe are given by (9).
So that, if it is verified that:
Δφ<Δφc then Δφ=Δφ/2+180░
whereas, if it is verified that:
Δφ>Δφc then Δφ=Δφ/2
Consequently, if an argument divider Div2 is considered, with a resonant frequency of f2>f from (9), θe>0 from (11), Δφc<180░ and therefore, according to (13) an input signal phase change of 180░ would cause a 90░ phase change in output O2. On the other hand, if an argument divider Div1 is considered, with a resonant frequency of f1<f from (9), θe<0 from (11), Δφc>180░ and therefore, according to (12) an input signal phase change of 180░ would cause a 270░ (−90░) phase change in output O1. In other words, if the input signal phase changes by 180░, corresponding to a BPSK signal, O1 and O2 would become in phase opposition, or vice versa, as shown in
Finally, if both signals add, this means having minimum amplitude at the output instead of maximum, or vice versa, which constitutes am ASK signal which changes at the same rhythm as the BPSK input signal phase.
The conversion of QPSK signals to ASK can be performed by employing an extension of the proposed method. In the case of a QPSK signal, the possible phase changes are 90░, 180░ and 270░. The previously described BPSK to ASK conversion method is perfectly applicable when the phase changes are 180░. In addition, the generated ASK signal does not change when the phase changes are 90░ or 270░, provided that when 90░<Δφc<270░ for both dividers, Div1 and Div2. In effect, if this condition is verified and the input signal phase change is 90░, the phase changes for output signals O1 and O2 change in the same proportion (225░ according to (12)), so that there no changes produced in the interference (phase difference between the two). A similar situation occurs when an input signal phase change of 270░ occurs.
In order to detect the 90░ phase changes in the input signal, it is sufficient to combine the O2 output from argument divider Div2 with output O3 from the divider Div3 fed with the same QPSK signal, and to verify that ΔΦc<90░ (a condition obtained by suitably adjusting the resonant frequency of the new divider Div3). In such as situation, with an input phase change of 90░ as has been previously seen, the O2 output will change phase by 225░, whereas output O3 will change (13) by 45░. Consequently, the phase difference between the two will be modified by 180░. It can easily be demonstrated that phase changes of 180░ or 270░ in the input signal do not change the phase difference in the O2 and O3 outputs. Therefore, if both signals O2 and O3 are summed, the result will be an ASK signal which will undergo amplitude modification whenever there is an input signal phase change of 90░ and no other.
In a similar fashion, in order to detect the input signal phase changes of 270░, it is only required to combine output O1 from argument divider Div1 with the O4 output from another argument divider Div4, which verifies that Δφc>270░.
In this way, the input signal with QPSK modulation is converted into three parallel ASK signals, each of which is associated with one of the possible phase changes in the QPSK signal.
From this description, the generalisation of the method for M-PSK to M-1 parallel ASK signal conversion, which corresponds to each of the possible M-1 phase changes in the input signal is immediate, employing a suitable number of Div1 dividers and correctly adjusting their resonant frequencies.
This invention provides a system and method for the conversion of Digital Phase Shift Keying signals (PSK) into Digital Amplitude Shift Keying signals (ASK).
The analogue argument dividers of
It is important to note that the frequency and phase locking time which is a characteristic of this type of divider circuit is much faster than that associated with the Costas Loop, because it is intrinsic to the actual components and not to the locking circuit as a whole as in the Costas Loop.
The transformer and the two varactor diodes form a resonant tank circuit, the resonant frequency of which is fixed by the value of control voltage Vc. These varactor diodes may be replaced by fixed value capacitors, in which case the possibility to control the resonant frequency is lost. The purpose of the cross coupled transistor pair (these are MOSFET in
In order to understand the conversion method, the converter system in
As has already been examined, the status of the ASK system output, either in phase or 180░ phase opposition (maximum or minimum amplitude, additive or subtractive interference, respectively) is a consequence of the phase change in the BPSK input signal. This transition process is illustrated in diagrammatic form in
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|U.S. Classification||329/304, 329/347|
|International Classification||H04L27/06, H04L27/227, H04L27/22|
|Cooperative Classification||H04L27/227, H04L27/06|
|European Classification||H04L27/06, H04L27/227|
|Jan 12, 2005||AS||Assignment|
Owner name: SEIKO EPSON CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOPEZ VILLEGAS, JOSE MA;SAMITIER I MARTI, JOSEP;REEL/FRAME:015589/0227
Effective date: 20041111
|Feb 28, 2005||AS||Assignment|
Owner name: SEIKO EPSON CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOPEZ VILLEGAS, JOSE MA.;SAMITIER I MARTI, JOSEP;REEL/FRAME:015804/0140
Effective date: 20050214
|Nov 21, 2006||CC||Certificate of correction|
|Apr 10, 2007||CC||Certificate of correction|
|Jun 19, 2007||CC||Certificate of correction|
|May 13, 2009||FPAY||Fee payment|
Year of fee payment: 4
|May 15, 2013||FPAY||Fee payment|
Year of fee payment: 8