|Publication number||US6975189 B1|
|Application number||US 09/705,134|
|Publication date||Dec 13, 2005|
|Filing date||Nov 2, 2000|
|Priority date||Nov 2, 2000|
|Also published as||EP1380105A2, WO2003063348A2, WO2003063348A3|
|Publication number||09705134, 705134, US 6975189 B1, US 6975189B1, US-B1-6975189, US6975189 B1, US6975189B1|
|Inventors||Alan E. Reamon, Lloyd F. Linder, Erick M. Hirata, Nick Elmi|
|Original Assignee||Telasic Communications, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (1), Referenced by (6), Classifications (16), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of Invention
This invention relates to electrical circuit and systems. More specifically, the present invention relates to transmission lines.
2. Description of the Related Art
In electrical circuit technology the advantages of a shielded signal path are well known. In transmission lines shielded conductors are widely used. The coaxial cable is an example of an improved transmission line having well known advantages stemming from its symmetry properties.
In microcircuits it has been long desired to achieve the advantages of shielded transmission lines, but planar fabrication techniques have not been acceptable to achieve this until now. The closest prior art, are the well-known on-chip stripline and the microstrip structures. These transmission line structures are not typically isolated well from surrounding electromagnetic fields. Improvements in isolation have been achieved through physical separation from neighboring circuit elements and signal paths. However, this approach takes up valuable surface area on the chip.
There is a need for an isolated, shielded conductor used on-chip without consuming an inordinate amount of space. More specifically, there is a need for an isolated, shielded conductor used on-chip at radio frequencies (RF).
The need in the art is addressed by the on-chip multi-layer metal-shielded monolithic transmission line of the present invention. Generally, the inventive transmission line includes plural parallel planar thin film conductive layers and plural planar thin film nonconductive separator layers disposed such that each adjacent pair of the conductive layers is separated by a nonconductive layer to form a stack of alternating conductive and nonconductive layers.
In the illustrative embodiment, the invention is a planar structure with metal top and bottom planes and metal sidewalls produced by alternating thin film layers of conductors and insulators which are etched to successively build walls to a selected depth. Vias are filled with metal deposited so as to join adjacent metal layers. This four-sided metal “box” is fabricated with a metal conductor coaxially positioned to be shielded by the surrounding metal. Such structures may be constructed using standard planar technique in a side-by-side arrangement with or without common walls.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
The stripline construction 5 shown in
Each of the nonconductive separator layers 20 provides a plurality of vias 22 between the two laterally terminal 16′ and 16′″ of the three conductive strips 16′, 16″ and 16′″ and the conductive planes 12, 14. The vias 22 are cut into the separator layers 20, typically by dry etching processes that are well known, and are thereafter filled with conductive material 50, usually as part of the next metal layer deposition, for electrically interconnecting conductive strips 16′ and 16′″ and the planes 12 and 14 so as to form a conductive side wall as part of a shield about the signal carrying centermost 16″ the three conductive strips 16′, 16″ and 16′″ for electrical isolation thereof. The center strip 16″ can be made approximately one micron in width and in height by process techniques well known to the planar fabrication engineer.
Each of the other of the conductive layers 10 between the one of the conductive layers 16 and the top one of the conductive planes 14, and between the one of the conductive layers 16 and the bottom one of the conductive planes 12, comprises a pair of laterally spaced apart conductive strips separated by a nonconductive spacer layer 42 so that the pair of laterally spaced conductive strips are spaced approximately at the selected width, i.e., the stack width 32. Each of the nonconductive separator layers 20 provides a plurality of vias 22 filled with conductive material 50 conductively joining the two outermost 16′, 16′″ of the three conductive strips of the one of the conductive layers 16, and the spaced apart conductive strips of the other of the conductive layers 10, and the conductive planes 12, 14 so as to form a conductive sidewall shield about the centermost 16″ of the three laterally spaced apart conductive strips.
One of the conductive layers 16 between the top 14 and the bottom 12 conductive planes comprises a plurality of N laterally space apart conductive strips 16′, 16″, 16′″, 16 IV, 16 V, 16 VI . . . 16 N, where n is an odd integer. Each laterally adjacent pair of the conductive strips, as for instance, 16′ and 16 ″ is separated by the nonconductive spacer layer 40, and the two laterally terminal of the plurality of conductive strips, 16′ and 16 N are spaced at the selected width 32 of the stack 30.
Each of the other of the conductive layers 10 between the one of the conductive layers 16 and the top one of the conductive planes 14, and between the one of the conductive layers 16 and the bottom one of the conductive planes 12, comprises a plurality of [(N−1)/2]+1 laterally spaced apart conductive strips, where each laterally adjacent pair of the conductive strips is separated by a nonconductive spacer layer 42, the two laterally terminal of the plurality of conductive strips being spaced at the selected width 32 of the stack 30.
The nonconductive separator layers 20 provide the plurality of metal filled vias 22, where the numeral 50 is meant to indicate the metal filling that occurs when the next conductive layer 10 is applied, as described above, positioned for electrically interconnecting the plurality of the conductive strips 10 so as to electrically isolate each of (N−1)/2 of the signal carrying conductive strips 16″, 16′V, 16 V′, etc. This enables the placement of any number of fully shielded signal carrying conductors in side-by-side positions on the substrate. Because elongated vias 22 have a limited length, a limitation on the technology, as shown in
As shown in
The method of making the on-chip multiple layer metal-shielded monolithic transmission line comprises the steps of forming the plurality of parallel planar thin film, conductive layers 10, by vapor deposition for instance, each in turn, separated by a plurality of planar thin film nonconductive separator layers 20, each also deposited or grown in turn, to form a stack 30 of alternating conductive and nonconductive said layers.
The process further comprises the step of extending, by simple metal deposition, the initial 12 and the final 14 ones of conductive layers, as the top and the bottom conductive planes, to define the mutually registered selected width 32 of the stack 30.
Further, the inventive process includes the step of forming one layer 16, usually the center layer, of the conductive layers 10 between the initial (bottom) and the final (top) conductive planes 12, 14 into a plurality of N laterally spaced apart conductive strips 16′, 16″, etc., where N is an odd integer. This may be carried out by masking and etching steps as is well known in the art. Each of the adjacent pairs of the conductive strips are separated as well by the same technique so that each laterally adjacent pair of the conductive strips is interposed by a nonconductive spacer layer 40 and spacing the two laterally terminal of the plurality of conductive strips is such as to position then at the selected width 32 of the stack 30 by proper masking and registration steps as is well known in the art.
Likewise, the conductive layers 10 between the one of the conductive layers 16 and the top one 14 of the conductive planes, and between the one of the conductive layers and the bottom one 12 of the conductive planes are separated into a plurality of [(N−1)/2]+1 laterally spaced apart conductive strips as is shown in
The only process requirement is that the number of metal layers, be greater than 3. However, the fine line geometry of the metal used in BiCMOS or a fineline multilayer CMOS process allows the thickness and minimum width of the metal conductor to be on the same order, thereby allowing the conductor to have the characteristics of an on-chip coaxial line. The novel structure is monolithic, exceeds typical isolation requirements, and uses significantly less surface area than microstrip or stripline structures in order to achieve the same isolation characteristics. A unique feature of the implementation is the use of continuous vias so as to encase the center conductor. This feature maintains tight routing while meeting isolation requirements.
The invention provides an isolated on-chip coaxial conductor. Isolation is almost perfect in the present case. This is possible due to the use of multilayer metal and nearly continuous interlayer metal via stacks along ground shield walls of the conductor. In the limit, conductor spacing can be minimized to a shared ground plane consisting of all layers of metal with nearly continuous stacked metal vias between these metal layers. This approach enables large matrix arrays to be implemented as monolithic structures so as to meet stringent isolation requirements while maintaining a relatively small die size. Using multi-layer metal, internal layers can be used as ground planes to provide for the routing of multi-signal paths in a parallel fashion in the x- and y- directions. For example, a five layer metal process allows the placement of signal conductors on metal layers 2 and 4, with ground shielding on layers 1, 3, and 5. (
In a preferred embodiment, five metal layers are placed and an isolated center conductor is provided. This allows a minimum impact from parasitics. From a symmetry standpoint it allows the coaxial solution. For three or more layers the conductor is placed at the center of the stack of layers. Current fine geometry techniques enable dimensions of the conductor to approximate a coaxial line when shielded. An important feature is the stacked, stretched, multi-layer vias, which enable nearly continuous closure of the center conductor, depending on the yield limits of a particular process technology for vias.
When adjacent conductors do not share a common ground shield, interlayer metal via stacks may be staggered. This approach eliminates any direct coupling between two adjacent conductors. Increasing spacing between ground shields further isolates the signals.
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof.
It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4673904 *||Nov 14, 1984||Jun 16, 1987||Itt Corporation||Micro-coaxial substrate|
|US4776087 *||Apr 27, 1987||Oct 11, 1988||International Business Machines Corporation||VLSI coaxial wiring structure|
|US5408053 *||Nov 30, 1993||Apr 18, 1995||Hughes Aircraft Company||Layered planar transmission lines|
|US5438167 *||Oct 19, 1993||Aug 1, 1995||Hughes Aircraft Company||Ferrimagnetic vias within multi-layer 3-dimensional structures/substrates|
|US5574415 *||Jun 11, 1992||Nov 12, 1996||Peterson; Robert K.||Method of fabricating microwave interconnects and packaging and the interconnects and packaging|
|US5729047 *||Mar 25, 1996||Mar 17, 1998||Micron Technology, Inc.||Method and structure for providing signal isolation and decoupling in an integrated circuit device|
|US5965935||Nov 5, 1997||Oct 12, 1999||Itt Industries, Inc.||Low loss ridged microstrip line for monolithic microwave integrated circuit (MMIC) applications|
|US6000120 *||Apr 16, 1998||Dec 14, 1999||Motorola, Inc.||Method of making coaxial transmission lines on a printed circuit board|
|US6133621 *||Dec 30, 1998||Oct 17, 2000||Stmicroelectronics S.R.L.||Integrated shielded electric connection|
|US6569757 *||Oct 28, 1999||May 27, 2003||Philips Electronics North America Corporation||Methods for forming co-axial interconnect lines in a CMOS process for high speed applications|
|EP0867929A2||Mar 25, 1998||Sep 30, 1998||P.C.B. Ltd.||Electronic interconnect structure and method for manufacturing it|
|1||Title: Theorectical Analysis of Microshield Transmission Lines with Dual-plane Discontinuities, 9th Annual Review of Progress in Applied Computational Electromagnetics at the Naval Postgraduate School, Monterey, CA, USA, Mar. 22-26, 1993. Conference Proceedings.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8044388||Jul 21, 2009||Oct 25, 2011||Nantero, Inc.||Method of forming a carbon nanotube-based contact to semiconductor|
|US8138563||Aug 8, 2008||Mar 20, 2012||International Business Machines Corporation||Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference|
|US8273648||Sep 25, 2012||International Business Machines Corporation||Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference|
|US20100032814 *||Feb 11, 2010||International Business Machines Corporation||Circuit structures and methods with beol layers configured to block electromagnetic edge interference|
|US20100148183 *||Jul 21, 2009||Jun 17, 2010||Ward Jonathan W||Method of Forming a Carbon Nanotube-Based Contact to Semiconductor|
|WO2008115652A1 *||Feb 20, 2008||Sep 25, 2008||Nantero, Inc.||Method of forming a carbon nanotube-based contact to semiconductor|
|U.S. Classification||333/238, 257/728, 257/664, 257/E23.114, 333/243|
|International Classification||H01L23/552, H01P3/08, H01L23/522|
|Cooperative Classification||H01L2924/0002, H01P3/088, H01L23/5225, H01L23/552, H01L2223/6622|
|European Classification||H01L23/522C6, H01L23/552, H01P3/08D|
|Apr 23, 2001||AS||Assignment|
Owner name: RAYTHEON COMPANY, MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REAMON, ALAN E.;LINDER, LLOYD;HIRATA, ERICK M.;AND OTHERS;REEL/FRAME:011745/0428;SIGNING DATES FROM 20001117 TO 20001207
|Jul 23, 2002||AS||Assignment|
Owner name: TELASIC COMMUNICATIONS, INC., CALIFORNIA
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Effective date: 20020702
|Aug 26, 2002||AS||Assignment|
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