|Publication number||US6985783 B2|
|Application number||US 09/827,644|
|Publication date||Jan 10, 2006|
|Filing date||Apr 6, 2001|
|Priority date||May 2, 1997|
|Also published as||US6272615, US20020193893|
|Publication number||09827644, 827644, US 6985783 B2, US 6985783B2, US-B2-6985783, US6985783 B2, US6985783B2|
|Inventors||Stephen (Hsiao Yi) Li, Jonathan Rowlands, Fuk Ho Pius Ng, Maria B. H. Gill|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (3), Referenced by (9), Classifications (33), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division of application Ser. No. 08/851,573, filed May 2, 1997 now U.S. Pat. No. 6,272,615.
This invention relates in general to the field of electronic systems and more particularly to an improved modular audio data processing architecture and method of operation.
Audio and video data compression for digital transmission of information will soon be used in large scale transmission systems for television and radio broadcasts as well as for encoding and playback of audio and video from such media as digital compact cassette and minidisc.
The Motion Pictures Expert Group (MPEG) has promulgated the MPEG audio and video standards for compression and decompression algorithms to be used in the digital transmission and receipt of audio and video broadcasts in ISO-11172 (hereinafter the “MPEG Standard”). The MPEG Standard provides for the efficient compression of data according to an established psychoacoustic model to enable real time transmission, decompression and broadcast of CD-quality sound and video images. The MPEG standard has gained wide acceptance in satellite broadcasting, CD-ROM publishing, and DAB. The MPEG Standard is useful in a variety of products including digital compact cassette decoders and encoders, and minidisc decoders and encoders, for example. In addition, other audio standards, such as the Dolby AC-3 standard, involve the encoding and decoding of audio and video data transmitted in digital format.
The AC-3 standard has been adopted for use on laser disc, digital video disk (DVD), the US ATV system, and some emerging digital cable systems. The two standards potentially have a large overlap of application areas.
Both of the standards are capable of carrying up to five full channels plus one bass channel, referred to as “5.1 channels,” of audio data and incorporate a number of variants including sampling frequencies, bit rates, speaker configurations, and a variety of control features. However, the standards differ in their bit allocation algorithms, transform length, control feature sets, and syntax formats.
Both of the compression standards are based on psycho-acoustics of the human perception system. The input digital audio signals are split into frequency subbands using an analysis filter bank. The subband filter outputs are then downsampled and quantized using dynamic bit allocation in such a way that the quantization noise is masked by the sound and remains imperceptible. These quantized and coded samples are then packed into audio frames that conform to the respective standard's formatting requirements. For a 5.1 channel system, high quality audio can be obtained for compression ratio in the range of 10:1.
The transmission of compressed digital data uses a data stream that may be received and processed at rates up to 15 megabits per second or higher. Prior systems that have been used to implement the MPEG decompression operation and other digital compression and decompression operations have required expensive digital signal processors and extensive support memory. Other architectures have involved large amounts of dedicated circuitry that are not easily adapted to new digital data compression or decompression applications.
An object of the present invention is provide an improved apparatus and methods of processing MPEG, AC-3 or other streams of data.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
In general, and in a form of the present invention a data processing device for processing a stream of data is provided which has a central processing unit (CPU) with an instruction register for holding an instruction. The CPU is operable to process a data word in response to the instruction. An index register connected to the CPU is operable to provide a base address in response to the instruction. Address circuitry is connected to the CPU and is operable to form an address of the data word by combining a portion of the base address with a portion of an immediate field in the instruction.
In another form of the invention, decoder circuitry is connected to the address circuitry and selects a certain width for the base portion of the address in response to a field in the instruction.
In another form of the instruction, a method is provided for accessing multiple data structures in a data processing system using a common index value. The method first initializes an index register within the data processing system with the common index value. A first instruction is executed which has an indexed immediate addressing mode, wherein the first instruction has an immediate value comprising a first base value, such that a first data structure in a first portion of memory of the data processing system is accessed by the first instruction. A second instruction is executed which also has an indexed immediate addressing mode, wherein the second instruction has an immediate value comprising a second base value, such that a second data structure in a second portion of memory of the data processing system is accessed by the second instruction using the same index value as the first instruction.
In another form of the invention, a method is provided for performing multi-way branching in a data processing system. An index register is first initialized with a data value that is indicative of a target address in a group of instructions. A branch instruction having an indexed immediate addressing mode is executed that has an immediate field with a base value that points to the group of instructions. A specific target instruction is branched to by combining the base value and the target address.
Other embodiments of the present invention will be evident from the description and drawings.
Other features and advantages of the present invention will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures and tables refer to corresponding parts unless otherwise indicated.
Aspects of the present invention include methods and apparatus for processing and decompressing an audio data stream. In the following description, specific information is set forth to provide a thorough understanding of the present invention. Well known circuits and devices are included in block diagram form in order not to complicate the description unnecessarily. Moreover, it will be apparent to one skilled in the art that specific details of these blocks are not required in order to practice the present invention.
The present invention comprises a system that is operable to efficiently decode a stream of data that has been encoded and compressed using any of a number of encoding standards, such as those defined by the Moving Pictures Expert Group (MPEG-1 or MPEG-2), or the Digital Audio Compression Standard (AC-3), for example. In order to accomplish the real time processing of the data stream, the system of the present invention must be able to receive a bit stream that can be transmitted at variable bit rates up to 15 megabits per second and to identify and retrieve a particular audio data set that is time multiplexed with other data within the bit stream. The system must then decode the retrieved data and present conventional pulse code modulated (PCM) data to a digital to analog converter which will, in turn, produce conventional analog audio signals with fidelity comparable to other digital audio technologies. The system of the present invention must also monitor synchronization within the bit stream and synchronization between the decoded audio data and other data streams, for example, digitally encoded video images associated with the audio which must be presented simultaneously with decoded audio data. In addition, MPEG or AC-3 data streams can also contain ancillary data which may be used as system control information or to transmit associated data such as song titles or the like. The system of the present invention must recognize ancillary data and alert other systems to its presence.
In order to appreciate the significance of aspects of the present invention, the architecture and general operation of a data processing device which meets the requirements of the preceding paragraph will now be described. Referring to
The design of device 100 includes two autonomous processing units working together through shared memory supported by multiple I/O modules. The operation of each unit is data-driven. The synchronization is carried out by the Bit-stream Processing Unit (BPU) which acts as the master processor. Bit-stream Processing Unit (BPU) 110 has a RAM 111 for holding data and a ROM 112 for holding instructions which are processed by BPU 110. Likewise, Arithmetic Unit (AU) 120 has a RAM 121 for holding data and a ROM 122 for holding instructions which are processed by AU 120. Data input interface 130 receives a stream of data on input lines DIN which is to be processed by device 100. PCM output interface 140 outputs a stream of PCM data on output lines PCMOUT which has been produced by device 100. Inter-Integrated Circuit (I2C) Interface 150 provides a mechanism for passing control directives or data parameters on interface lines 151 between device 100 and other control or processing units, which are not shown, using a well known protocol. Bus switch 160 selectively connects address/data bus 161 to address/data bus 162 to allow BPU 110 to pass data to AU 120.
A typical operation cycle is as follows: Coded data arrives at the Data Input Interface 130 asynchronous to device 100's system clock, which operates at 27 MHz. Data Input Interface 130 synchronizes the incoming data to the 27 MHz device clock and transfers the data to a buffer area 114 in BPU memory 111 through a direct memory access (DMA) operation. BPU 110 reads the compressed data from buffer 114, performs various decoding operations, and writes the unpacked frequency domain coefficients to AU RAM 121, a shared memory between BPU and AU. Arithmetic Unit 120 is then activated and performs subband synthesis filtering, which produces a stream of reconstructed PCM samples which are stored in output buffer area 124 of AU RAM 121. PCM Output Interface 140 receives PCM samples from output buffer 124 through a DMA transfer and then formats and outputs them to an external D/A converter. Additional functions performed by the BPU include control and status I/O, as well as overall system resource management.
BPU 110 is capable of performing an ALU operation, a memory I/O, and a memory address update operation in one system clock cycle. Three addressing modes: direct, indirect, and registered are supported. Selective acceleration is provided for field extraction and buffer management to reduce control software overhead. Table 1 is a list of the instruction set.
BPU Instruction Set
Rotate right with carry
Add with carry
Logical exclusive or
Subtract with borrow
Conditional 2's complement
Decrement & conditional branch
IO reg to memory move
Memory to IO reg move
AU operation - loosely coupled
AU execution - tightly coupled
Power down unit
BPU 110 has two pipeline stages: Instruction Fetch/Predecode which is performed in Micro Sequencer 230, and Decode/Execution which is performed in conjunction with instruction decoder 231. The decoding is split and merged with the Instruction Fetch and Execution respectively. This arrangement reduces one pipeline stage and thus branching overhead. Also, the shallow pipe operation enables the processor to have a very small register file (four general purpose registers, a dedicated bit-stream address pointer, and a control/status register) since memory can be accessed with only a single cycle delay.
The AU 120 module receives frequency domain coefficients from the BPU by means of shared AU memory 121. After the BPU has written a block of coefficients into AU memory 121, the BPU activates the AU through a coprocessor instruction, auOp. BPU 110 is then free to continue decoding the audio input data. Synchronization of the two processors is achieved through interrupts, using interrupt circuitry 240 (shown in
AU 120 is a 24-bit RISC processor with a register-to-register operational unit 300 and an address generation unit 320 operating in parallel. Operational unit 300 includes a register file 301, a multiplier unit 302 which operates in conjunction with an adder 303 on any two registers from register file 301. The output of adder 303 is provided to input mux 305 which is in turn connected to register file 301 so that a result can be stored into one of the registers.
A bit-width of 24 bits in the data path in the arithmetic unit was chosen so that the resulting PCM audio will be of superior quality after processing. The width was determined by comparing the results of fixed point simulations to the results of a similar simulation using double-precision floating point arithmetic. In addition, double-precision multiplies are performed selectively in critical areas within the subband synthesis filtering process.
The software architecture block diagram is illustrated in
The software operates as follows. Data Input Interface 410 buffers input data and regulates flow between the external source and the internal decoding tasks. Transport Decoder 420 strips out packet information from the input data and emits a raw AC-3 or MPEG audio bit-stream, which is processed by Audio Decoder 430. PCM Output Interface 440 synchronizes the audio data output to a system-wide absolute time reference and, when necessary, attempts to conceal bit-stream errors. I2C Control Interface 450 accepts configuration commands from an external host and reports device status. Finally, Kernel 400 responds to hardware interrupts and schedules task execution.
Alternatively, processing device 100 can be programmed to provide up to six channels of PCM data for a 5.1 channel sound reproduction system if the selected audio data stream conforms to MPEG-2 or AC-3. In such a 5.1 channel system, D/A 530 would form six analog channels for six speaker subsystems 540 a–n. Each speaker subsystem 540 contains at least one speaker and may contain an amplification circuit (not shown) and an equalization circuit (not shown).
The SPDIF (Sony/Philips Digital Interface Format) output of device 100 conforms to a subset of the Audio Engineering Society's AES3 standard for serial transmission of digital audio data. The SPDIF format is a subset of the minimum implementation of AES3. This stream of data can be provided to another system (not shown) for further processing or re-transmission.
Referring now to
The consolidation of all these functions onto a single chip with a large number of communications ports allows for removal of excess circuitry and/or logic needed for control and/or communications when these functions are distributed among several chips and allows for simplification of the circuitry remaining after consolidation onto a single chip. Thus, audio decoder 354 is the same as data processing device 100 with suitable modifications of interfaces 130, 140, 150 and 170. This results in a simpler and cost-reduced single chip implementation of the functionality currently available only by combining many different chips and/or by using special chipsets.
A novel aspect of data processing device 100 will now be discussed in detail, with reference to
The sources of an BPU operation can be any BPU register. If the destination is a register, then it is one of the source registers. If the destination is memory or an index register, then the result is not loaded into the BPU register file.
The destination of a memory load is always one of two BPU registers, either R0 or R1. To load multiple BPU registers in sequence, an BPU operation can be pipelined to move the previously loaded value into its correct location, concurrently with the read. The purpose in restricting the register that can be loaded into is to minimize the number of registers that have more than one source for a load.
Opcode field 800 defines the operation of the instruction. Source field 801 and source/destination field 802 specify the source and destination registers from register file 201, as shown in Table 2. Memory operation field 803 specifies a memory operation, as shown in Table 3. Memory mode field 804 specifies the addressing mode of a memory operation, as shown in Table 4. Adreessing modes will be discussed in more detail later with respect to
ALU SRC and SRC/DST Field Codes
ALU register 0
ALU register 1
ALU register 2
ALU register 3
I/O enable register
constant value of all ones
bit address pointer
MEM OP Field Codes
no memory operation
store ALU result to memory
load immed/memory into R0
load immed/memory into R1
MEM Mode Field Codes
direct memory address
register IRx or R0 or R6
indirect via IRx or R0 or R6
Interrupts will not be serviced until after the instruction in the delay slot has been executed. A branch instruction may not appear in the delay slot of another branch instruction.
All addressing modes are allowable for branches. In particular the table lookup, referred to as “indexed immediate,” addressing mode is valuable for computed branches via a jump table, and the direct mode for interrupt and subroutine return.
The decrement and branch instruction (DBcc) is a conditional branch where the conditional is whether a given index register is non-zero or not. The register is always decremented. This is used to implement loop counters.
The Dbcc instruction has the same opcode and format as an ordinary conditional branch, being just one of the possible conditions. However, since an index register must be specified in addition to the branch destination, a separate two bit field must be used for the index register number. Only index registers 0–3 can be used in the decrement and branch instruction.
Since index register file 221 is single read and write, this means that the destination address of the decrement and branch instruction cannot involve an index register computation. This is enforced by the microcode assembler. All other addressing mode are allowed as for branch instructions.
Referring still to
CC Field Codes
prev result == 0
prev result != 0
prev result < 0 (signed)
prev result >= 0 (signed)
prev result > 0 (signed)
prev result <= 0 (signed)
prev result >= 0 (unsigned)
prev result < 0 (unsigned)
prev result > 0 (unsigned)
prev result <= 0 (unsigned)
IRx == 0
IRx != 0
According to an aspect of the present invention, indirect mode can optionally replace some high order bits of the memory address with immediate bits from the instruction. This optional mode is referred to as “indexed immediate addressing mode.” This allows the base address for a table lookup to be specified in the instruction, with the index coming from an index register or BPU register. There are at least three advantageous uses for this:
Index registers IR0-5 can optionally be modified concurrently with an indirect addressing operation. The possible modifications are post-increment or decrement by one, and post-load from the operational unit 200 result. The increment and decrement modifications allow stepping through arrays. The load modification is used to load an index register from the BPU register file.
When used in an addressing mode, BPU register R6 (alternate name “BIT”) simulates bit addressing. If R6<15:0> is assumed to be a bit address, then bits R6<15:4> form the least significant 12 bits of the 14 bit word address, the most significant bits being set to zero. This value becomes the input to the address computation which is otherwise the same as for R0. Bits R6<3:0> are used by the get bit field instruction to complete the bit addressing function.
Register addressing mode has the same instruction format as indirect mode. The meaning of the fields is identical, however the result value is the computed memory address itself rather than the contents of memory at that address. This can be used to load the value of an index register into the BPU register file, or to compute the actual address referred to by an addressing operation.
Index Register Operation Field Codes
post-increment by one
post-decrement by one
post-load with ALU result
Index Register Source/Destination Field Codes
index register 0
index register 1
index register 2
index register 3
index register 4
index register 5
BPU register 0
BPU register 6 (drop 4 LSBs)
Source/Destination Field 832 Codes
BPU register 0
BPU register 6 (drop 4 LSBs)
Still referring to
Still referring to
The advantages of a variable size table selection are not limited to this embodiment. Devices with different address widths can be similarly enabled by modifying the width of the immediate field or by padding the output of mux 910 with a preselected fixed or variable value in order to form a final address with an appropriate number of bits.
Short Table Field Codes
INSTRUCTION REG BITS
2 0 8765
table size 64
table size 128
table size 256
table size 512
table size 1024
Long Table Field Codes
INSTRUCTION REG BITS
2 0 876543
table size 16
table size 32
table size 64
table size 128
table size 256
table size 512
table size 1024
In the table addressing mode, the more significant bits (4–12 for index register mode—
When applied to data look-up, like sine/cosine tables, the starting point, or base, of the table and its size is passed on to the assembler during assembling time. The assembler then checks for alignments (i.e. tables with 16 entries need to be aligned to 16 boundaries, that is, the least significant four bits of the base address need to be 0). It then inserts the appropriate ms bits of the table base address into the instruction word (nine in case of 16 entry table, the total address is 13 bits).
When indexed-immediate addressing mode is applied to multi-way branch, an additional step is to build the branch table by copying branch-target addresses into the table (as compared with data tables in which the contents are known), after that it is assembled the same way as data look-up. One simple example to illustrate multi-way branch: MPEG standard has 3 “layers”. Two bits in the header indicates the layer. The decoding is different for each layer. One way to do this would be to put the 3 starting addresses of the decoding section for each layer into a 4 entry table. The value of the two layers would then read into R0, for example, and then a branch table(MPEG—layer, R0) is executed, where MPEG—layer is the most significant bits indicating the starting address of the table and the Is bits of R0 are used as an index.
An alternative embodiment of the novel aspects of the present invention may include other circuitries which are combined with the circuitries disclosed herein in order to reduce the total gate count of the combined functions. Since those skilled in the art are aware of techniques for gate minimization, the details of such an embodiment will not be described herein.
Other types of processing devices having a Central processing unit (CPU) connected to an instruction register can advantageously incorporate aspects of the present invention.
Fabrication of data processing device 100 involves multiple steps of implanting various amounts of impurities into a semiconductor substrate and diffusing the impurities to selected depths within the substrate to form transistor devices. Masks are formed to control the placement of the impurities. Multiple layers of conductive material and insulative material are deposited and etched to interconnect the various devices. These steps are performed in a clean room environment.
A significant portion of the cost of producing the data processing device involves testing. While in wafer form, individual devices are biased to an operational state and probe tested for basic operational functionality. The wafer is then separated into individual devices which may be sold as bare die or packaged. After packaging, finished parts are biased into an operational state and tested for operational functionality.
As used herein, the terms “applied,” “connected,” and “connection” mean electrically connected, including where additional elements may be in the electrical connection path.
While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.
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|U.S. Classification||700/94, 710/200, 712/E09.04, 712/E09.075, 710/220, 386/241|
|International Classification||G06F9/38, G06F9/345, G06F9/355, G06F12/00, G06F13/22, H04N5/91, G06F9/35, G06F17/00, G06F9/32|
|Cooperative Classification||G06F9/3004, G06F9/30167, G06F9/30061, G06F9/322, G06F9/325, G06F9/355, G06F9/383, G06F9/35, G06F9/345|
|European Classification||G06F9/30T4T, G06F9/30A3C2, G06F9/38D2, G06F9/355, G06F9/32B6, G06F9/345, G06F9/30A2, G06F9/32B, G06F9/35|
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