|Publication number||US6988154 B2|
|Application number||US 09/801,241|
|Publication date||Jan 17, 2006|
|Filing date||Mar 7, 2001|
|Priority date||Mar 10, 2000|
|Also published as||US8688879, US8959269, US9418042, US20030009612, US20060174081, US20090055565, US20140281114, US20150154143, WO2001069411A2, WO2001069411A3|
|Publication number||09801241, 801241, US 6988154 B2, US 6988154B2, US-B2-6988154, US6988154 B2, US6988154B2|
|Original Assignee||Arc International|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (32), Non-Patent Citations (13), Referenced by (32), Classifications (18), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority benefit to U.S. provisional patent application Ser. No. 60/188,546 filed Mar. 10, 2000 and entitled “Memory Interface and Method of Interfacing Between Integrated Circuits.”
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
This application is related to pending U.S. patent application Ser. No. 09/418,663 filed Oct. 14, 1999 entitled “Method and Apparatus for Managing the Configuration and Functionality of a Semi-Conductor Design”, which claims priority benefit of U.S. provisional patent application Ser. No. 60/104,271 filed Oct. 14, 1998, of the same title.
1. Field of the Invention
The present invention relates to the field of integrated circuit design, specifically to the integration of peripheral components and macro functions with a central processing unit (CPU) or user-customizable microprocessor.
2. Description of Related Technology
As semiconductor processing capabilities increase the number of transistors that can be economically built on a single Integrated Circuit (IC), systems designers are made less effective by the difficulty encountered in combining large-scale macro blocks on a single IC. Such large-scale macro blocks (or “macro functions”) include, for example, those associated with third generation (“3G”) communications architectures, such as functions performing Viterbi butterfly decode, cyclic redundancy checks (CRC), convolutional encoding/decoding, permutation, and carrier modulation/demodulation. Some of the problems encountered by the designer are underscored by the need to integrate special purpose functions with an existing instruction set implemented by a given central processing unit (CPU). Often, a non-integrated design approach is employed, wherein the large-scale macro blocks or functions are treated as separate entities from the processor core, thereby requiring additional complexity, as well as specialized or unique interfaces between the core and its associated functions which are not standardized across the device. Specifically, with respect to memory interfaces, the use of control registers associated with the memory ports of the interface not only complicates the design, but also may under certain circumstances limit or restrict the functionality of the interface. For example, individual macro blocks associated with the design may be precluded from acting on data in separate memory banks simultaneously, thereby hindering the performance of the design as a whole by requiring that memory accesses be performed in “lock-step” fashion.
Prior art treatment of large-scale macro functions as separate entities within the design has further disabilities relating to memory. In particular, since the macro block is effectively a separate entity from the core, memory interfaces to existing core memory are often quite complex, thereby often necessitating the provision of separate memory dedicated to the macro function (or shared between multiple macro functions). The requirement for such additional memory adds cost and complexity to the device, as well as monopolizing already precious real estate on the die. This is especially true for so-called “system-on-a-chip” (SoC) designs, where available memory is often a limiting parameter. Additionally, such dedicated “off-core” memory is by definition not local to the core, and hence results in increased latency when such memory must be accessed by the core.
Furthermore, as more such large-scale macro function blocks are added to the design, the propensity for such increased complexity and non-standardization across the design increases accordingly.
Furthermore, conventional interface mechanisms are typically based on a common bus, and transfers between peripherals and the core(s) are arbitrated by one or more direct memory access (DMA) controllers. However, under such an approach, the timed transfer of data may not be deterministic, which is often a crucial requirement for DSP applications. Specifically, DSP systems often require not only that data are processed correctly mathematically, but that results are delivered at the right time. In this sense a “deterministic” transfer is one for which the timing is exactly known.
Based on the foregoing, there is a need for an improved apparatus and method for enabling macro functions and peripherals present on an integrated device to interface with the device processor core in a simple and standardized manner. Such improved interface would not only allow for standardized interface between macro-functions across the device, but also allow multiple macros to interface with individual (or a plurality of) memory banks simultaneously. Such improved apparatus and method would also ideally obviate separate or discrete local memory now used in support of macro (e.g., DSP core) functions, and facilitate deterministic transfer of data between functional entities in the design.
The present invention satisfies the aforementioned needs by an improved apparatus and method for interfacing between integrated circuit devices, such as between a digital processor and associated memory array.
In a first aspect of the invention, an improved interface apparatus useful for interfacing between an external device and one or more processor functions is disclosed. In one exemplary embodiment, the external device comprises a memory array, and the interface comprises a plurality of memory ports, a plurality of function ports with associated function controllers, a crossbar connecting the memory ports to the function ports, and an arbitration unit for arbitrating memory accesses and facilitating burst load/store operations. The interface apparatus enables a macro block to be integrated with the CPU, controlled with a custom processor instruction, and act directly on CPU local memory banks. Other macro blocks can also access data in other banks simultaneously. Under CPU control, blocks of data can be acted on by macro functions in a pipelined fashion. The local CPU memory banks therefore replace memory that might otherwise be duplicated in the macro block. Once acquired, data is local to the CPU which can also act on it without unnecessary additional latency.
In a second aspect of the invention, an improved data transfer protocol used in conjunction with the aforementioned interface is disclosed. In one embodiment, the protocol comprises a synchronous protocol using a plurality of registers disposed within the aforementioned functional control units of the function ports. Data exchange with the memory interface is synchronized with the clock of the processor core, and data is strobed in and out of the memory after memory access has been requested and granted. The grant of memory access requests is delayed if the requested memory bank is being accessed for a burst load/store operation, or by the processor core. The protocol of the invention supports, in conjunction with the memory interface, multiple simultaneous strobed accesses to different memory banks by different macro functions (function ports) associated with the interface.
In a third aspect of the invention, an improved data processing apparatus is disclosed. The device generally comprises a processor core, the aforementioned memory interface, at least one macro function, XY memory array, and I/O interface. In one exemplary embodiment, the processor core comprises an extensible Reduced Instruction Set Computer (RISC) based digital processor, and the macro function comprises a digital signal processor (DSP). The DSP may be a general purpose DSP, or alternatively any one of a number of algorithmically optimized designs which are adapted to perform certain data processing tasks. The RISC processor and DSP are tightly coupled such that the DSP and memory interface effectively become part of the RISC processor's instruction set, the macro function (DSP) being controlled by, for example, decoded instructions generated by the pipeline decode stage of the RISC processor. Furthermore, peripheral devices can have direct memory access (DMA) capability with respect to the XY memory array via the I/O interface. The components are also advantageously combined into a single-die integrated circuit device. In another embodiment, the device comprises a “3G” ASIC having a plurality of macro blocks including a signal receiver and demodulator, “turbo” or Viterbi decoder, block cyclic redundancy code (CRC) calculation macro, block permute macro, block convolution encoder macro, and modulator and transmitter, all of which are coupled to the core memory array via the memory interface.
In a fourth aspect of the invention, a method of interfacing between a memory and one or more processor functions is disclosed. In one exemplary embodiment, the method comprises specifying a number of function ports for an interface; specifying a number of memory ports for the interface; setting a number of control and other registers based on the function port configuration; specifying an interface protocol; initiating the function(s) associated with the function port(s); arbitrating one or more memory accesses; and performing read/write access to memory according to the selected protocol and control by the parent processor core.
In a fifth aspect of the invention, a method of testing a function associated with the previously described memory interface is disclosed. In one exemplary embodiment, the method comprises providing a memory interface having at least one memory port and associated memory array, at least one function port and associated function, and at least one control register used for controlling said function; providing a test sequence; providing an input test value in the memory array; initiating the function; generating results from the operation of the function on the input test value; and comparing the results returned by the function against a known value in order to test the operation of the function.
In a sixth aspect of the invention, an improved method of designing an integrated circuit device having an extensible processor core, secondary processor (e.g., DSP) or macro function, and memory interface is disclosed. In one embodiment, the method comprises providing an extensible core; providing at least one macro function; providing at least one memory interface; adding an HDL (hardware description language) “wrapper” around the DSP or macro function, the HDL wrapper adapted to (i) translate signals, (ii) buffer memory interfaces, and (iii) synchronize clock signals with the memory interface. In another embodiment, the method comprises providing an extensible core; providing at least one “soft” macro function; providing at least one memory interface as described previously herein; and adapting the “soft” macro function implementation to meet the specification associated with the memory interface.
Reference is now made to the drawings wherein like numerals refer to like parts throughout.
As used herein, the term “processor” is meant to include any integrated circuit or other electronic device capable of performing an operation on at least one instruction word including, without limitation, extensible reduced instruction set core (RISC) processors such as the ARC™ user-configurable core manufactured by the Assignee hereof, central processing units (CPUs), and digital signal processors (DSPs). Furthermore, various functional aspects of the processor may be implemented solely as software or firmware associated with the processor.
As used herein, the term “parent” processor refers generally to the aforementioned ARC core (or similar), while the term “host” processor refers generally to an external processor which controls the operation of the ARC core and/or other functional aspects of the design.
Additionally, it will be recognized by those of ordinary skill in the art that the term “stage” as used herein refers to various successive stages within a pipelined processor; i.e., stage 1 refers to the first pipelined stage, stage 2 to the second pipelined stage, and so forth.
It is also noted that while portions of the following description are cast in terms of VHSIC hardware description language (VHDL), other hardware description languages such as Verilog® may be used to describe various embodiments of the invention with equal success. Furthermore, while an exemplary Synopsys® synthesis engine such as the Design Compiler 2000.05 (DC00) is used to synthesize the various embodiments set forth herein, other synthesis engines such as Buildgates® available from, inter alia, Cadence Design Systems, Inc., may be used. IEEE std. 1076.3-1997, IEEE Standard VHDL Synthesis Packages, describe an industry-accepted language for specifying a Hardware Definition Language-based design and the synthesis capabilities that may be expected to be available to one of ordinary skill in the art.
The memory interface of the present invention has been conceived to enable, inter alia, DSP macro functions and peripherals to interface with another processor core using a simple and standard methodology. Close integration with predefined VLSI functions increases the ability to satisfy demanding applications and meet emerging industry standards, such as those relating to so-called “3G” applications. For certain high-speed communications tasks, only custom DSP and input/output (I/O) functions can meet the processing demands. This concept is illustrated in
The extensible nature of certain processor cores (e.g., the Applicant's “ARC” core) and associated XY memory allow DSP and I/O functions to be tightly coupled for such demanding applications. Using the apparatus and methodology of the present invention, the DSP core(s) effectively become part of the parent processor core instruction set, and I/O peripherals have direct memory access (DMA) to the processor core.
Furthermore, many algorithmically optimized DSP core designs exist. Combining dedicated hardware functional performance and software flexibility within the same IC advantageously provides the most cost effective and shortest time to market for new product development.
Description of Interface
Referring now to
The number of function ports 204 (and hence macro functions 210) is determined by the algorithmic needs of a particular application, and the necessity for hardware acceleration in that application. The number of memory ports 202 (and hence memory banks 214) is determined by the virtual flow of data between macro function blocks, the latter equivalent to a macro function block processing pipeline under CPU control. If a macro block 210 is processing data from a peripheral device (such as shown in
The memory ports 202 of the apparatus of
One embodiment of the arbitration controller logic is described. The arbitration controller 208 comprises a multiplexer adapted to select between burst, direct memory interface (DMI) devices, debug (not shown) functions, and the processor. The construction and operation of multiplexer devices are generally well known in the semiconductor arts, and accordingly not described further herein. The multiplexer of the present invention, however, is controlled by logic which provides the following priority structure: (i) the burst address is selected with the highest priority; (ii) external device permission to access the memory of the bank is given next priority; (iii) the debug channel is selected when the parent processor core (e.g., ARC) is halted, and the host device attempts to access the XY memory; and (iv) the processor source and destination operand busses are otherwise selected if appropriate. It will be recognized that other priority structures may be implemented consistent with the invention, however.
The function ports 204 comprise the interface of the memory interface 200 with the IC functions 210. All data, control, and clock signals are routed through the function ports 204. A synchronous protocol, described in detail herein with respect to
The function controllers 206 comprises the control, status, and test registers (see Tables 4–6 below) associated with each of the IC functions 210. The function controllers also include an interface (as illustrated in the exemplary configuration of
The interface 200 of the invention further utilizes a data transfer “fabric” which interconnects the memory ports 202 with the function ports 204, thereby facilitating data distribution within the interface. In the embodiment illustrated in
Using the aforementioned crossbar arrangement, each IC function 210 is connected through the interface 200 to a bank 214 of the memory array 212, and multiple functions/banks may be connected simultaneously. In the illustrated embodiment, the memory array 212 comprises XY memory. Such memory may comprise, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double-data rate (DDR) SDRAM, embedded/flash memory, or any other type of memory suitable for the desired application. Such memory devices are well known in the semiconductor arts, and accordingly will not be described further herein. The determination of which memory bank 214 in the array 212 is accessed is made either by (i) a control register in processor core auxiliary register space; or (ii) the instruction operand (e.g. “FFT 2” of the aforementioned ARC core). For example, in the case where the IC function comprises a DSP, the individual functions associated with the DSP can access any of the XY memory banks 214 in the array 212 for intermediate calculations and results. In one embodiment of the invention, the XY memory is implemented as two pages of memory, and adapted such that two operand sources may be provided simultaneously. Alternatively, provision may be made for selection between one of the two pages of memory at any one time if desired.
It is noted that different DSP cores (or other types of processor cores) will generally have varying interface, control and memory requirements. The interface 200 of the present invention advantageously provides the designer with the ability to integrate cores of various configurations directly with the parent processor core (e.g., extensible ARC processor) instruction and operand decode mechanism, auxiliary register, and on-core memory resources. The chip/system designer may choose to either to add an HDL “wrapper” around the DSP or core to translate signals, buffer memory interfaces, and synchronize clock signals, or alternatively modify the “soft” DSP core implementation to meet the specification associated with the memory interface 200, as described below with respect to
Referring now to
ld %r0, #CONTROL—WORD
sr %r0, [macro—control]
;load the control word into auxiliary reg.
ld %r0, #BANK
go—macro 0, %r0
;source operand contains bank to act on
lr %r0, [macro—status]
Copyright © 2001 ARC International plc. All rights reserved.
As illustrated in
As illustrated in the example of
In terms of operation, the functions of the DSP core 302 (or other IC function in communication with the interface 200) may, if desired, be initiated by the processor core (e.g. ARC™) pipeline stage 2 instruction decode, and also may optionally use the operand value. Other schemes of DSP core or peripheral initiation may also be used consistent with the invention. For example, it is also possible to initiate and control the DSP core or IC function using one or more control/status registers within the auxiliary space associated with the parent processor.
It is also noted that one or more XY memory banks 214 within the array 212 can advantageously be filled by a “burst” mode load while DSP functions execute on other memory banks. The memory interface 200 and the X/Y memory burst control unit (not shown) arbitrate between accesses. The burst control unit provides direct memory access (DMA) between the main memory and the XY memory system. Its functionality includes the ability to transfer blocks of data, and in one embodiment is integrated with the existing XY system. Note also that the arbitration unit of the present invention includes logic to arbitrate between the processor, an external DSP core (via DMI), host debug port (also not shown) and the parent processor, as previously described.
In one embodiment, the occupied memory resource is “locked out” by one access to another using a first-in-time method (i.e., whichever access is initiated first will lock the other access out until completed), as illustrated below:
ld %r0, #CONTROL—WORD sr %r0, [macro—control] ;load the control word into auxiliary reg. go—macro 0, %r0 ;source operand contains bank to act on . . . . mov %r0, x0—u Copyright © 2001 ARC International plc. All rights reserved.
In the foregoing example, the move (mov) instruction is attempting to transfer data from XY memory into a core register. Two arbitration solutions are possible: (i) either stall the move operation until the macro function completes, or (ii) with additional control logic, stall the macro function and allow processor access to a non-conflicting memory region.
It will be recognized, however, that other types of memory arbitration of the type well known in the art may be utilized to provide non-conflicting memory resource access, round-robin or prioritized arbitration with time division, queued or packetized transfer.
If either the aforementioned burst mode or DSP core function have control over X/Y memory, then “read or “write” operations by the parent processor core to that memory bank will be invalid, but this will not stall the processor core, as block transfers are, in the present embodiment, permitted to take multiple cycles. Hence, in this embodiment, the programmer has the responsibility of ensuring that such automated memory accesses, once initiated, have completed, although other mechanisms for ensuring memory access operation completion may conceivably be used. The following shows a polled solution to invalid parent processor XY access during burst mode:
sr [burst—control],#INITIATE—BURST ;DMA data into XY memory. . ;No access to same XY . bank here . . Wait: ; lr %r0, [burst—status] bne Wait ;Wait for DMA to complete mov %r0, x0—u ;XY access allowed Copyright © 2001 ARC International plc. All rights reserved.
Data Transfer Protocol
When the DSP core 302 or I/O device 404 (
The signal set associated with the exemplary interface 600 of
In the present invention, the control signals used to initiate the macro function are duplicated in one or more control registers. Specifically, in one embodiment, the signals are connected such that a “write” operation to the control register in auxiliary space is registered as a valid command as if correct in stage 2 of the processor pipeline. This ability, inter alia, facilitates the testing of the macro block through the host interface, as described below in greater detail. As auxiliary registers will be accessible from the host interface, this design feature advantageously ensures that the function can be tested. For example, a test sequence might write an input test vector into XY memory, initiate the macro function, and then compare returned results against a known vector. This process is depicted graphically in
Additional auxiliary registers may be used for test purposes as well. For example, in Applicant's ARC core, four test registers are configured for each function port by default. Specifically, if a macro block is connected to a peripheral device, the four test registers can be used to simulate the action of that peripheral under software control. Comparison of transform results in memory to the known stimulus can therefore be achieved for validation of the correct functioning of the macro block 210, advantageously without having to generate real-world stimuli. Other uses of the test registers are possible depending on the testing/operational requirements. It will also be recognized, however, that such additional auxiliary registers are optional, and may be specified in any number desired by the programmer/designer as allowed by the hardware constraints.
In the present embodiment, a number of read/write registers associated with each function port are provided. A default value is normally set, but as with the auxiliary registers, this number may vary. These read/write registers are used for control and data requirements specific to the function associated with the function port, such as, for example, error reporting such as internal data saturation of a fast fixed-point FFT block, status of a connected peripheral, etc.
One or more control registers are also provided. A basic requirement of the control register in the present invention is that power control and external function reset capabilities are provided. This reset (or other control) forces the function to release the memory bank back to the parent processor core. Interrupt control is provided and enabled by the control register, but the IC function also reports internal function status to the processor core using flags.
Tables 4–6 list registers used within the exemplary interface 600 of
Table 6 lists test/debug registers within the interface 600; four registers are provided in the present embodiment for, inter alia, function specific testing and debug capability. For example, as previously described, if a macro block is connected to a peripheral device the test registers might be used to simulate the action of that peripheral under software control, with comparison of transform results in memory to the known stimulus without having to generate real-world stimuli.
Data read/write bus from custom function.
Address bus from custom function. Bus size
depends on bank size.
Signal from custom function selects X or Y
bank for read or write.
Signal from custom function selects 16 or 32-
bit addressing and data bus mode.
Signal from custom function requests read or
Signal from custom function requests XY bank
Memory Request/Grant Signals
System clock output from ARC Memory
Memory request signal from custom function.
Memory grant signal from ARC Memory
Data strobe signal from custom function.
Register Control Signals
Control signals output from ARC Memory
Interface control/status register.
Status signals from custom function.
Interrupt signals from custom function (enabled
in control/status register.
ARC state 2 instruction decode (via ARC
Memory Interface) used to initiate function
ARC state 2 operand (via ARC Memory
Interface) used for basic function parameters.
TABLE 4 Register Control Signals Signal Description DMI—CTRLx Write: IRQ enable, reset, power, run/stop, clear error, test mode, free bits.... DMI—Opx Write: Set operand for function initiation via DMI—CTRLx. Read: An error code may be returned by a read.
1. Default bit positions are defined in the implementation specification.
Representative Bit Positions
2. An “x′, in the register name specifies the function to which the register applies. All registers of the illustrated embodiment are 32-bits.
General Purpose Registers
Function specific read/write register.
Function specific read/write register.
Function specific read/write register.
Function specific read/write register.
TABLE 6 Test/debug Registers Signal Description DMI—DBGOx Function specific read/write test/debug register. DMI—DBGOx Function specific read/write test/debug register. DMI—DBGOx Function specific read/write test/debug register. DMI—DBGOx Function specific read/write test/debug register.
It is noted that while the foregoing embodiment described a specific number of signals and registers associated with these signals, variations in the configuration of the interface, including the number and function of signals, and/or the number of registers, may be employed depending on the specific application and needs of the designer/programmer.
Referring now to
As illustrated in
It will be appreciated by one skilled in the art that the processor of
Furthermore, multiple macro blocks may be active as a “macro pipeline” controlled by the CPU as illustrated in
function0(bank[(cycle+0)%BANKS]); /* Initiate functions */
while(all—functions—not—complete); /* Wait */
Copyright © 2001 ARC International plc. All right reserved.
Referring now to
Next, in step 1004, the number of control and other registers needed for the interface is set based on the function port configuration. In one exemplary embodiment, a library of macro blocks with compatible interfaces is instantiated in the design by the (e.g. the semiconductor synthesis and design software manufactured by the Assignee hereof, and described in detail in Assignee's co-pending U.S. patent application Ser. No. 09/418,663, previously incorporated herein). Under such approach, the aforementioned software has knowledge of the block's requirements, and can instantiate the interface block appropriately.
The interface protocol is then specified in step 1006. One exemplary synchronous protocol is described herein with reference to
Referring now to
The memory configuration (i.e., use of memory interface and number of memory ports and function ports) is first specified by the user (step 1120). The system builder script is then invoked (step 1122) to (i) create a working directory of the user files, and (ii) copy files, including VHDL for macro functions and memory interface as required from the master database. The selected files are also customized as required to configure the system as selected by the user. The structural VHDL is then generated per step 1124. A simulation makefile and a synthesis script are then generated (step 1126). The designer then simulates or synthesizes the design (including memory interface and macro functions) per steps 1128 and 1130, respectively.
The memory interface description is next provided per step 1206. In step 1208, the parent processor parameters such as cache size, extension instructions, and type of build (e.g., system versus core only) is selected. The memory configuration (i.e., use of memory interface and number of memory ports and function ports) is also specified. The system builder script is then invoked (step 1210) to (i) create a working directory of the user files, and (ii) copy files, including VHDL for modules and extensions, as required from the master database. One of the copied files in the present example comprises the memory interface file, while another comprises that for the selected “soft” macro functions previously identified for the build by the user. The selected files are also customized to configure the system as selected by the user. The structural VHDL is then generated per step 1212. A simulation makefile and a synthesis script are then generated (step 1214). The designer then simulates or synthesizes the design (including extended core, memory interface, and user-configured macro functions) per steps 1216 and 1218, respectively. Note that in contrast to the method of
It will be recognized that while certain aspects of the invention are described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods of the invention, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the invention disclosed and claimed herein.
While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the invention. The foregoing description is of the best mode presently contemplated of carrying out the invention. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles of the invention. The scope of the invention should be determined with reference to the claims appended hereto.
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|U.S. Classification||710/240, 710/316, 710/305, 710/317|
|International Classification||G06F9/38, G06F13/16, G06F13/14, G06F13/38, G06F12/00|
|Cooperative Classification||G06F15/7839, G06F13/1605, G06F13/1647, G06F9/3885, G06F13/16, G06F13/4022|
|European Classification||G06F9/38T, G06F13/16, G06F13/16A6|
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