US 6989575 B2
Arrays of microelectronic elements such as magnetorestive memory elements and FET's, including dual-gate FET's, are fabricated by methods involving a host wafer and a first wafer on which part of the microelectronic elements are separately formed. Conductive elements such as metal-filled vias are formed in the host wafer and extend to its surface. Hydrogen ions are implanted at a selected depth in the first wafer. After formation of selected portions of the microelectronic elements above the hyrogen ion implantation depth of the first wafer, the latter is bonded to the surface of the host wafer so that complementary parts of the two wafers can join to form the microelectronic elements. The first wafer is fractured at the hydrogen ion implantation depth and its lower portion is removed to allow for polishing and affixing of electrodes thereon.
1. An array of microelectronic elements comprising:
a substrate of semiconductor material;
a lower layer of dielectric material disposed with a lower surface in contact with said substrate and an upper surface in spaced adjacency thereto;
a pattern of mutually electrically isolated conducting regions disposed within said lower layer of dielectric material, said conducting regions extending to said upper surface of said lower layer;
an upper layer of dielectric material disposed with a lower surface thereof in contact with and bonded to said upper surface of said lower layer;
a plurality of nodes of semiconductor material disposed within said upper layer of dielectric material, each of said nodes being in electrical contact with only one of said conducting regions at said upper surface of said lower layer; and
a bonding promoting layer formed on said lower layer of dielectric material, said bonding promoting layer bonding said lower surface of said upper layer of dielectric material to said upper surface of said lower layer,
wherein each conducting region comprises:
a metal conductor; and
a via which is filled with a diffusion barrier material, said diffusion barrier material extending between said metal conductor and a node in said plurality of nodes and electrically connecting said metal conductor with said node.
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15. A microelectronic element array comprising:
a semiconductor substrate;
a first dielectric layer formed on said substrate;
a plurality of electrically isolated conductive regions disposed within said first dielectric layer, each conductive region comprising:
a metal conductor; and
a conductive via which is filled with a diffusion barrier material formed on said metal conductor;
a second dielectric layer having a lower surface which is bonded to an upper surface of said first dielectric layer;
a plurality of semiconductor nodes formed in said second dielectric layer, each semiconductor node contacting said conductive via and being electrically connected to said metal conductor by said conductive via; and
a bonding promoting layer formed on said first dielectric layer, said bonding promoting layer bonding said lower surface of said second dielectric layer to said upper surface of said first dielectric layer,
wherein said diffusion barrier material extends between said metal conductor and a node in said plurality of nodes.
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a plurality of magnetic tunnel junction (MTJ) elements, each MTJ element in electrical contact with a diode in said plurality of monocrystalline semiconductor diodes.
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24. A microelectronic element array comprising:
a first dielectric layer formed on a substrate;
at least one electrically isolated conductive region formed in said first dielectric layer, said at least one conductive region comprising:
a metal conductor; and
a conductive via which is filled with a diffusion barrier material formed on said metal conductor;
a second dielectric layer which is bonded to said first dielectric layer; and
at least one semiconductor node formed in said second dielectric layer, said at least one semiconductor node being formed on and contacting said at least one conductive region; and
a bonding promoting layer formed on said first dielectric layer, said bonding promoting layer bonding a lower surface of said second dielectric layer to an upper surface of said first dielectric layer,
wherein said diffusion barrier material extends between said metal conductor and said at least one semiconductor node and electrically connects said metal conductor to said at least one semiconductor node.
The present Application is a Divisional Application of U.S. patent application Ser. No. 09/427,251, filed on Oct. 26, 1999 now U.S. Pat No. 6,391,658.
The Government of the United States of America has rights in this invention pursuant to Contract No. MDA972-96-C-0030 awarded by the Defence Advanced Research Projects Agency.
The present invention relates to methods for forming arrays of microelectronic elements, such as magnetoresistive memory elements and FET's (field effect transistors).
An embodiment of the present invention relates to a nonvolatile memory storage array for computers and portable electronics, fabricated on a Si wafer substrate with integrated Si electronics, and using a magnetoresistive structures in each memory cell. Specifically in relation to magnetoresistive memory elements, an embodiment of this invention concerns a new structure for a memory cell consisting of a magnetic tunnel junction and a diode, similar to the cell described in U.S. Pat. No. 5,640,343 by Gallagher, et al. This invention also includes a fabrication method for said new structure.
According to an embodiment of the present invention, the new structure described herein comprises a single crystal Si diode located atop a conducting “via” (a metallic or other conducting channel through a lower conductivity layer of Si or the like) of small crossectional area, and further comprises a magnetic tunnel junction (MTJ) located atop said diode. The novel fabrication method uses a wafer bonding process to place such a single crystal Si (SCS) diode atop the conducting via.
Previously, magnetic memory cells consisting of a magnetic tunnel junction and a diode (herein called “MagRAM”) have been described in U.S. Pat. No. 5,640,343 by Gallagher, et al (IBM) and also in U.S. Pat. No. 5,734,605 by Zhu, et al (Motorola). Arrays of said memory cells were described in both of these patents. Generally, each MagRAM memory cell contains two magnetic regions separated by a thin dielectric layer through which electron tunnelling occurs and the dielectric is known as the tunnel barrier. A first magnetic layer has a fixed magnetization axis and serves as a magnetic reference layer and is composed of relatively permanent (“hard”) magnetic materials. The tunnel barrier is sandwiched between the first and second magnetic layers. The second magnetic layer is relatively easily switched between 2 magnetic states, which are aligned parallel and anti-parallel to the magnetic axis of the first reference layer. The first and second magnetic layers and the tunnel barrier comprise a trilayer MTJ, and the electrical resistance of said MTJ has two well defined values corresponding to the two alignment states of the second (“free”) magnetic layer. Information storage is performed by assigning 0 and 1 to the two electrical resistance states of each cell.
Arrays of MTJ memory cells containing upwards of 1,000 cells are very useful. An extremely high information storage density suitable for very large scale integrated (VLSI) circuits is possible using a very compact (small area) MTJ cell design that is vertically integrated, and wherein each cell consists of an MTJ and a diode in a vertical stack located at the intersection of two metal thin film wires, and the MTJ plus diode stack electrically contacts each of said thin film wires. This vertically integrated memory cell occupies a minimum area of the VLSI chip yielding the maximum information density, and is known as the “crosspoint architecture”.
In such a crosspoint architecture memory cell, a diode is located atop the bottom metal conductor (row line). An MTJ is located atop the diode, electrically in series with the diode. The top metal conductor is above and in contact with the MTJ. When the resistance of the cell is sensed, the sense current flows through only one memory cell, instead of through N cells as in conventional series architecture magnetoresistive memories. The signal-to-noise ratio (SNR) of the crosspoint array containing N elements is N times larger than the conventional array containing N elements. Alternatively, the SNR can be the same and the sense power of the crosspoint architecture can be reduced by a factor of N×N (or N squared).
The sensing operation is a measurement of resistance, and any series resistance that is similar in magnitude to the MTJ resistance detracts from the signal. Thus, the diode should have a small series resistance, and this diode resistance should be uniform throughout an array of many diodes (memory cells). The diode atop the row line may be formed in a small lithographically defined piece of semiconductor such as Si, and furthermore this Si piece (“island”) may consist of 1 large crystal grain (single crystal or monocrystalline), or may consist of multiple smaller crystal grains (polycrystalline). The polycrystalline state is typical of thin film semiconductors.
The advantages of using a single crystal Si (SCS) diode (as opposed to a thin film diode) in the MagRAM cell, and in high density arrays of these cells, are improved electrical performance, and more uniform electrical characteristics in large arrays of diodes (e.g. 1,000×1,000 arrays). Specifically, the electrical performance of an SCS diode includes a lower series resistance (higher forward current density) and a higher rectification (ratio of Forward/Reverse bias currents). With a lower diode resistance, a given value of the sense current during the Read operation requires a lower voltage, and hence the power consumption is lower. Also, a higher diode conductivity interferes less with the Read operation, when the conductivity of the MTJ device used to store the data is sensed. With a higher diode rectification, less current is passed in the reverse bias direction, and so overall power consumption of the array is reduced.
The present invention broadly provides a method of forming an array of microelectronic elements, said method comprising the steps of:
Preferably, step a) comprises a further step of forming a semiconductor device in the aforesaid semiconductor layer above each of said conducting regions of said metal conductors.
According to a preferred embodiment, the aforesaid microelectronic elements are magnetoresistive memory elements and the method comprising the further step of forming an MTJ structure in electrical contact with said semiconductor layer above each of said conducting regions of said metal conductors. The semiconductor device can be a diode which is in electrical contact with the magnetoresistive memory element.
According to another preferred embodiment, step a) comprises a further step of forming a field effect transistor at positions in said semiconductor layer which overlie said conducting regions of said metal conductors, each of said conducting regions (e.g. metal-filled via) serving as a first gate electrode of said field effect transistor. Moreover, step a) may then comprise a further step of forming a first oxide layer on said first surface of said first wafer before step c). Advantageously, a second oxide layer may be formed on the fracture surface, and further, a second gate electrode may formed to overlie each such field effect transistor (FET).
The invention further provides an array of microelectronic elements comprising:
As will be understood, each of the nodes may comprise a semiconductor device, such as a diode. Alternatively, the microelectronic elements may comprise magnetoresistive memory elements each comprising a said diode and an MTJ structure.
Desireably, each semiconductor device may be a field effect transistor comprising a first gate electrode in contact with one of said conducting regions at said upper surface of said lower layer
Moreover, a first insulating layer may be disposed over an upper surface of said upper layer and a second insulating layer may be formed over said upper surface of said lower layer, and a second gate electrode may be deposited upon the aforesaid first insulating layer above each field effect transistor.
It is a purpose of the present invention to combine the stated advantages of an SCS diode with the highest density (smallest area) crosspoint MagRAM cell. It is preferable to locate the SCS diode in the MagRAM cell atop a via of small area, rather than located directly atop the word line.
One advantage of the structure of the present invention using a filled via is reliability. The structure of the present invention is more reliable because this structure prevents a solid state reaction between the Si diode and the metal comprising the word line, by using a conductive diffusion barrier material to fill the via. Suitable diffusion barrier materials include W, TiN, TaN, and the TaSiN ternary alloys. Without such a barrier, only refractory metal word lines which are relatively unreactive with Si may be used. A second advantage of the structure of the present invention using a filled via is enabling a lower resistance metal (copper) to comprise the word line. The Refractory metal word lines have a relatively high resistance, and therefor only small arrays of memory elements can be made. Using the diffusion barrier structure of this invention, higher conductivity metals including Cu and Al may be used to form the word line, and larger memory arrays can be made. Both Cu and Al react with Si at low temperatures if a barrier is not placed between the metal and Si. In the present structure, the metal via height is minimized to allow close proximity of the lower conductor (word line) and the MTJ.
It is an object of the present invention to disclose a stepwise method to make the structure of the present invention. This method consists of the following general steps: A first semiconductor wafer (for example Si) is prepared containing a p/n junction diode consisting of thin n-type and p-type Si layers, and specifically the first wafer has a smooth first surface. Furthermore, the first wafer also contains a zone below the first surface and below the p/n junction diode containing implanted atoms of hydrogen or a noble gas, which zone becomes a fracture zone upon heating the wafer. A second semiconductor wafer, optionally containing resistance sensing circuits, is prepared containing spaced apart metal conductors (word lines) with spaced apart filled via holes atop said metal conductors. Said second wafer contains a second surface, the surface area of which consists of a smooth dielectic layer containing spaced apart filled vias. The first surface of the first wafer and the second surface of the second wafer are placed in intimate contact in a clean environment, and held in intimate contact during heating of the wafer pair. Upon heating, the first wafer fractures into a layer of Si which is very thin (<0.5 micron thick) and is compliant to the second wafer and becomes bonded onto the second surface of the second wafer, whereupon the bulk of the first wafer is removed. The thin compliant Si layer containing the p/n junction becomes functionally the top of the second wafer. Individual memory elements are then fabricated on the second wafer located atop each of the filled vias, said memory elements consisting of a diode in series with an MTJ. Each diode is formed in the thin bonded Si layer. Each MTJ is located atop a diode, and each diode is atop a filled via. The memory array is completed by surrounding all the memory elements with a bulk dielectric (polymer, or deposited oxide or nitiride of Si), and then forming a second set of spaced apart metal conductors (bit lines) atop the dielectric and electrically contacting the MTJ's. The second set of metal conductors is approximately perpendicular to the word line conductors, forming the previously mentioned “crosspoint” architecture which yield a very high information storage density.
Fabrication of the inventive structures is now described in reference to the Figures. The fabrication method of the present invention makes use of a process known as the Smart-CutR (a trademark of the Soitec company) process, details of which have been described in many publications, for example in BASIC MECHANISMS INVOLVED IN THE SmartCutR PROCESS, by B. Aspar and co-workers, appearing in Microelectronic Engineering 36 (1997) p. 233.
Briefly, the Smart-CutR process uses implantation of hydrogen or noble gas ions into a first Si wafer and wafer bonding techniques to transfer a thin Si layer and bond said thin Si layer onto a second Si wafer substrate. Optionally, the second wafer may contain other layers or patterned structures. Specifically, the first wafer is implanted with H+ ions at 95 keV energy and dose from 0.3 to 1×1017 cm−2. Inside a clean environment (clean room), the first and second wafers are placed in intimate contact, both of said wafers having atomically smooth surfaces on the contacting surfaces. When the assembly of first and second wafers in intimate contact is heated to 400–600° C., the 1st wafer fractures at the H implanted zone, and a thin Si layer is bonded to the second wafer. Due to the roughness of the new surfaces formed by fracture, the two wafers are easily separated and the bulk of the first wafer can be re-used. The transferred thin Si layer becomes structurally a part of the second wafer, and the new, fractured, surface of the transferred thin Si layer is polished.
Details of the method of the present invention are now described.
After implantation steps 1. and 2, the 1st wafer is annealled at about 1,000° C. for a few seconds to activate the dopants. This completes the high temperature processing steps.
3. High energy H+ implantation to form the H+-implanted zone 1.
To make the thinnest possible diode structure, low implantation energy is used and the thermal activation cycle is minimized, and a sacrificial silicon oxide layer may be left on the surface 4 a during H+ implantation. Alternatively, solid source diffusion from a deposited layer containing Boron may be used to convert the p-type layer.
The bulk of the first Si wafer 4 is not affected by these implantation steps.
Next, the H+ or other ions are implanted through surface 4 a to a planar region 1 at a selected depth within wafer 4. After implantation, any remaining sacrificial oxide layer is removed.
A specific feature of this invention is to place a bonding promoter layer, 12, at the second surface of the 2nd wafer 17. For example, a thin layer of a glass having a softening temperature of 400–500° C. is the bonding promoter. Below the promoter layer 12 is a dielectric 10, such as deposited SiO2.
Alignment marks are present on the host wafer 17 for use in subsequent lithography steps described below in reference to
The structure shown in
The Si layer has 2 components, the n-type layer, 3, and a p-type Si layer, 2.
The structure of
The MTJ structure is next fabricated. One example of the process to fabricate the MTJ is described in detail in MICROSTRUCTURED MAGNETIC TUNNEL JUNCTIONS, by W. J. Gallagher et al, in JOURNAL OF APPLIED PHYSICS 81, 1997, p. 3741.
Summarizing an example of the general MTJ fabrication method, the MTJ consists of a “fixed” magnet layer, a thin dielectric tunnel barrier, and a “free” (or switchable) magnetic layer. Herein, this MTJ structure is called the trilayer MTJ structure, and the abbraviation Py means “permalloy” which is Fe19Ni81. The magnetic layers are deposited by sputter deposition in an applied magnetic field, and this field axis defines the magnetic axis of the films. To deposit the MTJ trilayer structure, the following 3 steps may be employed.
First, a permanent magnet layer about 20 nm thick is deposited to form the “fixed” magnet, and this layer may be composed of sub-layers. For example, the permanent magnet layer may be composed of a seed layer of 5 nm thick Py is to act as a template layer, under a 10 nm antiferromagnetic layer 10 nm under a ferromagnetic “fixed” layer of 10 nm thick Py of iron manganese alloy (FeMn).
Second, a thin dielectric layer of 1–3 nm thickness is deposited to serve as a tunnel barrier. This layer must be free of holes or other defects, and must be uniform in thickness in order to fabricate MTJ's with uniform resistance, and must be as thin as possible. For example, a layer of Al2O3 about 1.5 nm thick is an optimum dielectric layer.
Third, a “soft” magnetic layer, which may be readily switched between 2 magnetic states is deposited. For example 10 nm of Py forms an optimum switchable magnet. Optionally, there may be conductive electrode layers of about 10–50 nm thickness above the tri layer MTJ structure.
In this process, the entire MTJ stack and the Si layers are to be patterned using a single lithographic mask step, but using different RIE etch chemistries and the thin magnetic layers may be etched using ion beam etching.
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The present invention has been described with reference to preferred embodiments in order to facilitate a better understanding of the invention. However, those skilled in the art will recognize that the invention can be embodied in various ways without departing from the scope and spirit of the invention as set forth in the appended claims.